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749cf76c CD |
1 | /* |
2 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
3 | * Authors: Rusty Russell <rusty@rustcorp.com.au> | |
4 | * Christoffer Dall <c.dall@virtualopensystems.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License, version 2, as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
18 | */ | |
d06a5440 MZ |
19 | |
20 | #include <linux/bsearch.h> | |
5b3e5e5b | 21 | #include <linux/mm.h> |
749cf76c | 22 | #include <linux/kvm_host.h> |
1138245c | 23 | #include <linux/uaccess.h> |
5b3e5e5b CD |
24 | #include <asm/kvm_arm.h> |
25 | #include <asm/kvm_host.h> | |
26 | #include <asm/kvm_emulate.h> | |
27 | #include <asm/kvm_coproc.h> | |
8034699a | 28 | #include <asm/kvm_mmu.h> |
5b3e5e5b CD |
29 | #include <asm/cacheflush.h> |
30 | #include <asm/cputype.h> | |
31 | #include <trace/events/kvm.h> | |
4fe21e4c RR |
32 | #include <asm/vfp.h> |
33 | #include "../vfp/vfpinstr.h" | |
749cf76c | 34 | |
01630ab8 | 35 | #define CREATE_TRACE_POINTS |
5b3e5e5b CD |
36 | #include "trace.h" |
37 | #include "coproc.h" | |
38 | ||
39 | ||
40 | /****************************************************************************** | |
41 | * Co-processor emulation | |
42 | *****************************************************************************/ | |
43 | ||
b1d4cb69 MZ |
44 | static bool write_to_read_only(struct kvm_vcpu *vcpu, |
45 | const struct coproc_params *params) | |
46 | { | |
47 | WARN_ONCE(1, "CP15 write to read-only register\n"); | |
48 | print_cp_instr(params); | |
49 | kvm_inject_undefined(vcpu); | |
50 | return false; | |
51 | } | |
52 | ||
53 | static bool read_from_write_only(struct kvm_vcpu *vcpu, | |
54 | const struct coproc_params *params) | |
55 | { | |
56 | WARN_ONCE(1, "CP15 read to write-only register\n"); | |
57 | print_cp_instr(params); | |
58 | kvm_inject_undefined(vcpu); | |
59 | return false; | |
60 | } | |
61 | ||
c27581ed CD |
62 | /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ |
63 | static u32 cache_levels; | |
64 | ||
65 | /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ | |
66 | #define CSSELR_MAX 12 | |
67 | ||
73891f72 VK |
68 | /* |
69 | * kvm_vcpu_arch.cp15 holds cp15 registers as an array of u32, but some | |
70 | * of cp15 registers can be viewed either as couple of two u32 registers | |
71 | * or one u64 register. Current u64 register encoding is that least | |
72 | * significant u32 word is followed by most significant u32 word. | |
73 | */ | |
74 | static inline void vcpu_cp15_reg64_set(struct kvm_vcpu *vcpu, | |
75 | const struct coproc_reg *r, | |
76 | u64 val) | |
77 | { | |
fb32a52a MZ |
78 | vcpu_cp15(vcpu, r->reg) = val & 0xffffffff; |
79 | vcpu_cp15(vcpu, r->reg + 1) = val >> 32; | |
73891f72 VK |
80 | } |
81 | ||
82 | static inline u64 vcpu_cp15_reg64_get(struct kvm_vcpu *vcpu, | |
83 | const struct coproc_reg *r) | |
84 | { | |
85 | u64 val; | |
86 | ||
fb32a52a | 87 | val = vcpu_cp15(vcpu, r->reg + 1); |
73891f72 | 88 | val = val << 32; |
fb32a52a | 89 | val = val | vcpu_cp15(vcpu, r->reg); |
73891f72 VK |
90 | return val; |
91 | } | |
92 | ||
5b3e5e5b CD |
93 | int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run) |
94 | { | |
95 | kvm_inject_undefined(vcpu); | |
96 | return 1; | |
97 | } | |
98 | ||
99 | int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run) | |
100 | { | |
101 | /* | |
102 | * We can get here, if the host has been built without VFPv3 support, | |
103 | * but the guest attempted a floating point operation. | |
104 | */ | |
105 | kvm_inject_undefined(vcpu); | |
106 | return 1; | |
107 | } | |
108 | ||
109 | int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run) | |
110 | { | |
111 | kvm_inject_undefined(vcpu); | |
112 | return 1; | |
113 | } | |
114 | ||
e8c2d99f JA |
115 | static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) |
116 | { | |
117 | /* | |
2d1d841b MZ |
118 | * Compute guest MPIDR. We build a virtual cluster out of the |
119 | * vcpu_id, but we read the 'U' bit from the underlying | |
120 | * hardware directly. | |
e8c2d99f | 121 | */ |
fb32a52a | 122 | vcpu_cp15(vcpu, c0_MPIDR) = ((read_cpuid_mpidr() & MPIDR_SMP_BITMASK) | |
2d1d841b MZ |
123 | ((vcpu->vcpu_id >> 2) << MPIDR_LEVEL_BITS) | |
124 | (vcpu->vcpu_id & 3)); | |
e8c2d99f JA |
125 | } |
126 | ||
127 | /* TRM entries A7:4.3.31 A15:4.3.28 - RO WI */ | |
128 | static bool access_actlr(struct kvm_vcpu *vcpu, | |
129 | const struct coproc_params *p, | |
130 | const struct coproc_reg *r) | |
131 | { | |
132 | if (p->is_write) | |
133 | return ignore_write(vcpu, p); | |
134 | ||
fb32a52a | 135 | *vcpu_reg(vcpu, p->Rt1) = vcpu_cp15(vcpu, c1_ACTLR); |
e8c2d99f JA |
136 | return true; |
137 | } | |
138 | ||
139 | /* TRM entries A7:4.3.56, A15:4.3.60 - R/O. */ | |
140 | static bool access_cbar(struct kvm_vcpu *vcpu, | |
141 | const struct coproc_params *p, | |
142 | const struct coproc_reg *r) | |
143 | { | |
144 | if (p->is_write) | |
145 | return write_to_read_only(vcpu, p); | |
146 | return read_zero(vcpu, p); | |
147 | } | |
148 | ||
149 | /* TRM entries A7:4.3.49, A15:4.3.48 - R/O WI */ | |
150 | static bool access_l2ctlr(struct kvm_vcpu *vcpu, | |
151 | const struct coproc_params *p, | |
152 | const struct coproc_reg *r) | |
153 | { | |
154 | if (p->is_write) | |
155 | return ignore_write(vcpu, p); | |
156 | ||
fb32a52a | 157 | *vcpu_reg(vcpu, p->Rt1) = vcpu_cp15(vcpu, c9_L2CTLR); |
e8c2d99f JA |
158 | return true; |
159 | } | |
160 | ||
161 | static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) | |
162 | { | |
163 | u32 l2ctlr, ncores; | |
164 | ||
165 | asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); | |
166 | l2ctlr &= ~(3 << 24); | |
167 | ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1; | |
9cbb6d96 MZ |
168 | /* How many cores in the current cluster and the next ones */ |
169 | ncores -= (vcpu->vcpu_id & ~3); | |
170 | /* Cap it to the maximum number of cores in a single cluster */ | |
171 | ncores = min(ncores, 3U); | |
e8c2d99f JA |
172 | l2ctlr |= (ncores & 3) << 24; |
173 | ||
fb32a52a | 174 | vcpu_cp15(vcpu, c9_L2CTLR) = l2ctlr; |
e8c2d99f JA |
175 | } |
176 | ||
177 | static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) | |
178 | { | |
179 | u32 actlr; | |
180 | ||
181 | /* ACTLR contains SMP bit: make sure you create all cpus first! */ | |
182 | asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr)); | |
183 | /* Make the SMP bit consistent with the guest configuration */ | |
184 | if (atomic_read(&vcpu->kvm->online_vcpus) > 1) | |
185 | actlr |= 1U << 6; | |
186 | else | |
187 | actlr &= ~(1U << 6); | |
188 | ||
fb32a52a | 189 | vcpu_cp15(vcpu, c1_ACTLR) = actlr; |
e8c2d99f JA |
190 | } |
191 | ||
192 | /* | |
193 | * TRM entries: A7:4.3.50, A15:4.3.49 | |
194 | * R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored). | |
195 | */ | |
196 | static bool access_l2ectlr(struct kvm_vcpu *vcpu, | |
197 | const struct coproc_params *p, | |
198 | const struct coproc_reg *r) | |
199 | { | |
200 | if (p->is_write) | |
201 | return ignore_write(vcpu, p); | |
202 | ||
203 | *vcpu_reg(vcpu, p->Rt1) = 0; | |
204 | return true; | |
205 | } | |
206 | ||
3c1e7165 MZ |
207 | /* |
208 | * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). | |
209 | */ | |
5b3e5e5b CD |
210 | static bool access_dcsw(struct kvm_vcpu *vcpu, |
211 | const struct coproc_params *p, | |
212 | const struct coproc_reg *r) | |
213 | { | |
5b3e5e5b CD |
214 | if (!p->is_write) |
215 | return read_from_write_only(vcpu, p); | |
216 | ||
3c1e7165 | 217 | kvm_set_way_flush(vcpu); |
5b3e5e5b CD |
218 | return true; |
219 | } | |
220 | ||
8034699a MZ |
221 | /* |
222 | * Generic accessor for VM registers. Only called as long as HCR_TVM | |
3c1e7165 MZ |
223 | * is set. If the guest enables the MMU, we stop trapping the VM |
224 | * sys_regs and leave it in complete control of the caches. | |
225 | * | |
226 | * Used by the cpu-specific code. | |
8034699a | 227 | */ |
3c1e7165 MZ |
228 | bool access_vm_reg(struct kvm_vcpu *vcpu, |
229 | const struct coproc_params *p, | |
230 | const struct coproc_reg *r) | |
8034699a | 231 | { |
3c1e7165 MZ |
232 | bool was_enabled = vcpu_has_cache_enabled(vcpu); |
233 | ||
8034699a MZ |
234 | BUG_ON(!p->is_write); |
235 | ||
fb32a52a | 236 | vcpu_cp15(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt1); |
8034699a | 237 | if (p->is_64bit) |
fb32a52a | 238 | vcpu_cp15(vcpu, r->reg + 1) = *vcpu_reg(vcpu, p->Rt2); |
8034699a | 239 | |
3c1e7165 | 240 | kvm_toggle_cache(vcpu, was_enabled); |
8034699a MZ |
241 | return true; |
242 | } | |
243 | ||
acda5430 VM |
244 | static bool access_gic_sgi(struct kvm_vcpu *vcpu, |
245 | const struct coproc_params *p, | |
246 | const struct coproc_reg *r) | |
247 | { | |
248 | u64 reg; | |
3e8a8a50 | 249 | bool g1; |
acda5430 VM |
250 | |
251 | if (!p->is_write) | |
252 | return read_from_write_only(vcpu, p); | |
253 | ||
254 | reg = (u64)*vcpu_reg(vcpu, p->Rt2) << 32; | |
255 | reg |= *vcpu_reg(vcpu, p->Rt1) ; | |
256 | ||
3e8a8a50 MZ |
257 | /* |
258 | * In a system where GICD_CTLR.DS=1, a ICC_SGI0R access generates | |
259 | * Group0 SGIs only, while ICC_SGI1R can generate either group, | |
260 | * depending on the SGI configuration. ICC_ASGI1R is effectively | |
261 | * equivalent to ICC_SGI0R, as there is no "alternative" secure | |
262 | * group. | |
263 | */ | |
264 | switch (p->Op1) { | |
265 | default: /* Keep GCC quiet */ | |
266 | case 0: /* ICC_SGI1R */ | |
267 | g1 = true; | |
268 | break; | |
269 | case 1: /* ICC_ASGI1R */ | |
270 | case 2: /* ICC_SGI0R */ | |
271 | g1 = false; | |
272 | break; | |
273 | } | |
274 | ||
275 | vgic_v3_dispatch_sgi(vcpu, reg, g1); | |
acda5430 VM |
276 | |
277 | return true; | |
278 | } | |
279 | ||
280 | static bool access_gic_sre(struct kvm_vcpu *vcpu, | |
281 | const struct coproc_params *p, | |
282 | const struct coproc_reg *r) | |
283 | { | |
284 | if (p->is_write) | |
285 | return ignore_write(vcpu, p); | |
286 | ||
287 | *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; | |
288 | ||
289 | return true; | |
290 | } | |
291 | ||
b9fb1739 JF |
292 | static bool access_cntp_tval(struct kvm_vcpu *vcpu, |
293 | const struct coproc_params *p, | |
294 | const struct coproc_reg *r) | |
295 | { | |
84135d3d | 296 | u32 val; |
b9fb1739 JF |
297 | |
298 | if (p->is_write) { | |
299 | val = *vcpu_reg(vcpu, p->Rt1); | |
84135d3d AP |
300 | kvm_arm_timer_write_sysreg(vcpu, |
301 | TIMER_PTIMER, TIMER_REG_TVAL, val); | |
b9fb1739 | 302 | } else { |
84135d3d AP |
303 | val = kvm_arm_timer_read_sysreg(vcpu, |
304 | TIMER_PTIMER, TIMER_REG_TVAL); | |
305 | *vcpu_reg(vcpu, p->Rt1) = val; | |
b9fb1739 JF |
306 | } |
307 | ||
308 | return true; | |
309 | } | |
310 | ||
311 | static bool access_cntp_ctl(struct kvm_vcpu *vcpu, | |
312 | const struct coproc_params *p, | |
313 | const struct coproc_reg *r) | |
314 | { | |
315 | u32 val; | |
316 | ||
317 | if (p->is_write) { | |
318 | val = *vcpu_reg(vcpu, p->Rt1); | |
84135d3d AP |
319 | kvm_arm_timer_write_sysreg(vcpu, |
320 | TIMER_PTIMER, TIMER_REG_CTL, val); | |
b9fb1739 | 321 | } else { |
84135d3d AP |
322 | val = kvm_arm_timer_read_sysreg(vcpu, |
323 | TIMER_PTIMER, TIMER_REG_CTL); | |
b9fb1739 JF |
324 | *vcpu_reg(vcpu, p->Rt1) = val; |
325 | } | |
326 | ||
327 | return true; | |
328 | } | |
329 | ||
330 | static bool access_cntp_cval(struct kvm_vcpu *vcpu, | |
331 | const struct coproc_params *p, | |
332 | const struct coproc_reg *r) | |
333 | { | |
334 | u64 val; | |
335 | ||
336 | if (p->is_write) { | |
337 | val = (u64)*vcpu_reg(vcpu, p->Rt2) << 32; | |
338 | val |= *vcpu_reg(vcpu, p->Rt1); | |
84135d3d AP |
339 | kvm_arm_timer_write_sysreg(vcpu, |
340 | TIMER_PTIMER, TIMER_REG_CVAL, val); | |
b9fb1739 | 341 | } else { |
84135d3d AP |
342 | val = kvm_arm_timer_read_sysreg(vcpu, |
343 | TIMER_PTIMER, TIMER_REG_CVAL); | |
b9fb1739 JF |
344 | *vcpu_reg(vcpu, p->Rt1) = val; |
345 | *vcpu_reg(vcpu, p->Rt2) = val >> 32; | |
346 | } | |
347 | ||
348 | return true; | |
349 | } | |
350 | ||
5b3e5e5b CD |
351 | /* |
352 | * We could trap ID_DFR0 and tell the guest we don't support performance | |
353 | * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was | |
354 | * NAKed, so it will read the PMCR anyway. | |
355 | * | |
356 | * Therefore we tell the guest we have 0 counters. Unfortunately, we | |
357 | * must always support PMCCNTR (the cycle counter): we just RAZ/WI for | |
358 | * all PM registers, which doesn't crash the guest kernel at least. | |
359 | */ | |
9b619a8f | 360 | static bool trap_raz_wi(struct kvm_vcpu *vcpu, |
5b3e5e5b CD |
361 | const struct coproc_params *p, |
362 | const struct coproc_reg *r) | |
363 | { | |
364 | if (p->is_write) | |
365 | return ignore_write(vcpu, p); | |
366 | else | |
367 | return read_zero(vcpu, p); | |
368 | } | |
369 | ||
9b619a8f ZH |
370 | #define access_pmcr trap_raz_wi |
371 | #define access_pmcntenset trap_raz_wi | |
372 | #define access_pmcntenclr trap_raz_wi | |
373 | #define access_pmovsr trap_raz_wi | |
374 | #define access_pmselr trap_raz_wi | |
375 | #define access_pmceid0 trap_raz_wi | |
376 | #define access_pmceid1 trap_raz_wi | |
377 | #define access_pmccntr trap_raz_wi | |
378 | #define access_pmxevtyper trap_raz_wi | |
379 | #define access_pmxevcntr trap_raz_wi | |
380 | #define access_pmuserenr trap_raz_wi | |
381 | #define access_pmintenset trap_raz_wi | |
382 | #define access_pmintenclr trap_raz_wi | |
5b3e5e5b CD |
383 | |
384 | /* Architected CP15 registers. | |
240e99cb CD |
385 | * CRn denotes the primary register number, but is copied to the CRm in the |
386 | * user space API for 64-bit register access in line with the terminology used | |
387 | * in the ARM ARM. | |
388 | * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit | |
389 | * registers preceding 32-bit ones. | |
5b3e5e5b CD |
390 | */ |
391 | static const struct coproc_reg cp15_regs[] = { | |
e8c2d99f JA |
392 | /* MPIDR: we use VMPIDR for guest access. */ |
393 | { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32, | |
394 | NULL, reset_mpidr, c0_MPIDR }, | |
395 | ||
5b3e5e5b CD |
396 | /* CSSELR: swapped by interrupt.S. */ |
397 | { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32, | |
398 | NULL, reset_unknown, c0_CSSELR }, | |
399 | ||
e8c2d99f JA |
400 | /* ACTLR: trapped by HCR.TAC bit. */ |
401 | { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32, | |
402 | access_actlr, reset_actlr, c1_ACTLR }, | |
403 | ||
404 | /* CPACR: swapped by interrupt.S. */ | |
405 | { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32, | |
406 | NULL, reset_val, c1_CPACR, 0x00000000 }, | |
407 | ||
8034699a MZ |
408 | /* TTBR0/TTBR1/TTBCR: swapped by interrupt.S. */ |
409 | { CRm64( 2), Op1( 0), is64, access_vm_reg, reset_unknown64, c2_TTBR0 }, | |
410 | { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32, | |
411 | access_vm_reg, reset_unknown, c2_TTBR0 }, | |
412 | { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32, | |
413 | access_vm_reg, reset_unknown, c2_TTBR1 }, | |
5b3e5e5b | 414 | { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32, |
8034699a MZ |
415 | access_vm_reg, reset_val, c2_TTBCR, 0x00000000 }, |
416 | { CRm64( 2), Op1( 1), is64, access_vm_reg, reset_unknown64, c2_TTBR1 }, | |
417 | ||
5b3e5e5b CD |
418 | |
419 | /* DACR: swapped by interrupt.S. */ | |
420 | { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32, | |
8034699a | 421 | access_vm_reg, reset_unknown, c3_DACR }, |
5b3e5e5b CD |
422 | |
423 | /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */ | |
424 | { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32, | |
8034699a | 425 | access_vm_reg, reset_unknown, c5_DFSR }, |
5b3e5e5b | 426 | { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32, |
8034699a | 427 | access_vm_reg, reset_unknown, c5_IFSR }, |
5b3e5e5b | 428 | { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32, |
8034699a | 429 | access_vm_reg, reset_unknown, c5_ADFSR }, |
5b3e5e5b | 430 | { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32, |
8034699a | 431 | access_vm_reg, reset_unknown, c5_AIFSR }, |
5b3e5e5b CD |
432 | |
433 | /* DFAR/IFAR: swapped by interrupt.S. */ | |
434 | { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32, | |
8034699a | 435 | access_vm_reg, reset_unknown, c6_DFAR }, |
5b3e5e5b | 436 | { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32, |
8034699a | 437 | access_vm_reg, reset_unknown, c6_IFAR }, |
6a077e4a MZ |
438 | |
439 | /* PAR swapped by interrupt.S */ | |
240e99cb | 440 | { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR }, |
6a077e4a | 441 | |
5b3e5e5b CD |
442 | /* |
443 | * DC{C,I,CI}SW operations: | |
444 | */ | |
445 | { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw}, | |
446 | { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw}, | |
447 | { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw}, | |
e8c2d99f JA |
448 | /* |
449 | * L2CTLR access (guest wants to know #CPUs). | |
450 | */ | |
451 | { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32, | |
452 | access_l2ctlr, reset_l2ctlr, c9_L2CTLR }, | |
453 | { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr}, | |
454 | ||
5b3e5e5b CD |
455 | /* |
456 | * Dummy performance monitor implementation. | |
457 | */ | |
458 | { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr}, | |
459 | { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset}, | |
460 | { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr}, | |
461 | { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr}, | |
462 | { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr}, | |
463 | { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0}, | |
464 | { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1}, | |
465 | { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr}, | |
466 | { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper}, | |
467 | { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr}, | |
468 | { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr}, | |
469 | { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset}, | |
470 | { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr}, | |
471 | ||
472 | /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */ | |
473 | { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32, | |
8034699a | 474 | access_vm_reg, reset_unknown, c10_PRRR}, |
5b3e5e5b | 475 | { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32, |
8034699a | 476 | access_vm_reg, reset_unknown, c10_NMRR}, |
5b3e5e5b | 477 | |
af20814e MZ |
478 | /* AMAIR0/AMAIR1: swapped by interrupt.S. */ |
479 | { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32, | |
480 | access_vm_reg, reset_unknown, c10_AMAIR0}, | |
481 | { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32, | |
482 | access_vm_reg, reset_unknown, c10_AMAIR1}, | |
483 | ||
acda5430 VM |
484 | /* ICC_SGI1R */ |
485 | { CRm64(12), Op1( 0), is64, access_gic_sgi}, | |
486 | ||
5b3e5e5b CD |
487 | /* VBAR: swapped by interrupt.S. */ |
488 | { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32, | |
489 | NULL, reset_val, c12_VBAR, 0x00000000 }, | |
490 | ||
ec876f4b MZ |
491 | /* ICC_ASGI1R */ |
492 | { CRm64(12), Op1( 1), is64, access_gic_sgi}, | |
493 | /* ICC_SGI0R */ | |
494 | { CRm64(12), Op1( 2), is64, access_gic_sgi}, | |
acda5430 VM |
495 | /* ICC_SRE */ |
496 | { CRn(12), CRm(12), Op1( 0), Op2(5), is32, access_gic_sre }, | |
497 | ||
5b3e5e5b CD |
498 | /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */ |
499 | { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32, | |
8034699a | 500 | access_vm_reg, reset_val, c13_CID, 0x00000000 }, |
5b3e5e5b CD |
501 | { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32, |
502 | NULL, reset_unknown, c13_TID_URW }, | |
503 | { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32, | |
504 | NULL, reset_unknown, c13_TID_URO }, | |
505 | { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32, | |
506 | NULL, reset_unknown, c13_TID_PRIV }, | |
c7e3ba64 | 507 | |
b9fb1739 JF |
508 | /* CNTP */ |
509 | { CRm64(14), Op1( 2), is64, access_cntp_cval}, | |
510 | ||
c7e3ba64 MZ |
511 | /* CNTKCTL: swapped by interrupt.S. */ |
512 | { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32, | |
513 | NULL, reset_val, c14_CNTKCTL, 0x00000000 }, | |
e8c2d99f | 514 | |
b9fb1739 JF |
515 | /* CNTP */ |
516 | { CRn(14), CRm( 2), Op1( 0), Op2( 0), is32, access_cntp_tval }, | |
517 | { CRn(14), CRm( 2), Op1( 0), Op2( 1), is32, access_cntp_ctl }, | |
518 | ||
e8c2d99f JA |
519 | /* The Configuration Base Address Register. */ |
520 | { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar}, | |
5b3e5e5b CD |
521 | }; |
522 | ||
b613f59d MZ |
523 | static int check_reg_table(const struct coproc_reg *table, unsigned int n) |
524 | { | |
525 | unsigned int i; | |
526 | ||
527 | for (i = 1; i < n; i++) { | |
528 | if (cmp_reg(&table[i-1], &table[i]) >= 0) { | |
529 | kvm_err("reg table %p out of order (%d)\n", table, i - 1); | |
530 | return 1; | |
531 | } | |
532 | } | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
5b3e5e5b CD |
537 | /* Target specific emulation tables */ |
538 | static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS]; | |
539 | ||
540 | void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table) | |
541 | { | |
b613f59d | 542 | BUG_ON(check_reg_table(table->table, table->num)); |
5b3e5e5b CD |
543 | target_tables[table->target] = table; |
544 | } | |
545 | ||
546 | /* Get specific register table for this target. */ | |
547 | static const struct coproc_reg *get_target_table(unsigned target, size_t *num) | |
548 | { | |
549 | struct kvm_coproc_target_table *table; | |
550 | ||
551 | table = target_tables[target]; | |
552 | *num = table->num; | |
553 | return table->table; | |
554 | } | |
555 | ||
d06a5440 MZ |
556 | #define reg_to_match_value(x) \ |
557 | ({ \ | |
558 | unsigned long val; \ | |
559 | val = (x)->CRn << 11; \ | |
560 | val |= (x)->CRm << 7; \ | |
561 | val |= (x)->Op1 << 4; \ | |
562 | val |= (x)->Op2 << 1; \ | |
563 | val |= !(x)->is_64bit; \ | |
564 | val; \ | |
565 | }) | |
566 | ||
567 | static int match_reg(const void *key, const void *elt) | |
568 | { | |
569 | const unsigned long pval = (unsigned long)key; | |
570 | const struct coproc_reg *r = elt; | |
571 | ||
572 | return pval - reg_to_match_value(r); | |
573 | } | |
574 | ||
5b3e5e5b CD |
575 | static const struct coproc_reg *find_reg(const struct coproc_params *params, |
576 | const struct coproc_reg table[], | |
577 | unsigned int num) | |
578 | { | |
d06a5440 | 579 | unsigned long pval = reg_to_match_value(params); |
5b3e5e5b | 580 | |
d06a5440 | 581 | return bsearch((void *)pval, table, num, sizeof(table[0]), match_reg); |
5b3e5e5b CD |
582 | } |
583 | ||
584 | static int emulate_cp15(struct kvm_vcpu *vcpu, | |
585 | const struct coproc_params *params) | |
586 | { | |
587 | size_t num; | |
588 | const struct coproc_reg *table, *r; | |
589 | ||
590 | trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn, | |
591 | params->CRm, params->Op2, params->is_write); | |
592 | ||
593 | table = get_target_table(vcpu->arch.target, &num); | |
594 | ||
595 | /* Search target-specific then generic table. */ | |
596 | r = find_reg(params, table, num); | |
597 | if (!r) | |
598 | r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs)); | |
599 | ||
600 | if (likely(r)) { | |
601 | /* If we don't have an accessor, we should never get here! */ | |
602 | BUG_ON(!r->access); | |
603 | ||
604 | if (likely(r->access(vcpu, params, r))) { | |
605 | /* Skip instruction, since it was emulated */ | |
23b415d6 | 606 | kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); |
5b3e5e5b | 607 | } |
5b3e5e5b | 608 | } else { |
9d0d4d34 | 609 | /* If access function fails, it should complain. */ |
d1878af3 MR |
610 | kvm_err("Unsupported guest CP15 access at: %08lx [%08lx]\n", |
611 | *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); | |
5b3e5e5b | 612 | print_cp_instr(params); |
9d0d4d34 | 613 | kvm_inject_undefined(vcpu); |
5b3e5e5b | 614 | } |
9d0d4d34 | 615 | |
5b3e5e5b CD |
616 | return 1; |
617 | } | |
618 | ||
661e6b02 | 619 | static struct coproc_params decode_64bit_hsr(struct kvm_vcpu *vcpu) |
5b3e5e5b CD |
620 | { |
621 | struct coproc_params params; | |
622 | ||
46c214dd | 623 | params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf; |
7393b599 MZ |
624 | params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf; |
625 | params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0); | |
5b3e5e5b CD |
626 | params.is_64bit = true; |
627 | ||
7393b599 | 628 | params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf; |
5b3e5e5b | 629 | params.Op2 = 0; |
7393b599 | 630 | params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf; |
46c214dd | 631 | params.CRm = 0; |
5b3e5e5b | 632 | |
661e6b02 ZH |
633 | return params; |
634 | } | |
635 | ||
636 | /** | |
637 | * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access | |
638 | * @vcpu: The VCPU pointer | |
639 | * @run: The kvm_run struct | |
640 | */ | |
641 | int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run) | |
642 | { | |
643 | struct coproc_params params = decode_64bit_hsr(vcpu); | |
644 | ||
5b3e5e5b CD |
645 | return emulate_cp15(vcpu, ¶ms); |
646 | } | |
647 | ||
661e6b02 ZH |
648 | /** |
649 | * kvm_handle_cp14_64 -- handles a mrrc/mcrr trap on a guest CP14 access | |
650 | * @vcpu: The VCPU pointer | |
651 | * @run: The kvm_run struct | |
652 | */ | |
653 | int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run) | |
654 | { | |
655 | struct coproc_params params = decode_64bit_hsr(vcpu); | |
656 | ||
657 | /* raz_wi cp14 */ | |
9b619a8f | 658 | trap_raz_wi(vcpu, ¶ms, NULL); |
661e6b02 ZH |
659 | |
660 | /* handled */ | |
661 | kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); | |
662 | return 1; | |
663 | } | |
664 | ||
5b3e5e5b CD |
665 | static void reset_coproc_regs(struct kvm_vcpu *vcpu, |
666 | const struct coproc_reg *table, size_t num) | |
667 | { | |
668 | unsigned long i; | |
669 | ||
670 | for (i = 0; i < num; i++) | |
671 | if (table[i].reset) | |
672 | table[i].reset(vcpu, &table[i]); | |
673 | } | |
674 | ||
661e6b02 | 675 | static struct coproc_params decode_32bit_hsr(struct kvm_vcpu *vcpu) |
5b3e5e5b CD |
676 | { |
677 | struct coproc_params params; | |
678 | ||
7393b599 MZ |
679 | params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf; |
680 | params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf; | |
681 | params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0); | |
5b3e5e5b CD |
682 | params.is_64bit = false; |
683 | ||
7393b599 MZ |
684 | params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf; |
685 | params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7; | |
686 | params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7; | |
5b3e5e5b CD |
687 | params.Rt2 = 0; |
688 | ||
661e6b02 ZH |
689 | return params; |
690 | } | |
691 | ||
692 | /** | |
693 | * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access | |
694 | * @vcpu: The VCPU pointer | |
695 | * @run: The kvm_run struct | |
696 | */ | |
697 | int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run) | |
698 | { | |
699 | struct coproc_params params = decode_32bit_hsr(vcpu); | |
5b3e5e5b CD |
700 | return emulate_cp15(vcpu, ¶ms); |
701 | } | |
702 | ||
661e6b02 ZH |
703 | /** |
704 | * kvm_handle_cp14_32 -- handles a mrc/mcr trap on a guest CP14 access | |
705 | * @vcpu: The VCPU pointer | |
706 | * @run: The kvm_run struct | |
707 | */ | |
708 | int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run) | |
709 | { | |
710 | struct coproc_params params = decode_32bit_hsr(vcpu); | |
711 | ||
712 | /* raz_wi cp14 */ | |
9b619a8f | 713 | trap_raz_wi(vcpu, ¶ms, NULL); |
661e6b02 ZH |
714 | |
715 | /* handled */ | |
716 | kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); | |
717 | return 1; | |
718 | } | |
719 | ||
1138245c CD |
720 | /****************************************************************************** |
721 | * Userspace API | |
722 | *****************************************************************************/ | |
723 | ||
724 | static bool index_to_params(u64 id, struct coproc_params *params) | |
725 | { | |
726 | switch (id & KVM_REG_SIZE_MASK) { | |
727 | case KVM_REG_SIZE_U32: | |
728 | /* Any unused index bits means it's not valid. */ | |
729 | if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | |
730 | | KVM_REG_ARM_COPROC_MASK | |
731 | | KVM_REG_ARM_32_CRN_MASK | |
732 | | KVM_REG_ARM_CRM_MASK | |
733 | | KVM_REG_ARM_OPC1_MASK | |
734 | | KVM_REG_ARM_32_OPC2_MASK)) | |
735 | return false; | |
736 | ||
737 | params->is_64bit = false; | |
738 | params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK) | |
739 | >> KVM_REG_ARM_32_CRN_SHIFT); | |
740 | params->CRm = ((id & KVM_REG_ARM_CRM_MASK) | |
741 | >> KVM_REG_ARM_CRM_SHIFT); | |
742 | params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK) | |
743 | >> KVM_REG_ARM_OPC1_SHIFT); | |
744 | params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK) | |
745 | >> KVM_REG_ARM_32_OPC2_SHIFT); | |
746 | return true; | |
747 | case KVM_REG_SIZE_U64: | |
748 | /* Any unused index bits means it's not valid. */ | |
749 | if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | |
750 | | KVM_REG_ARM_COPROC_MASK | |
751 | | KVM_REG_ARM_CRM_MASK | |
752 | | KVM_REG_ARM_OPC1_MASK)) | |
753 | return false; | |
754 | params->is_64bit = true; | |
240e99cb CD |
755 | /* CRm to CRn: see cp15_to_index for details */ |
756 | params->CRn = ((id & KVM_REG_ARM_CRM_MASK) | |
1138245c CD |
757 | >> KVM_REG_ARM_CRM_SHIFT); |
758 | params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK) | |
759 | >> KVM_REG_ARM_OPC1_SHIFT); | |
760 | params->Op2 = 0; | |
240e99cb | 761 | params->CRm = 0; |
1138245c CD |
762 | return true; |
763 | default: | |
764 | return false; | |
765 | } | |
766 | } | |
767 | ||
768 | /* Decode an index value, and find the cp15 coproc_reg entry. */ | |
769 | static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu, | |
770 | u64 id) | |
771 | { | |
772 | size_t num; | |
773 | const struct coproc_reg *table, *r; | |
774 | struct coproc_params params; | |
775 | ||
776 | /* We only do cp15 for now. */ | |
777 | if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15) | |
778 | return NULL; | |
779 | ||
780 | if (!index_to_params(id, ¶ms)) | |
781 | return NULL; | |
782 | ||
783 | table = get_target_table(vcpu->arch.target, &num); | |
784 | r = find_reg(¶ms, table, num); | |
785 | if (!r) | |
786 | r = find_reg(¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); | |
787 | ||
788 | /* Not saved in the cp15 array? */ | |
789 | if (r && !r->reg) | |
790 | r = NULL; | |
791 | ||
792 | return r; | |
793 | } | |
794 | ||
795 | /* | |
796 | * These are the invariant cp15 registers: we let the guest see the host | |
797 | * versions of these, so they're part of the guest state. | |
798 | * | |
799 | * A future CPU may provide a mechanism to present different values to | |
800 | * the guest, or a future kvm may trap them. | |
801 | */ | |
802 | /* Unfortunately, there's no register-argument for mrc, so generate. */ | |
803 | #define FUNCTION_FOR32(crn, crm, op1, op2, name) \ | |
804 | static void get_##name(struct kvm_vcpu *v, \ | |
805 | const struct coproc_reg *r) \ | |
806 | { \ | |
807 | u32 val; \ | |
808 | \ | |
809 | asm volatile("mrc p15, " __stringify(op1) \ | |
810 | ", %0, c" __stringify(crn) \ | |
811 | ", c" __stringify(crm) \ | |
812 | ", " __stringify(op2) "\n" : "=r" (val)); \ | |
813 | ((struct coproc_reg *)r)->val = val; \ | |
814 | } | |
815 | ||
816 | FUNCTION_FOR32(0, 0, 0, 0, MIDR) | |
817 | FUNCTION_FOR32(0, 0, 0, 1, CTR) | |
818 | FUNCTION_FOR32(0, 0, 0, 2, TCMTR) | |
819 | FUNCTION_FOR32(0, 0, 0, 3, TLBTR) | |
820 | FUNCTION_FOR32(0, 0, 0, 6, REVIDR) | |
821 | FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0) | |
822 | FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1) | |
823 | FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0) | |
824 | FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0) | |
825 | FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0) | |
826 | FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1) | |
827 | FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2) | |
828 | FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3) | |
829 | FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0) | |
830 | FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1) | |
831 | FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2) | |
832 | FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3) | |
833 | FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4) | |
834 | FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5) | |
835 | FUNCTION_FOR32(0, 0, 1, 1, CLIDR) | |
836 | FUNCTION_FOR32(0, 0, 1, 7, AIDR) | |
837 | ||
838 | /* ->val is filled in by kvm_invariant_coproc_table_init() */ | |
839 | static struct coproc_reg invariant_cp15[] = { | |
840 | { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR }, | |
841 | { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR }, | |
842 | { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR }, | |
843 | { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR }, | |
844 | { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR }, | |
845 | ||
504bfce1 MZ |
846 | { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR }, |
847 | { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR }, | |
848 | ||
1138245c CD |
849 | { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 }, |
850 | { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 }, | |
851 | { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 }, | |
852 | { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 }, | |
853 | { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 }, | |
854 | { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 }, | |
855 | { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 }, | |
856 | { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 }, | |
857 | ||
858 | { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 }, | |
859 | { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 }, | |
860 | { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 }, | |
861 | { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 }, | |
862 | { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 }, | |
863 | { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 }, | |
1138245c CD |
864 | }; |
865 | ||
73891f72 VK |
866 | /* |
867 | * Reads a register value from a userspace address to a kernel | |
868 | * variable. Make sure that register size matches sizeof(*__val). | |
869 | */ | |
1138245c CD |
870 | static int reg_from_user(void *val, const void __user *uaddr, u64 id) |
871 | { | |
1138245c CD |
872 | if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) |
873 | return -EFAULT; | |
874 | return 0; | |
875 | } | |
876 | ||
73891f72 VK |
877 | /* |
878 | * Writes a register value to a userspace address from a kernel variable. | |
879 | * Make sure that register size matches sizeof(*__val). | |
880 | */ | |
1138245c CD |
881 | static int reg_to_user(void __user *uaddr, const void *val, u64 id) |
882 | { | |
1138245c CD |
883 | if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) |
884 | return -EFAULT; | |
885 | return 0; | |
886 | } | |
887 | ||
888 | static int get_invariant_cp15(u64 id, void __user *uaddr) | |
889 | { | |
890 | struct coproc_params params; | |
891 | const struct coproc_reg *r; | |
73891f72 | 892 | int ret; |
1138245c CD |
893 | |
894 | if (!index_to_params(id, ¶ms)) | |
895 | return -ENOENT; | |
896 | ||
897 | r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15)); | |
898 | if (!r) | |
899 | return -ENOENT; | |
900 | ||
73891f72 VK |
901 | ret = -ENOENT; |
902 | if (KVM_REG_SIZE(id) == 4) { | |
903 | u32 val = r->val; | |
904 | ||
905 | ret = reg_to_user(uaddr, &val, id); | |
906 | } else if (KVM_REG_SIZE(id) == 8) { | |
907 | ret = reg_to_user(uaddr, &r->val, id); | |
908 | } | |
909 | return ret; | |
1138245c CD |
910 | } |
911 | ||
912 | static int set_invariant_cp15(u64 id, void __user *uaddr) | |
913 | { | |
914 | struct coproc_params params; | |
915 | const struct coproc_reg *r; | |
916 | int err; | |
73891f72 | 917 | u64 val; |
1138245c CD |
918 | |
919 | if (!index_to_params(id, ¶ms)) | |
920 | return -ENOENT; | |
921 | r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15)); | |
922 | if (!r) | |
923 | return -ENOENT; | |
924 | ||
73891f72 VK |
925 | err = -ENOENT; |
926 | if (KVM_REG_SIZE(id) == 4) { | |
927 | u32 val32; | |
928 | ||
929 | err = reg_from_user(&val32, uaddr, id); | |
930 | if (!err) | |
931 | val = val32; | |
932 | } else if (KVM_REG_SIZE(id) == 8) { | |
933 | err = reg_from_user(&val, uaddr, id); | |
934 | } | |
1138245c CD |
935 | if (err) |
936 | return err; | |
937 | ||
938 | /* This is what we mean by invariant: you can't change it. */ | |
939 | if (r->val != val) | |
940 | return -EINVAL; | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
c27581ed CD |
945 | static bool is_valid_cache(u32 val) |
946 | { | |
947 | u32 level, ctype; | |
948 | ||
949 | if (val >= CSSELR_MAX) | |
18d45766 | 950 | return false; |
c27581ed CD |
951 | |
952 | /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ | |
953 | level = (val >> 1); | |
954 | ctype = (cache_levels >> (level * 3)) & 7; | |
955 | ||
956 | switch (ctype) { | |
957 | case 0: /* No cache */ | |
958 | return false; | |
959 | case 1: /* Instruction cache only */ | |
960 | return (val & 1); | |
961 | case 2: /* Data cache only */ | |
962 | case 4: /* Unified cache */ | |
963 | return !(val & 1); | |
964 | case 3: /* Separate instruction and data caches */ | |
965 | return true; | |
966 | default: /* Reserved: we can't know instruction or data. */ | |
967 | return false; | |
968 | } | |
969 | } | |
970 | ||
971 | /* Which cache CCSIDR represents depends on CSSELR value. */ | |
972 | static u32 get_ccsidr(u32 csselr) | |
973 | { | |
974 | u32 ccsidr; | |
975 | ||
976 | /* Make sure noone else changes CSSELR during this! */ | |
977 | local_irq_disable(); | |
978 | /* Put value into CSSELR */ | |
979 | asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); | |
980 | isb(); | |
981 | /* Read result out of CCSIDR */ | |
982 | asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr)); | |
983 | local_irq_enable(); | |
984 | ||
985 | return ccsidr; | |
986 | } | |
987 | ||
988 | static int demux_c15_get(u64 id, void __user *uaddr) | |
989 | { | |
990 | u32 val; | |
991 | u32 __user *uval = uaddr; | |
992 | ||
993 | /* Fail if we have unknown bits set. */ | |
994 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
995 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
996 | return -ENOENT; | |
997 | ||
998 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { | |
999 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: | |
1000 | if (KVM_REG_SIZE(id) != 4) | |
1001 | return -ENOENT; | |
1002 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) | |
1003 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; | |
1004 | if (!is_valid_cache(val)) | |
1005 | return -ENOENT; | |
1006 | ||
1007 | return put_user(get_ccsidr(val), uval); | |
1008 | default: | |
1009 | return -ENOENT; | |
1010 | } | |
1011 | } | |
1012 | ||
1013 | static int demux_c15_set(u64 id, void __user *uaddr) | |
1014 | { | |
1015 | u32 val, newval; | |
1016 | u32 __user *uval = uaddr; | |
1017 | ||
1018 | /* Fail if we have unknown bits set. */ | |
1019 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
1020 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
1021 | return -ENOENT; | |
1022 | ||
1023 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { | |
1024 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: | |
1025 | if (KVM_REG_SIZE(id) != 4) | |
1026 | return -ENOENT; | |
1027 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) | |
1028 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; | |
1029 | if (!is_valid_cache(val)) | |
1030 | return -ENOENT; | |
1031 | ||
1032 | if (get_user(newval, uval)) | |
1033 | return -EFAULT; | |
1034 | ||
1035 | /* This is also invariant: you can't change it. */ | |
1036 | if (newval != get_ccsidr(val)) | |
1037 | return -EINVAL; | |
1038 | return 0; | |
1039 | default: | |
1040 | return -ENOENT; | |
1041 | } | |
1042 | } | |
1043 | ||
4fe21e4c RR |
1044 | #ifdef CONFIG_VFPv3 |
1045 | static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC, | |
1046 | KVM_REG_ARM_VFP_FPSCR, | |
1047 | KVM_REG_ARM_VFP_FPINST, | |
1048 | KVM_REG_ARM_VFP_FPINST2, | |
1049 | KVM_REG_ARM_VFP_MVFR0, | |
1050 | KVM_REG_ARM_VFP_MVFR1, | |
1051 | KVM_REG_ARM_VFP_FPSID }; | |
1052 | ||
1053 | static unsigned int num_fp_regs(void) | |
1054 | { | |
1055 | if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2) | |
1056 | return 32; | |
1057 | else | |
1058 | return 16; | |
1059 | } | |
1060 | ||
1061 | static unsigned int num_vfp_regs(void) | |
1062 | { | |
1063 | /* Normal FP regs + control regs. */ | |
1064 | return num_fp_regs() + ARRAY_SIZE(vfp_sysregs); | |
1065 | } | |
1066 | ||
1067 | static int copy_vfp_regids(u64 __user *uindices) | |
1068 | { | |
1069 | unsigned int i; | |
1070 | const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP; | |
1071 | const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; | |
1072 | ||
1073 | for (i = 0; i < num_fp_regs(); i++) { | |
1074 | if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i, | |
1075 | uindices)) | |
1076 | return -EFAULT; | |
1077 | uindices++; | |
1078 | } | |
1079 | ||
1080 | for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) { | |
1081 | if (put_user(u32reg | vfp_sysregs[i], uindices)) | |
1082 | return -EFAULT; | |
1083 | uindices++; | |
1084 | } | |
1085 | ||
1086 | return num_vfp_regs(); | |
1087 | } | |
1088 | ||
1089 | static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) | |
1090 | { | |
1091 | u32 vfpid = (id & KVM_REG_ARM_VFP_MASK); | |
1092 | u32 val; | |
1093 | ||
1094 | /* Fail if we have unknown bits set. */ | |
1095 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
1096 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
1097 | return -ENOENT; | |
1098 | ||
1099 | if (vfpid < num_fp_regs()) { | |
1100 | if (KVM_REG_SIZE(id) != 8) | |
1101 | return -ENOENT; | |
0ca5565d | 1102 | return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpregs[vfpid], |
4fe21e4c RR |
1103 | id); |
1104 | } | |
1105 | ||
1106 | /* FP control registers are all 32 bit. */ | |
1107 | if (KVM_REG_SIZE(id) != 4) | |
1108 | return -ENOENT; | |
1109 | ||
1110 | switch (vfpid) { | |
1111 | case KVM_REG_ARM_VFP_FPEXC: | |
0ca5565d | 1112 | return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpexc, id); |
4fe21e4c | 1113 | case KVM_REG_ARM_VFP_FPSCR: |
0ca5565d | 1114 | return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpscr, id); |
4fe21e4c | 1115 | case KVM_REG_ARM_VFP_FPINST: |
0ca5565d | 1116 | return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpinst, id); |
4fe21e4c | 1117 | case KVM_REG_ARM_VFP_FPINST2: |
0ca5565d | 1118 | return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpinst2, id); |
4fe21e4c RR |
1119 | case KVM_REG_ARM_VFP_MVFR0: |
1120 | val = fmrx(MVFR0); | |
1121 | return reg_to_user(uaddr, &val, id); | |
1122 | case KVM_REG_ARM_VFP_MVFR1: | |
1123 | val = fmrx(MVFR1); | |
1124 | return reg_to_user(uaddr, &val, id); | |
1125 | case KVM_REG_ARM_VFP_FPSID: | |
1126 | val = fmrx(FPSID); | |
1127 | return reg_to_user(uaddr, &val, id); | |
1128 | default: | |
1129 | return -ENOENT; | |
1130 | } | |
1131 | } | |
1132 | ||
1133 | static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr) | |
1134 | { | |
1135 | u32 vfpid = (id & KVM_REG_ARM_VFP_MASK); | |
1136 | u32 val; | |
1137 | ||
1138 | /* Fail if we have unknown bits set. */ | |
1139 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
1140 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
1141 | return -ENOENT; | |
1142 | ||
1143 | if (vfpid < num_fp_regs()) { | |
1144 | if (KVM_REG_SIZE(id) != 8) | |
1145 | return -ENOENT; | |
0ca5565d | 1146 | return reg_from_user(&vcpu->arch.ctxt.vfp.fpregs[vfpid], |
4fe21e4c RR |
1147 | uaddr, id); |
1148 | } | |
1149 | ||
1150 | /* FP control registers are all 32 bit. */ | |
1151 | if (KVM_REG_SIZE(id) != 4) | |
1152 | return -ENOENT; | |
1153 | ||
1154 | switch (vfpid) { | |
1155 | case KVM_REG_ARM_VFP_FPEXC: | |
0ca5565d | 1156 | return reg_from_user(&vcpu->arch.ctxt.vfp.fpexc, uaddr, id); |
4fe21e4c | 1157 | case KVM_REG_ARM_VFP_FPSCR: |
0ca5565d | 1158 | return reg_from_user(&vcpu->arch.ctxt.vfp.fpscr, uaddr, id); |
4fe21e4c | 1159 | case KVM_REG_ARM_VFP_FPINST: |
0ca5565d | 1160 | return reg_from_user(&vcpu->arch.ctxt.vfp.fpinst, uaddr, id); |
4fe21e4c | 1161 | case KVM_REG_ARM_VFP_FPINST2: |
0ca5565d | 1162 | return reg_from_user(&vcpu->arch.ctxt.vfp.fpinst2, uaddr, id); |
4fe21e4c RR |
1163 | /* These are invariant. */ |
1164 | case KVM_REG_ARM_VFP_MVFR0: | |
1165 | if (reg_from_user(&val, uaddr, id)) | |
1166 | return -EFAULT; | |
1167 | if (val != fmrx(MVFR0)) | |
1168 | return -EINVAL; | |
1169 | return 0; | |
1170 | case KVM_REG_ARM_VFP_MVFR1: | |
1171 | if (reg_from_user(&val, uaddr, id)) | |
1172 | return -EFAULT; | |
1173 | if (val != fmrx(MVFR1)) | |
1174 | return -EINVAL; | |
1175 | return 0; | |
1176 | case KVM_REG_ARM_VFP_FPSID: | |
1177 | if (reg_from_user(&val, uaddr, id)) | |
1178 | return -EFAULT; | |
1179 | if (val != fmrx(FPSID)) | |
1180 | return -EINVAL; | |
1181 | return 0; | |
1182 | default: | |
1183 | return -ENOENT; | |
1184 | } | |
1185 | } | |
1186 | #else /* !CONFIG_VFPv3 */ | |
1187 | static unsigned int num_vfp_regs(void) | |
1188 | { | |
1189 | return 0; | |
1190 | } | |
1191 | ||
1192 | static int copy_vfp_regids(u64 __user *uindices) | |
1193 | { | |
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) | |
1198 | { | |
1199 | return -ENOENT; | |
1200 | } | |
1201 | ||
1202 | static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr) | |
1203 | { | |
1204 | return -ENOENT; | |
1205 | } | |
1206 | #endif /* !CONFIG_VFPv3 */ | |
1207 | ||
1138245c CD |
1208 | int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) |
1209 | { | |
1210 | const struct coproc_reg *r; | |
1211 | void __user *uaddr = (void __user *)(long)reg->addr; | |
73891f72 | 1212 | int ret; |
1138245c | 1213 | |
c27581ed CD |
1214 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) |
1215 | return demux_c15_get(reg->id, uaddr); | |
1216 | ||
4fe21e4c RR |
1217 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP) |
1218 | return vfp_get_reg(vcpu, reg->id, uaddr); | |
1219 | ||
1138245c CD |
1220 | r = index_to_coproc_reg(vcpu, reg->id); |
1221 | if (!r) | |
1222 | return get_invariant_cp15(reg->id, uaddr); | |
1223 | ||
73891f72 VK |
1224 | ret = -ENOENT; |
1225 | if (KVM_REG_SIZE(reg->id) == 8) { | |
1226 | u64 val; | |
1227 | ||
1228 | val = vcpu_cp15_reg64_get(vcpu, r); | |
1229 | ret = reg_to_user(uaddr, &val, reg->id); | |
1230 | } else if (KVM_REG_SIZE(reg->id) == 4) { | |
fb32a52a | 1231 | ret = reg_to_user(uaddr, &vcpu_cp15(vcpu, r->reg), reg->id); |
73891f72 VK |
1232 | } |
1233 | ||
1234 | return ret; | |
1138245c CD |
1235 | } |
1236 | ||
1237 | int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) | |
1238 | { | |
1239 | const struct coproc_reg *r; | |
1240 | void __user *uaddr = (void __user *)(long)reg->addr; | |
73891f72 | 1241 | int ret; |
1138245c | 1242 | |
c27581ed CD |
1243 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) |
1244 | return demux_c15_set(reg->id, uaddr); | |
1245 | ||
4fe21e4c RR |
1246 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP) |
1247 | return vfp_set_reg(vcpu, reg->id, uaddr); | |
1248 | ||
1138245c CD |
1249 | r = index_to_coproc_reg(vcpu, reg->id); |
1250 | if (!r) | |
1251 | return set_invariant_cp15(reg->id, uaddr); | |
1252 | ||
73891f72 VK |
1253 | ret = -ENOENT; |
1254 | if (KVM_REG_SIZE(reg->id) == 8) { | |
1255 | u64 val; | |
1256 | ||
1257 | ret = reg_from_user(&val, uaddr, reg->id); | |
1258 | if (!ret) | |
1259 | vcpu_cp15_reg64_set(vcpu, r, val); | |
1260 | } else if (KVM_REG_SIZE(reg->id) == 4) { | |
fb32a52a | 1261 | ret = reg_from_user(&vcpu_cp15(vcpu, r->reg), uaddr, reg->id); |
73891f72 VK |
1262 | } |
1263 | ||
1264 | return ret; | |
1138245c CD |
1265 | } |
1266 | ||
c27581ed CD |
1267 | static unsigned int num_demux_regs(void) |
1268 | { | |
1269 | unsigned int i, count = 0; | |
1270 | ||
1271 | for (i = 0; i < CSSELR_MAX; i++) | |
1272 | if (is_valid_cache(i)) | |
1273 | count++; | |
1274 | ||
1275 | return count; | |
1276 | } | |
1277 | ||
1278 | static int write_demux_regids(u64 __user *uindices) | |
1279 | { | |
1280 | u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; | |
1281 | unsigned int i; | |
1282 | ||
1283 | val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; | |
1284 | for (i = 0; i < CSSELR_MAX; i++) { | |
1285 | if (!is_valid_cache(i)) | |
1286 | continue; | |
1287 | if (put_user(val | i, uindices)) | |
1288 | return -EFAULT; | |
1289 | uindices++; | |
1290 | } | |
1291 | return 0; | |
1292 | } | |
1293 | ||
1138245c CD |
1294 | static u64 cp15_to_index(const struct coproc_reg *reg) |
1295 | { | |
1296 | u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT); | |
f1d67d4a | 1297 | if (reg->is_64bit) { |
1138245c CD |
1298 | val |= KVM_REG_SIZE_U64; |
1299 | val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); | |
240e99cb CD |
1300 | /* |
1301 | * CRn always denotes the primary coproc. reg. nr. for the | |
1302 | * in-kernel representation, but the user space API uses the | |
1303 | * CRm for the encoding, because it is modelled after the | |
1304 | * MRRC/MCRR instructions: see the ARM ARM rev. c page | |
1305 | * B3-1445 | |
1306 | */ | |
1307 | val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT); | |
1138245c CD |
1308 | } else { |
1309 | val |= KVM_REG_SIZE_U32; | |
1310 | val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); | |
1311 | val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT); | |
1312 | val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT); | |
1313 | val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT); | |
1314 | } | |
1315 | return val; | |
1316 | } | |
1317 | ||
1318 | static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind) | |
1319 | { | |
1320 | if (!*uind) | |
1321 | return true; | |
1322 | ||
1323 | if (put_user(cp15_to_index(reg), *uind)) | |
1324 | return false; | |
1325 | ||
1326 | (*uind)++; | |
1327 | return true; | |
1328 | } | |
1329 | ||
1330 | /* Assumed ordered tables, see kvm_coproc_table_init. */ | |
1331 | static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind) | |
1332 | { | |
1333 | const struct coproc_reg *i1, *i2, *end1, *end2; | |
1334 | unsigned int total = 0; | |
1335 | size_t num; | |
1336 | ||
1337 | /* We check for duplicates here, to allow arch-specific overrides. */ | |
1338 | i1 = get_target_table(vcpu->arch.target, &num); | |
1339 | end1 = i1 + num; | |
1340 | i2 = cp15_regs; | |
1341 | end2 = cp15_regs + ARRAY_SIZE(cp15_regs); | |
1342 | ||
1343 | BUG_ON(i1 == end1 || i2 == end2); | |
1344 | ||
1345 | /* Walk carefully, as both tables may refer to the same register. */ | |
1346 | while (i1 || i2) { | |
1347 | int cmp = cmp_reg(i1, i2); | |
1348 | /* target-specific overrides generic entry. */ | |
1349 | if (cmp <= 0) { | |
1350 | /* Ignore registers we trap but don't save. */ | |
1351 | if (i1->reg) { | |
1352 | if (!copy_reg_to_user(i1, &uind)) | |
1353 | return -EFAULT; | |
1354 | total++; | |
1355 | } | |
1356 | } else { | |
1357 | /* Ignore registers we trap but don't save. */ | |
1358 | if (i2->reg) { | |
1359 | if (!copy_reg_to_user(i2, &uind)) | |
1360 | return -EFAULT; | |
1361 | total++; | |
1362 | } | |
1363 | } | |
1364 | ||
1365 | if (cmp <= 0 && ++i1 == end1) | |
1366 | i1 = NULL; | |
1367 | if (cmp >= 0 && ++i2 == end2) | |
1368 | i2 = NULL; | |
1369 | } | |
1370 | return total; | |
1371 | } | |
1372 | ||
1373 | unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu) | |
1374 | { | |
1375 | return ARRAY_SIZE(invariant_cp15) | |
c27581ed | 1376 | + num_demux_regs() |
4fe21e4c | 1377 | + num_vfp_regs() |
1138245c CD |
1378 | + walk_cp15(vcpu, (u64 __user *)NULL); |
1379 | } | |
1380 | ||
1381 | int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) | |
1382 | { | |
1383 | unsigned int i; | |
1384 | int err; | |
1385 | ||
1386 | /* Then give them all the invariant registers' indices. */ | |
1387 | for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) { | |
1388 | if (put_user(cp15_to_index(&invariant_cp15[i]), uindices)) | |
1389 | return -EFAULT; | |
1390 | uindices++; | |
1391 | } | |
1392 | ||
1393 | err = walk_cp15(vcpu, uindices); | |
c27581ed CD |
1394 | if (err < 0) |
1395 | return err; | |
1396 | uindices += err; | |
1397 | ||
4fe21e4c RR |
1398 | err = copy_vfp_regids(uindices); |
1399 | if (err < 0) | |
1400 | return err; | |
1401 | uindices += err; | |
1402 | ||
c27581ed | 1403 | return write_demux_regids(uindices); |
1138245c CD |
1404 | } |
1405 | ||
5b3e5e5b CD |
1406 | void kvm_coproc_table_init(void) |
1407 | { | |
1408 | unsigned int i; | |
1409 | ||
1410 | /* Make sure tables are unique and in order. */ | |
b613f59d MZ |
1411 | BUG_ON(check_reg_table(cp15_regs, ARRAY_SIZE(cp15_regs))); |
1412 | BUG_ON(check_reg_table(invariant_cp15, ARRAY_SIZE(invariant_cp15))); | |
1138245c CD |
1413 | |
1414 | /* We abuse the reset function to overwrite the table itself. */ | |
1415 | for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) | |
1416 | invariant_cp15[i].reset(NULL, &invariant_cp15[i]); | |
c27581ed CD |
1417 | |
1418 | /* | |
1419 | * CLIDR format is awkward, so clean it up. See ARM B4.1.20: | |
1420 | * | |
1421 | * If software reads the Cache Type fields from Ctype1 | |
1422 | * upwards, once it has seen a value of 0b000, no caches | |
1423 | * exist at further-out levels of the hierarchy. So, for | |
1424 | * example, if Ctype3 is the first Cache Type field with a | |
1425 | * value of 0b000, the values of Ctype4 to Ctype7 must be | |
1426 | * ignored. | |
1427 | */ | |
1428 | asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels)); | |
1429 | for (i = 0; i < 7; i++) | |
1430 | if (((cache_levels >> (i*3)) & 7) == 0) | |
1431 | break; | |
1432 | /* Clear all higher bits. */ | |
1433 | cache_levels &= (1 << (i*3))-1; | |
5b3e5e5b CD |
1434 | } |
1435 | ||
1436 | /** | |
1437 | * kvm_reset_coprocs - sets cp15 registers to reset value | |
1438 | * @vcpu: The VCPU pointer | |
1439 | * | |
1440 | * This function finds the right table above and sets the registers on the | |
1441 | * virtual CPU struct to their architecturally defined reset values. | |
1442 | */ | |
749cf76c CD |
1443 | void kvm_reset_coprocs(struct kvm_vcpu *vcpu) |
1444 | { | |
5b3e5e5b CD |
1445 | size_t num; |
1446 | const struct coproc_reg *table; | |
1447 | ||
1448 | /* Catch someone adding a register without putting in reset entry. */ | |
fb32a52a | 1449 | memset(vcpu->arch.ctxt.cp15, 0x42, sizeof(vcpu->arch.ctxt.cp15)); |
5b3e5e5b CD |
1450 | |
1451 | /* Generic chip reset first (so target could override). */ | |
1452 | reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); | |
1453 | ||
1454 | table = get_target_table(vcpu->arch.target, &num); | |
1455 | reset_coproc_regs(vcpu, table, num); | |
1456 | ||
1457 | for (num = 1; num < NR_CP15_REGS; num++) | |
20589c8c MZ |
1458 | WARN(vcpu_cp15(vcpu, num) == 0x42424242, |
1459 | "Didn't reset vcpu_cp15(vcpu, %zi)", num); | |
749cf76c | 1460 | } |