Commit | Line | Data |
---|---|---|
afe4b25e LB |
1 | /* |
2 | * linux/arch/arm/kernel/xscale-cp0.c | |
3 | * | |
4 | * XScale DSP and iWMMXt coprocessor context switching and handling | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/signal.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/init.h> | |
17 | #include <asm/thread_notify.h> | |
18 | #include <asm/io.h> | |
19 | ||
20 | static inline void dsp_save_state(u32 *state) | |
21 | { | |
22 | __asm__ __volatile__ ( | |
23 | "mrrc p0, 0, %0, %1, c0\n" | |
24 | : "=r" (state[0]), "=r" (state[1])); | |
25 | } | |
26 | ||
27 | static inline void dsp_load_state(u32 *state) | |
28 | { | |
29 | __asm__ __volatile__ ( | |
30 | "mcrr p0, 0, %0, %1, c0\n" | |
31 | : : "r" (state[0]), "r" (state[1])); | |
32 | } | |
33 | ||
34 | static int dsp_do(struct notifier_block *self, unsigned long cmd, void *t) | |
35 | { | |
36 | struct thread_info *thread = t; | |
37 | ||
38 | switch (cmd) { | |
39 | case THREAD_NOTIFY_FLUSH: | |
40 | thread->cpu_context.extra[0] = 0; | |
41 | thread->cpu_context.extra[1] = 0; | |
42 | break; | |
43 | ||
44 | case THREAD_NOTIFY_SWITCH: | |
45 | dsp_save_state(current_thread_info()->cpu_context.extra); | |
46 | dsp_load_state(thread->cpu_context.extra); | |
47 | break; | |
48 | } | |
49 | ||
50 | return NOTIFY_DONE; | |
51 | } | |
52 | ||
53 | static struct notifier_block dsp_notifier_block = { | |
54 | .notifier_call = dsp_do, | |
55 | }; | |
56 | ||
57 | ||
58 | #ifdef CONFIG_IWMMXT | |
59 | static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t) | |
60 | { | |
61 | struct thread_info *thread = t; | |
62 | ||
63 | switch (cmd) { | |
64 | case THREAD_NOTIFY_FLUSH: | |
65 | /* | |
66 | * flush_thread() zeroes thread->fpstate, so no need | |
67 | * to do anything here. | |
68 | * | |
69 | * FALLTHROUGH: Ensure we don't try to overwrite our newly | |
70 | * initialised state information on the first fault. | |
71 | */ | |
72 | ||
73 | case THREAD_NOTIFY_RELEASE: | |
74 | iwmmxt_task_release(thread); | |
75 | break; | |
76 | ||
77 | case THREAD_NOTIFY_SWITCH: | |
78 | iwmmxt_task_switch(thread); | |
79 | break; | |
80 | } | |
81 | ||
82 | return NOTIFY_DONE; | |
83 | } | |
84 | ||
85 | static struct notifier_block iwmmxt_notifier_block = { | |
86 | .notifier_call = iwmmxt_do, | |
87 | }; | |
88 | #endif | |
89 | ||
90 | ||
91 | static u32 __init xscale_cp_access_read(void) | |
92 | { | |
93 | u32 value; | |
94 | ||
95 | __asm__ __volatile__ ( | |
96 | "mrc p15, 0, %0, c15, c1, 0\n\t" | |
97 | : "=r" (value)); | |
98 | ||
99 | return value; | |
100 | } | |
101 | ||
102 | static void __init xscale_cp_access_write(u32 value) | |
103 | { | |
104 | u32 temp; | |
105 | ||
106 | __asm__ __volatile__ ( | |
107 | "mcr p15, 0, %1, c15, c1, 0\n\t" | |
108 | "mrc p15, 0, %0, c15, c1, 0\n\t" | |
109 | "mov %0, %0\n\t" | |
110 | "sub pc, pc, #4\n\t" | |
111 | : "=r" (temp) : "r" (value)); | |
112 | } | |
113 | ||
114 | /* | |
115 | * Detect whether we have a MAC coprocessor (40 bit register) or an | |
116 | * iWMMXt coprocessor (64 bit registers) by loading 00000100:00000000 | |
117 | * into a coprocessor register and reading it back, and checking | |
118 | * whether the upper word survived intact. | |
119 | */ | |
120 | static int __init cpu_has_iwmmxt(void) | |
121 | { | |
122 | u32 lo; | |
123 | u32 hi; | |
124 | ||
125 | /* | |
126 | * This sequence is interpreted by the DSP coprocessor as: | |
127 | * mar acc0, %2, %3 | |
128 | * mra %0, %1, acc0 | |
129 | * | |
130 | * And by the iWMMXt coprocessor as: | |
131 | * tmcrr wR0, %2, %3 | |
132 | * tmrrc %0, %1, wR0 | |
133 | */ | |
134 | __asm__ __volatile__ ( | |
135 | "mcrr p0, 0, %2, %3, c0\n" | |
136 | "mrrc p0, 0, %0, %1, c0\n" | |
137 | : "=r" (lo), "=r" (hi) | |
138 | : "r" (0), "r" (0x100)); | |
139 | ||
140 | return !!hi; | |
141 | } | |
142 | ||
143 | ||
144 | /* | |
145 | * If we detect that the CPU has iWMMXt (and CONFIG_IWMMXT=y), we | |
146 | * disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy | |
147 | * switch code handle iWMMXt context switching. If on the other | |
148 | * hand the CPU has a DSP coprocessor, we keep access to CP0 enabled | |
149 | * all the time, and save/restore acc0 on context switch in non-lazy | |
150 | * fashion. | |
151 | */ | |
152 | static int __init xscale_cp0_init(void) | |
153 | { | |
154 | u32 cp_access; | |
155 | ||
156 | cp_access = xscale_cp_access_read() & ~3; | |
157 | xscale_cp_access_write(cp_access | 1); | |
158 | ||
159 | if (cpu_has_iwmmxt()) { | |
160 | #ifndef CONFIG_IWMMXT | |
161 | printk(KERN_WARNING "CAUTION: XScale iWMMXt coprocessor " | |
162 | "detected, but kernel support is missing.\n"); | |
163 | #else | |
164 | printk(KERN_INFO "XScale iWMMXt coprocessor detected.\n"); | |
165 | elf_hwcap |= HWCAP_IWMMXT; | |
166 | thread_register_notifier(&iwmmxt_notifier_block); | |
167 | #endif | |
168 | } else { | |
169 | printk(KERN_INFO "XScale DSP coprocessor detected.\n"); | |
170 | thread_register_notifier(&dsp_notifier_block); | |
171 | cp_access |= 1; | |
172 | } | |
173 | ||
174 | xscale_cp_access_write(cp_access); | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | late_initcall(xscale_cp0_init); |