Merge remote-tracking branch 'spi/fix/clps711x' into spi-clps711x
[linux-2.6-block.git] / arch / arm / kernel / smp.c
CommitLineData
1da177e4
LT
1/*
2 * linux/arch/arm/kernel/smp.c
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
c97d4869 10#include <linux/module.h>
1da177e4
LT
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16#include <linux/cache.h>
17#include <linux/profile.h>
18#include <linux/errno.h>
19#include <linux/mm.h>
4e950f6f 20#include <linux/err.h>
1da177e4 21#include <linux/cpu.h>
1da177e4 22#include <linux/seq_file.h>
c97d4869 23#include <linux/irq.h>
bc28248e
RK
24#include <linux/percpu.h>
25#include <linux/clockchips.h>
3c030bea 26#include <linux/completion.h>
ec971ea5 27#include <linux/cpufreq.h>
1da177e4 28
60063497 29#include <linux/atomic.h>
abcee5fb 30#include <asm/smp.h>
1da177e4
LT
31#include <asm/cacheflush.h>
32#include <asm/cpu.h>
42578c82 33#include <asm/cputype.h>
5a567d78 34#include <asm/exception.h>
8903826d 35#include <asm/idmap.h>
c9018aab 36#include <asm/topology.h>
e65f38ed
RK
37#include <asm/mmu_context.h>
38#include <asm/pgtable.h>
39#include <asm/pgalloc.h>
1da177e4 40#include <asm/processor.h>
37b05b63 41#include <asm/sections.h>
1da177e4
LT
42#include <asm/tlbflush.h>
43#include <asm/ptrace.h>
d6257288 44#include <asm/smp_plat.h>
4588c34d 45#include <asm/virt.h>
abcee5fb 46#include <asm/mach/arch.h>
eb08375e 47#include <asm/mpu.h>
1da177e4 48
e65f38ed
RK
49/*
50 * as from 2.5, kernels no longer have an init_tasks structure
51 * so we need some other way of telling a new secondary core
52 * where to place its SVC stack
53 */
54struct secondary_data secondary_data;
55
28e8e29c
MZ
56/*
57 * control for which core is the next to come out of the secondary
58 * boot "holding pen"
59 */
8bd26e3a 60volatile int pen_release = -1;
28e8e29c 61
1da177e4 62enum ipi_msg_type {
559a5939
SB
63 IPI_WAKEUP,
64 IPI_TIMER,
1da177e4
LT
65 IPI_RESCHEDULE,
66 IPI_CALL_FUNC,
f6dd9fa5 67 IPI_CALL_FUNC_SINGLE,
1da177e4
LT
68 IPI_CPU_STOP,
69};
70
149c2415
RK
71static DECLARE_COMPLETION(cpu_running);
72
abcee5fb
MZ
73static struct smp_operations smp_ops;
74
75void __init smp_set_ops(struct smp_operations *ops)
76{
77 if (ops)
78 smp_ops = *ops;
79};
80
4756dcbf
CC
81static unsigned long get_arch_pgd(pgd_t *pgd)
82{
83 phys_addr_t pgdir = virt_to_phys(pgd);
84 BUG_ON(pgdir & ARCH_PGD_MASK);
85 return pgdir >> ARCH_PGD_SHIFT;
86}
87
8bd26e3a 88int __cpu_up(unsigned int cpu, struct task_struct *idle)
1da177e4 89{
1da177e4
LT
90 int ret;
91
e65f38ed
RK
92 /*
93 * We need to tell the secondary core where to find
94 * its stack and the page tables.
95 */
32d39a93 96 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
eb08375e
JA
97#ifdef CONFIG_ARM_MPU
98 secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr;
99#endif
100
c4a1f032 101#ifdef CONFIG_MMU
4756dcbf
CC
102 secondary_data.pgdir = get_arch_pgd(idmap_pgd);
103 secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
c4a1f032 104#endif
1027247f
RK
105 __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
106 outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
e65f38ed 107
1da177e4
LT
108 /*
109 * Now bring the CPU into our world.
110 */
111 ret = boot_secondary(cpu, idle);
e65f38ed 112 if (ret == 0) {
e65f38ed
RK
113 /*
114 * CPU was successfully started, wait for it
115 * to come online or time out.
116 */
149c2415
RK
117 wait_for_completion_timeout(&cpu_running,
118 msecs_to_jiffies(1000));
e65f38ed 119
58613cd1
RK
120 if (!cpu_online(cpu)) {
121 pr_crit("CPU%u: failed to come online\n", cpu);
e65f38ed 122 ret = -EIO;
58613cd1
RK
123 }
124 } else {
125 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
e65f38ed
RK
126 }
127
e65f38ed 128
eb08375e 129 memset(&secondary_data, 0, sizeof(secondary_data));
1da177e4
LT
130 return ret;
131}
132
abcee5fb 133/* platform specific SMP operations */
ac6c7998 134void __init smp_init_cpus(void)
abcee5fb
MZ
135{
136 if (smp_ops.smp_init_cpus)
137 smp_ops.smp_init_cpus();
138}
139
8bd26e3a 140int boot_secondary(unsigned int cpu, struct task_struct *idle)
abcee5fb
MZ
141{
142 if (smp_ops.smp_boot_secondary)
143 return smp_ops.smp_boot_secondary(cpu, idle);
144 return -ENOSYS;
145}
146
2103f6cb
SW
147int platform_can_cpu_hotplug(void)
148{
149#ifdef CONFIG_HOTPLUG_CPU
150 if (smp_ops.cpu_kill)
151 return 1;
152#endif
153
154 return 0;
155}
156
a054a811 157#ifdef CONFIG_HOTPLUG_CPU
ac6c7998 158static int platform_cpu_kill(unsigned int cpu)
abcee5fb
MZ
159{
160 if (smp_ops.cpu_kill)
161 return smp_ops.cpu_kill(cpu);
162 return 1;
163}
164
ac6c7998 165static int platform_cpu_disable(unsigned int cpu)
abcee5fb
MZ
166{
167 if (smp_ops.cpu_disable)
168 return smp_ops.cpu_disable(cpu);
169
170 /*
171 * By default, allow disabling all CPUs except the first one,
172 * since this is special on a lot of platforms, e.g. because
173 * of clock tick interrupts.
174 */
175 return cpu == 0 ? -EPERM : 0;
176}
a054a811
RK
177/*
178 * __cpu_disable runs on the processor to be shutdown.
179 */
8bd26e3a 180int __cpu_disable(void)
a054a811
RK
181{
182 unsigned int cpu = smp_processor_id();
a054a811
RK
183 int ret;
184
8e2a43f5 185 ret = platform_cpu_disable(cpu);
a054a811
RK
186 if (ret)
187 return ret;
188
189 /*
190 * Take this CPU offline. Once we clear this, we can't return,
191 * and we must not schedule until we're ready to give up the cpu.
192 */
e03cdade 193 set_cpu_online(cpu, false);
a054a811
RK
194
195 /*
196 * OK - migrate IRQs away from this CPU
197 */
198 migrate_irqs();
199
200 /*
201 * Flush user cache and TLB mappings, and then remove this CPU
202 * from the vm mask set of all processes.
e6b866e9
LP
203 *
204 * Caches are flushed to the Level of Unification Inner Shareable
205 * to write-back dirty lines to unified caches shared by all CPUs.
a054a811 206 */
e6b866e9 207 flush_cache_louis();
a054a811
RK
208 local_flush_tlb_all();
209
3eaa73bd 210 clear_tasks_mm_cpumask(cpu);
a054a811
RK
211
212 return 0;
213}
214
3c030bea
RK
215static DECLARE_COMPLETION(cpu_died);
216
a054a811
RK
217/*
218 * called on the thread which is asking for a CPU to be shutdown -
219 * waits until shutdown has completed, or it is timed out.
220 */
8bd26e3a 221void __cpu_die(unsigned int cpu)
a054a811 222{
3c030bea
RK
223 if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
224 pr_err("CPU%u: cpu didn't die\n", cpu);
225 return;
226 }
227 printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
228
51acdfd1
RK
229 /*
230 * platform_cpu_kill() is generally expected to do the powering off
231 * and/or cutting of clocks to the dying CPU. Optionally, this may
232 * be done by the CPU which is dying in preference to supporting
233 * this call, but that means there is _no_ synchronisation between
234 * the requesting CPU and the dying CPU actually losing power.
235 */
a054a811
RK
236 if (!platform_cpu_kill(cpu))
237 printk("CPU%u: unable to kill\n", cpu);
238}
239
240/*
241 * Called from the idle thread for the CPU which has been shutdown.
242 *
243 * Note that we disable IRQs here, but do not re-enable them
244 * before returning to the caller. This is also the behaviour
245 * of the other hotplug-cpu capable cores, so presumably coming
246 * out of idle fixes this.
247 */
90140c30 248void __ref cpu_die(void)
a054a811
RK
249{
250 unsigned int cpu = smp_processor_id();
251
a054a811
RK
252 idle_task_exit();
253
f36d3401 254 local_irq_disable();
f36d3401 255
51acdfd1
RK
256 /*
257 * Flush the data out of the L1 cache for this CPU. This must be
258 * before the completion to ensure that data is safely written out
259 * before platform_cpu_kill() gets called - which may disable
260 * *this* CPU and power down its cache.
261 */
262 flush_cache_louis();
263
264 /*
265 * Tell __cpu_die() that this CPU is now safe to dispose of. Once
266 * this returns, power and/or clocks can be removed at any point
267 * from this CPU and its cache by platform_cpu_kill().
268 */
aa033810 269 complete(&cpu_died);
3c030bea 270
a054a811 271 /*
51acdfd1
RK
272 * Ensure that the cache lines associated with that completion are
273 * written out. This covers the case where _this_ CPU is doing the
274 * powering down, to ensure that the completion is visible to the
275 * CPU waiting for this one.
276 */
277 flush_cache_louis();
278
279 /*
280 * The actual CPU shutdown procedure is at least platform (if not
281 * CPU) specific. This may remove power, or it may simply spin.
282 *
283 * Platforms are generally expected *NOT* to return from this call,
284 * although there are some which do because they have no way to
285 * power down the CPU. These platforms are the _only_ reason we
286 * have a return path which uses the fragment of assembly below.
287 *
288 * The return path should not be used for platforms which can
289 * power off the CPU.
a054a811 290 */
0a301110
RK
291 if (smp_ops.cpu_die)
292 smp_ops.cpu_die(cpu);
a054a811
RK
293
294 /*
295 * Do not return to the idle loop - jump back to the secondary
296 * cpu initialisation. There's some initialisation which needs
297 * to be repeated to undo the effects of taking the CPU offline.
298 */
299 __asm__("mov sp, %0\n"
faabfa08 300 " mov fp, #0\n"
a054a811
RK
301 " b secondary_start_kernel"
302 :
32d39a93 303 : "r" (task_stack_page(current) + THREAD_SIZE - 8));
a054a811
RK
304}
305#endif /* CONFIG_HOTPLUG_CPU */
306
05c74a6c
RK
307/*
308 * Called by both boot and secondaries to move global data into
309 * per-processor storage.
310 */
8bd26e3a 311static void smp_store_cpu_info(unsigned int cpuid)
05c74a6c
RK
312{
313 struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
314
315 cpu_info->loops_per_jiffy = loops_per_jiffy;
e8d432c9 316 cpu_info->cpuid = read_cpuid_id();
c9018aab
VG
317
318 store_cpu_topology(cpuid);
05c74a6c
RK
319}
320
e65f38ed
RK
321/*
322 * This is the secondary CPU boot entry. We're using this CPUs
323 * idle thread stack, but a set of temporary page tables.
324 */
8bd26e3a 325asmlinkage void secondary_start_kernel(void)
e65f38ed
RK
326{
327 struct mm_struct *mm = &init_mm;
5f40b909
WD
328 unsigned int cpu;
329
330 /*
331 * The identity mapping is uncached (strongly ordered), so
332 * switch away from it before attempting any exclusive accesses.
333 */
334 cpu_switch_mm(mm->pgd, mm);
89c7e4b8 335 local_flush_bp_all();
5f40b909
WD
336 enter_lazy_tlb(mm, current);
337 local_flush_tlb_all();
e65f38ed 338
e65f38ed
RK
339 /*
340 * All kernel threads share the same mm context; grab a
341 * reference and switch to it.
342 */
5f40b909 343 cpu = smp_processor_id();
e65f38ed
RK
344 atomic_inc(&mm->mm_count);
345 current->active_mm = mm;
56f8ba83 346 cpumask_set_cpu(cpu, mm_cpumask(mm));
e65f38ed 347
14318efb
RH
348 cpu_init();
349
fde165b2
CC
350 printk("CPU%u: Booted secondary processor\n", cpu);
351
5bfb5d69 352 preempt_disable();
2c0136db 353 trace_hardirqs_off();
e65f38ed
RK
354
355 /*
356 * Give the platform a chance to do its own initialisation.
357 */
0a301110
RK
358 if (smp_ops.smp_secondary_init)
359 smp_ops.smp_secondary_init(cpu);
e65f38ed 360
e545a614 361 notify_cpu_starting(cpu);
a8655e83 362
e65f38ed
RK
363 calibrate_delay();
364
365 smp_store_cpu_info(cpu);
366
367 /*
573619d1
RK
368 * OK, now it's safe to let the boot CPU continue. Wait for
369 * the CPU migration code to notice that the CPU is online
149c2415 370 * before we continue - which happens after __cpu_up returns.
e65f38ed 371 */
e03cdade 372 set_cpu_online(cpu, true);
149c2415 373 complete(&cpu_running);
eb047454 374
eb047454
TG
375 local_irq_enable();
376 local_fiq_enable();
377
e65f38ed
RK
378 /*
379 * OK, it's off to the idle thread for us
380 */
f7b861b7 381 cpu_startup_entry(CPUHP_ONLINE);
e65f38ed
RK
382}
383
1da177e4
LT
384void __init smp_cpus_done(unsigned int max_cpus)
385{
9fc2105a
WD
386 printk(KERN_INFO "SMP: Total of %d processors activated.\n",
387 num_online_cpus());
4588c34d
DM
388
389 hyp_mode_check();
1da177e4
LT
390}
391
392void __init smp_prepare_boot_cpu(void)
393{
14318efb 394 set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
1da177e4
LT
395}
396
05c74a6c 397void __init smp_prepare_cpus(unsigned int max_cpus)
1da177e4 398{
05c74a6c 399 unsigned int ncores = num_possible_cpus();
1da177e4 400
c9018aab
VG
401 init_cpu_topology();
402
05c74a6c 403 smp_store_cpu_info(smp_processor_id());
1da177e4
LT
404
405 /*
05c74a6c 406 * are we trying to boot more cores than exist?
1da177e4 407 */
05c74a6c
RK
408 if (max_cpus > ncores)
409 max_cpus = ncores;
7fa22bd5 410 if (ncores > 1 && max_cpus) {
7fa22bd5
SB
411 /*
412 * Initialise the present map, which describes the set of CPUs
413 * actually populated at the present time. A platform should
0a301110
RK
414 * re-initialize the map in the platforms smp_prepare_cpus()
415 * if present != possible (e.g. physical hotplug).
7fa22bd5 416 */
0b5f9c00 417 init_cpu_present(cpu_possible_mask);
7fa22bd5 418
05c74a6c
RK
419 /*
420 * Initialise the SCU if there are more than one CPU
421 * and let them know where to start.
422 */
0a301110
RK
423 if (smp_ops.smp_prepare_cpus)
424 smp_ops.smp_prepare_cpus(max_cpus);
05c74a6c 425 }
1da177e4
LT
426}
427
0f7b332f
RK
428static void (*smp_cross_call)(const struct cpumask *, unsigned int);
429
430void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
431{
b1cffebf
RH
432 if (!smp_cross_call)
433 smp_cross_call = fn;
0f7b332f
RK
434}
435
82668104 436void arch_send_call_function_ipi_mask(const struct cpumask *mask)
1da177e4 437{
e3fbb087 438 smp_cross_call(mask, IPI_CALL_FUNC);
1da177e4
LT
439}
440
b62655f4
SG
441void arch_send_wakeup_ipi_mask(const struct cpumask *mask)
442{
443 smp_cross_call(mask, IPI_WAKEUP);
444}
445
f6dd9fa5 446void arch_send_call_function_single_ipi(int cpu)
3e459990 447{
e3fbb087 448 smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
3e459990 449}
3e459990 450
4a88abd7 451static const char *ipi_types[NR_IPI] = {
559a5939
SB
452#define S(x,s) [x] = s
453 S(IPI_WAKEUP, "CPU wakeup interrupts"),
4a88abd7
RK
454 S(IPI_TIMER, "Timer broadcast interrupts"),
455 S(IPI_RESCHEDULE, "Rescheduling interrupts"),
456 S(IPI_CALL_FUNC, "Function call interrupts"),
457 S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
458 S(IPI_CPU_STOP, "CPU stop interrupts"),
459};
460
f13cd417 461void show_ipi_list(struct seq_file *p, int prec)
1da177e4 462{
4a88abd7 463 unsigned int cpu, i;
1da177e4 464
4a88abd7
RK
465 for (i = 0; i < NR_IPI; i++) {
466 seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
1da177e4 467
026b7c6b 468 for_each_online_cpu(cpu)
4a88abd7
RK
469 seq_printf(p, "%10u ",
470 __get_irq_stat(cpu, ipi_irqs[i]));
1da177e4 471
4a88abd7
RK
472 seq_printf(p, " %s\n", ipi_types[i]);
473 }
1da177e4
LT
474}
475
b54992fe 476u64 smp_irq_stat_cpu(unsigned int cpu)
37ee16ae 477{
b54992fe
RK
478 u64 sum = 0;
479 int i;
37ee16ae 480
b54992fe
RK
481 for (i = 0; i < NR_IPI; i++)
482 sum += __get_irq_stat(cpu, ipi_irqs[i]);
37ee16ae 483
b54992fe 484 return sum;
37ee16ae
RK
485}
486
bc28248e 487#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
3d06770e 488void tick_broadcast(const struct cpumask *mask)
bc28248e 489{
e3fbb087 490 smp_cross_call(mask, IPI_TIMER);
bc28248e 491}
5388a6b2 492#endif
bc28248e 493
bd31b859 494static DEFINE_RAW_SPINLOCK(stop_lock);
1da177e4
LT
495
496/*
497 * ipi_cpu_stop - handle IPI from smp_send_stop()
498 */
499static void ipi_cpu_stop(unsigned int cpu)
500{
3d3f78d7
RK
501 if (system_state == SYSTEM_BOOTING ||
502 system_state == SYSTEM_RUNNING) {
bd31b859 503 raw_spin_lock(&stop_lock);
3d3f78d7
RK
504 printk(KERN_CRIT "CPU%u: stopping\n", cpu);
505 dump_stack();
bd31b859 506 raw_spin_unlock(&stop_lock);
3d3f78d7 507 }
1da177e4 508
e03cdade 509 set_cpu_online(cpu, false);
1da177e4
LT
510
511 local_fiq_disable();
512 local_irq_disable();
513
514 while (1)
515 cpu_relax();
516}
517
518/*
519 * Main handler for inter-processor interrupts
1da177e4 520 */
4073723a 521asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs)
0b5a1b95
SG
522{
523 handle_IPI(ipinr, regs);
524}
525
526void handle_IPI(int ipinr, struct pt_regs *regs)
1da177e4
LT
527{
528 unsigned int cpu = smp_processor_id();
c97d4869 529 struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 530
559a5939
SB
531 if (ipinr < NR_IPI)
532 __inc_irq_stat(cpu, ipi_irqs[ipinr]);
1da177e4 533
24480d98 534 switch (ipinr) {
559a5939
SB
535 case IPI_WAKEUP:
536 break;
537
e2c50119 538#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
24480d98 539 case IPI_TIMER:
7deabca0 540 irq_enter();
e2c50119 541 tick_receive_broadcast();
7deabca0 542 irq_exit();
24480d98 543 break;
e2c50119 544#endif
1da177e4 545
24480d98 546 case IPI_RESCHEDULE:
184748cc 547 scheduler_ipi();
24480d98 548 break;
1da177e4 549
24480d98 550 case IPI_CALL_FUNC:
7deabca0 551 irq_enter();
24480d98 552 generic_smp_call_function_interrupt();
7deabca0 553 irq_exit();
24480d98 554 break;
f6dd9fa5 555
24480d98 556 case IPI_CALL_FUNC_SINGLE:
7deabca0 557 irq_enter();
24480d98 558 generic_smp_call_function_single_interrupt();
7deabca0 559 irq_exit();
24480d98 560 break;
1da177e4 561
24480d98 562 case IPI_CPU_STOP:
7deabca0 563 irq_enter();
24480d98 564 ipi_cpu_stop(cpu);
7deabca0 565 irq_exit();
24480d98 566 break;
1da177e4 567
24480d98
RK
568 default:
569 printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n",
570 cpu, ipinr);
571 break;
1da177e4 572 }
c97d4869 573 set_irq_regs(old_regs);
1da177e4
LT
574}
575
576void smp_send_reschedule(int cpu)
577{
e3fbb087 578 smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
1da177e4
LT
579}
580
1da177e4
LT
581void smp_send_stop(void)
582{
28e18293 583 unsigned long timeout;
6fa99b7f 584 struct cpumask mask;
1da177e4 585
6fa99b7f
WD
586 cpumask_copy(&mask, cpu_online_mask);
587 cpumask_clear_cpu(smp_processor_id(), &mask);
c5dff4ff
JMC
588 if (!cpumask_empty(&mask))
589 smp_cross_call(&mask, IPI_CPU_STOP);
4b0ef3b1 590
28e18293
RK
591 /* Wait up to one second for other CPUs to stop */
592 timeout = USEC_PER_SEC;
593 while (num_online_cpus() > 1 && timeout--)
594 udelay(1);
4b0ef3b1 595
28e18293
RK
596 if (num_online_cpus() > 1)
597 pr_warning("SMP: failed to stop secondary CPUs\n");
4b0ef3b1
RK
598}
599
4b0ef3b1 600/*
1da177e4 601 * not supported here
4b0ef3b1 602 */
5048bcba 603int setup_profiling_timer(unsigned int multiplier)
4b0ef3b1 604{
1da177e4 605 return -EINVAL;
4b0ef3b1 606}
ec971ea5
RZ
607
608#ifdef CONFIG_CPU_FREQ
609
610static DEFINE_PER_CPU(unsigned long, l_p_j_ref);
611static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq);
612static unsigned long global_l_p_j_ref;
613static unsigned long global_l_p_j_ref_freq;
614
615static int cpufreq_callback(struct notifier_block *nb,
616 unsigned long val, void *data)
617{
618 struct cpufreq_freqs *freq = data;
619 int cpu = freq->cpu;
620
621 if (freq->flags & CPUFREQ_CONST_LOOPS)
622 return NOTIFY_OK;
623
624 if (!per_cpu(l_p_j_ref, cpu)) {
625 per_cpu(l_p_j_ref, cpu) =
626 per_cpu(cpu_data, cpu).loops_per_jiffy;
627 per_cpu(l_p_j_ref_freq, cpu) = freq->old;
628 if (!global_l_p_j_ref) {
629 global_l_p_j_ref = loops_per_jiffy;
630 global_l_p_j_ref_freq = freq->old;
631 }
632 }
633
634 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
635 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
636 (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) {
637 loops_per_jiffy = cpufreq_scale(global_l_p_j_ref,
638 global_l_p_j_ref_freq,
639 freq->new);
640 per_cpu(cpu_data, cpu).loops_per_jiffy =
641 cpufreq_scale(per_cpu(l_p_j_ref, cpu),
642 per_cpu(l_p_j_ref_freq, cpu),
643 freq->new);
644 }
645 return NOTIFY_OK;
646}
647
648static struct notifier_block cpufreq_notifier = {
649 .notifier_call = cpufreq_callback,
650};
651
652static int __init register_cpufreq_notifier(void)
653{
654 return cpufreq_register_notifier(&cpufreq_notifier,
655 CPUFREQ_TRANSITION_NOTIFIER);
656}
657core_initcall(register_cpufreq_notifier);
658
659#endif