ARM: 8744/1: don't discard memblock for kexec
[linux-block.git] / arch / arm / kernel / head-common.S
CommitLineData
75d90832
HC
1/*
2 * linux/arch/arm/kernel/head-common.S
3 *
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
6ebbf2ce 13#include <asm/assembler.h>
75d90832 14
9c4c9f38
GU
15#define ATAG_CORE 0x54410001
16#define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2)
31abdb74 17#define ATAG_CORE_SIZE_EMPTY ((2*4) >> 2)
9c4c9f38 18
4c2896e8
GL
19#ifdef CONFIG_CPU_BIG_ENDIAN
20#define OF_DT_MAGIC 0xd00dfeed
21#else
22#define OF_DT_MAGIC 0xedfe0dd0 /* 0xd00dfeed in big-endian */
23#endif
24
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HC
25/*
26 * Exception handling. Something went wrong and we can't proceed. We
27 * ought to tell the user, but since we don't have any guarantee that
28 * we're even running on the right architecture, we do virtually nothing.
29 *
30 * If CONFIG_DEBUG_LL is set we try to print out something about the error
31 * and hope for the best (useful if bootloader fails to pass a proper
32 * machine ID for example).
33 */
80924ac5 34 __HEAD
9d20fdd5
BG
35
36/* Determine validity of the r2 atags pointer. The heuristic requires
37 * that the pointer be aligned, in the first 16k of physical RAM and
4c2896e8
GL
38 * that the ATAG_CORE marker is first and present. If CONFIG_OF_FLATTREE
39 * is selected, then it will also accept a dtb pointer. Future revisions
9d20fdd5
BG
40 * of this function may be more lenient with the physical address and
41 * may also be able to move the ATAGS block if necessary.
42 *
9d20fdd5 43 * Returns:
4c2896e8 44 * r2 either valid atags pointer, valid dtb pointer, or zero
9d20fdd5
BG
45 * r5, r6 corrupted
46 */
9d20fdd5
BG
47__vet_atags:
48 tst r2, #0x3 @ aligned?
49 bne 1f
50
4c2896e8
GL
51 ldr r5, [r2, #0]
52#ifdef CONFIG_OF_FLATTREE
53 ldr r6, =OF_DT_MAGIC @ is it a DTB?
54 cmp r5, r6
55 beq 2f
56#endif
57 cmp r5, #ATAG_CORE_SIZE @ is first tag ATAG_CORE?
31abdb74 58 cmpne r5, #ATAG_CORE_SIZE_EMPTY
9d20fdd5
BG
59 bne 1f
60 ldr r5, [r2, #4]
61 ldr r6, =ATAG_CORE
62 cmp r5, r6
63 bne 1f
64
6ebbf2ce 652: ret lr @ atag/dtb pointer is ok
9d20fdd5
BG
66
671: mov r2, #0
6ebbf2ce 68 ret lr
93ed3970 69ENDPROC(__vet_atags)
5085f3ff 70
17bb5e2c
RK
71/*
72 * The following fragment of code is executed with the MMU on in MMU mode,
73 * and uses absolute addresses; this is not position independent.
74 *
75 * r0 = cp#15 control register
76 * r1 = machine ID
4c2896e8 77 * r2 = atags/dtb pointer
17bb5e2c
RK
78 * r9 = processor ID
79 */
80 __INIT
81__mmap_switched:
9520b1a1
NP
82
83 mov r7, r1
84 mov r8, r2
85 mov r10, r0
86
87 adr r4, __mmap_switched_data
88 mov fp, #0
89
ca8b5d97
NP
90#if defined(CONFIG_XIP_DEFLATED_DATA)
91 ARM( ldr sp, [r4], #4 )
92 THUMB( ldr sp, [r4] )
93 THUMB( add r4, #4 )
94 bl __inflate_kernel_data @ decompress .data to RAM
95 teq r0, #0
96 bne __error
97#elif defined(CONFIG_XIP_KERNEL)
9520b1a1
NP
98 ARM( ldmia r4!, {r0, r1, r2, sp} )
99 THUMB( ldmia r4!, {r0, r1, r2, r3} )
100 THUMB( mov sp, r3 )
101 sub r2, r2, r1
102 bl memcpy @ copy .data to RAM
103#endif
104
105 ARM( ldmia r4!, {r0, r1, sp} )
106 THUMB( ldmia r4!, {r0, r1, r3} )
107 THUMB( mov sp, r3 )
108 sub r1, r1, r0
109 bl __memzero @ clear .bss
110
111 ldmia r4, {r0, r1, r2, r3}
112 str r9, [r0] @ Save processor ID
113 str r7, [r1] @ Save machine type
114 str r8, [r2] @ Save atags pointer
115 cmp r3, #0
116 strne r10, [r3] @ Save control register values
59b6359d 117 mov lr, #0
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118 b start_kernel
119ENDPROC(__mmap_switched)
120
121 .align 2
122 .type __mmap_switched_data, %object
123__mmap_switched_data:
9520b1a1 124#ifdef CONFIG_XIP_KERNEL
ca8b5d97 125#ifndef CONFIG_XIP_DEFLATED_DATA
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NP
126 .long _sdata @ r0
127 .long __data_loc @ r1
128 .long _edata_loc @ r2
ca8b5d97 129#endif
9520b1a1
NP
130 .long __bss_stop @ sp (temporary stack in .bss)
131#endif
132
133 .long __bss_start @ r0
134 .long __bss_stop @ r1
135 .long init_thread_union + THREAD_START_SP @ sp
136
137 .long processor_id @ r0
138 .long __machine_arch_type @ r1
139 .long __atags_pointer @ r2
b849a60e 140#ifdef CONFIG_CPU_CP15
9520b1a1 141 .long cr_alignment @ r3
b849a60e 142#else
9520b1a1 143 .long 0 @ r3
b849a60e 144#endif
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145 .size __mmap_switched_data, . - __mmap_switched_data
146
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147/*
148 * This provides a C-API version of __lookup_processor_type
149 */
150ENTRY(lookup_processor_type)
151 stmfd sp!, {r4 - r6, r9, lr}
152 mov r9, r0
153 bl __lookup_processor_type
154 mov r0, r5
155 ldmfd sp!, {r4 - r6, r9, pc}
156ENDPROC(lookup_processor_type)
157
8c69d7af
SW
158 __FINIT
159 .text
160
5085f3ff
RK
161/*
162 * Read processor ID register (CP#15, CR0), and look up in the linker-built
163 * supported processor list. Note that we can't use the absolute addresses
164 * for the __proc_info lists since we aren't running with the MMU on
165 * (and therefore, we are not in the correct address space). We have to
166 * calculate the offset.
167 *
168 * r9 = cpuid
169 * Returns:
170 * r3, r4, r6 corrupted
171 * r5 = proc_info pointer in physical address space
172 * r9 = cpuid (preserved)
173 */
5085f3ff
RK
174__lookup_processor_type:
175 adr r3, __lookup_processor_type_data
176 ldmia r3, {r4 - r6}
177 sub r3, r3, r4 @ get offset between virt&phys
178 add r5, r5, r3 @ convert virt addresses to
179 add r6, r6, r3 @ physical address space
1801: ldmia r5, {r3, r4} @ value, mask
181 and r4, r4, r9 @ mask wanted bits
182 teq r3, r4
183 beq 2f
184 add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
185 cmp r5, r6
186 blo 1b
187 mov r5, #0 @ unknown processor
6ebbf2ce 1882: ret lr
5085f3ff
RK
189ENDPROC(__lookup_processor_type)
190
191/*
192 * Look in <asm/procinfo.h> for information about the __proc_info structure.
193 */
194 .align 2
195 .type __lookup_processor_type_data, %object
196__lookup_processor_type_data:
197 .long .
198 .long __proc_info_begin
199 .long __proc_info_end
200 .size __lookup_processor_type_data, . - __lookup_processor_type_data
c083c660 201
b3634575
TP
202__error_lpae:
203#ifdef CONFIG_DEBUG_LL
204 adr r0, str_lpae
205 bl printascii
206 b __error
207str_lpae: .asciz "\nError: Kernel with LPAE support, but CPU does not support LPAE.\n"
208#else
209 b __error
210#endif
211 .align
212ENDPROC(__error_lpae)
213
c083c660
RK
214__error_p:
215#ifdef CONFIG_DEBUG_LL
216 adr r0, str_p1
217 bl printascii
218 mov r0, r9
219 bl printhex8
220 adr r0, str_p2
221 bl printascii
222 b __error
223str_p1: .asciz "\nError: unrecognized/unsupported processor variant (0x"
224str_p2: .asciz ").\n"
225 .align
226#endif
227ENDPROC(__error_p)
228
229__error:
230#ifdef CONFIG_ARCH_RPC
231/*
232 * Turn the screen red on a error - RiscPC only.
233 */
234 mov r0, #0x02000000
235 mov r3, #0x11
236 orr r3, r3, r3, lsl #8
237 orr r3, r3, r3, lsl #16
238 str r3, [r0], #4
239 str r3, [r0], #4
240 str r3, [r0], #4
241 str r3, [r0], #4
242#endif
2431: mov r0, r0
244 b 1b
245ENDPROC(__error)