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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes | |
15 | * it to save wrong values... Be aware! | |
16 | */ | |
1da177e4 | 17 | |
f09b9979 | 18 | #include <asm/memory.h> |
1da177e4 | 19 | #include <asm/glue.h> |
1da177e4 | 20 | #include <asm/vfpmacros.h> |
bce495d8 | 21 | #include <asm/arch/entry-macro.S> |
d6551e88 | 22 | #include <asm/thread_notify.h> |
1da177e4 LT |
23 | |
24 | #include "entry-header.S" | |
25 | ||
187a51ad RK |
26 | /* |
27 | * Interrupt handling. Preserves r7, r8, r9 | |
28 | */ | |
29 | .macro irq_handler | |
30 | 1: get_irqnr_and_base r0, r6, r5, lr | |
31 | movne r1, sp | |
32 | @ | |
33 | @ routine called with r0 = irq number, r1 = struct pt_regs * | |
34 | @ | |
35 | adrne lr, 1b | |
36 | bne asm_do_IRQ | |
791be9b9 RK |
37 | |
38 | #ifdef CONFIG_SMP | |
39 | /* | |
40 | * XXX | |
41 | * | |
42 | * this macro assumes that irqstat (r6) and base (r5) are | |
43 | * preserved from get_irqnr_and_base above | |
44 | */ | |
45 | test_for_ipi r0, r6, r5, lr | |
46 | movne r0, sp | |
47 | adrne lr, 1b | |
48 | bne do_IPI | |
37ee16ae RK |
49 | |
50 | #ifdef CONFIG_LOCAL_TIMERS | |
51 | test_for_ltirq r0, r6, r5, lr | |
52 | movne r0, sp | |
53 | adrne lr, 1b | |
54 | bne do_local_timer | |
55 | #endif | |
791be9b9 RK |
56 | #endif |
57 | ||
187a51ad RK |
58 | .endm |
59 | ||
1da177e4 LT |
60 | /* |
61 | * Invalid mode handlers | |
62 | */ | |
ccea7a19 RK |
63 | .macro inv_entry, reason |
64 | sub sp, sp, #S_FRAME_SIZE | |
65 | stmib sp, {r1 - lr} | |
1da177e4 LT |
66 | mov r1, #\reason |
67 | .endm | |
68 | ||
69 | __pabt_invalid: | |
ccea7a19 RK |
70 | inv_entry BAD_PREFETCH |
71 | b common_invalid | |
1da177e4 LT |
72 | |
73 | __dabt_invalid: | |
ccea7a19 RK |
74 | inv_entry BAD_DATA |
75 | b common_invalid | |
1da177e4 LT |
76 | |
77 | __irq_invalid: | |
ccea7a19 RK |
78 | inv_entry BAD_IRQ |
79 | b common_invalid | |
1da177e4 LT |
80 | |
81 | __und_invalid: | |
ccea7a19 RK |
82 | inv_entry BAD_UNDEFINSTR |
83 | ||
84 | @ | |
85 | @ XXX fall through to common_invalid | |
86 | @ | |
87 | ||
88 | @ | |
89 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
90 | @ | |
91 | common_invalid: | |
92 | zero_fp | |
93 | ||
94 | ldmia r0, {r4 - r6} | |
95 | add r0, sp, #S_PC @ here for interlock avoidance | |
96 | mov r7, #-1 @ "" "" "" "" | |
97 | str r4, [sp] @ save preserved r0 | |
98 | stmia r0, {r5 - r7} @ lr_<exception>, | |
99 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 100 | |
1da177e4 | 101 | mov r0, sp |
1da177e4 LT |
102 | b bad_mode |
103 | ||
104 | /* | |
105 | * SVC mode handlers | |
106 | */ | |
2dede2d8 NP |
107 | |
108 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
109 | #define SPFIX(code...) code | |
110 | #else | |
111 | #define SPFIX(code...) | |
112 | #endif | |
113 | ||
ccea7a19 | 114 | .macro svc_entry |
1da177e4 | 115 | sub sp, sp, #S_FRAME_SIZE |
2dede2d8 NP |
116 | SPFIX( tst sp, #4 ) |
117 | SPFIX( bicne sp, sp, #4 ) | |
ccea7a19 RK |
118 | stmib sp, {r1 - r12} |
119 | ||
120 | ldmia r0, {r1 - r3} | |
121 | add r5, sp, #S_SP @ here for interlock avoidance | |
122 | mov r4, #-1 @ "" "" "" "" | |
123 | add r0, sp, #S_FRAME_SIZE @ "" "" "" "" | |
2dede2d8 | 124 | SPFIX( addne r0, r0, #4 ) |
ccea7a19 RK |
125 | str r1, [sp] @ save the "real" r0 copied |
126 | @ from the exception stack | |
127 | ||
1da177e4 LT |
128 | mov r1, lr |
129 | ||
130 | @ | |
131 | @ We are now ready to fill in the remaining blanks on the stack: | |
132 | @ | |
133 | @ r0 - sp_svc | |
134 | @ r1 - lr_svc | |
135 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
136 | @ r3 - spsr_<exception> | |
137 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
138 | @ | |
139 | stmia r5, {r0 - r4} | |
140 | .endm | |
141 | ||
142 | .align 5 | |
143 | __dabt_svc: | |
ccea7a19 | 144 | svc_entry |
1da177e4 LT |
145 | |
146 | @ | |
147 | @ get ready to re-enable interrupts if appropriate | |
148 | @ | |
149 | mrs r9, cpsr | |
150 | tst r3, #PSR_I_BIT | |
151 | biceq r9, r9, #PSR_I_BIT | |
152 | ||
153 | @ | |
154 | @ Call the processor-specific abort handler: | |
155 | @ | |
156 | @ r2 - aborted context pc | |
157 | @ r3 - aborted context cpsr | |
158 | @ | |
159 | @ The abort handler must return the aborted address in r0, and | |
160 | @ the fault status register in r1. r9 must be preserved. | |
161 | @ | |
162 | #ifdef MULTI_ABORT | |
163 | ldr r4, .LCprocfns | |
164 | mov lr, pc | |
165 | ldr pc, [r4] | |
166 | #else | |
167 | bl CPU_ABORT_HANDLER | |
168 | #endif | |
169 | ||
170 | @ | |
171 | @ set desired IRQ state, then call main handler | |
172 | @ | |
173 | msr cpsr_c, r9 | |
174 | mov r2, sp | |
175 | bl do_DataAbort | |
176 | ||
177 | @ | |
178 | @ IRQs off again before pulling preserved data off the stack | |
179 | @ | |
1ec42c0c | 180 | disable_irq |
1da177e4 LT |
181 | |
182 | @ | |
183 | @ restore SPSR and restart the instruction | |
184 | @ | |
185 | ldr r0, [sp, #S_PSR] | |
186 | msr spsr_cxsf, r0 | |
187 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
188 | ||
189 | .align 5 | |
190 | __irq_svc: | |
ccea7a19 RK |
191 | svc_entry |
192 | ||
7ad1bcb2 RK |
193 | #ifdef CONFIG_TRACE_IRQFLAGS |
194 | bl trace_hardirqs_off | |
195 | #endif | |
1da177e4 | 196 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
197 | get_thread_info tsk |
198 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
199 | add r7, r8, #1 @ increment it | |
200 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 201 | #endif |
ccea7a19 | 202 | |
187a51ad | 203 | irq_handler |
1da177e4 | 204 | #ifdef CONFIG_PREEMPT |
706fdd9f | 205 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
1da177e4 LT |
206 | tst r0, #_TIF_NEED_RESCHED |
207 | blne svc_preempt | |
208 | preempt_return: | |
706fdd9f RK |
209 | ldr r0, [tsk, #TI_PREEMPT] @ read preempt value |
210 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count | |
1da177e4 | 211 | teq r0, r7 |
1da177e4 LT |
212 | strne r0, [r0, -r0] @ bug() |
213 | #endif | |
214 | ldr r0, [sp, #S_PSR] @ irqs are already disabled | |
215 | msr spsr_cxsf, r0 | |
7ad1bcb2 RK |
216 | #ifdef CONFIG_TRACE_IRQFLAGS |
217 | tst r0, #PSR_I_BIT | |
218 | bleq trace_hardirqs_on | |
219 | #endif | |
1da177e4 LT |
220 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr |
221 | ||
222 | .ltorg | |
223 | ||
224 | #ifdef CONFIG_PREEMPT | |
225 | svc_preempt: | |
706fdd9f | 226 | teq r8, #0 @ was preempt count = 0 |
1da177e4 LT |
227 | ldreq r6, .LCirq_stat |
228 | movne pc, lr @ no | |
229 | ldr r0, [r6, #4] @ local_irq_count | |
230 | ldr r1, [r6, #8] @ local_bh_count | |
231 | adds r0, r0, r1 | |
232 | movne pc, lr | |
233 | mov r7, #0 @ preempt_schedule_irq | |
706fdd9f | 234 | str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 |
1da177e4 | 235 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 236 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 LT |
237 | tst r0, #_TIF_NEED_RESCHED |
238 | beq preempt_return @ go again | |
239 | b 1b | |
240 | #endif | |
241 | ||
242 | .align 5 | |
243 | __und_svc: | |
ccea7a19 | 244 | svc_entry |
1da177e4 LT |
245 | |
246 | @ | |
247 | @ call emulation code, which returns using r9 if it has emulated | |
248 | @ the instruction, or the more conventional lr if we are to treat | |
249 | @ this as a real undefined instruction | |
250 | @ | |
251 | @ r0 - instruction | |
252 | @ | |
253 | ldr r0, [r2, #-4] | |
254 | adr r9, 1f | |
255 | bl call_fpe | |
256 | ||
257 | mov r0, sp @ struct pt_regs *regs | |
258 | bl do_undefinstr | |
259 | ||
260 | @ | |
261 | @ IRQs off again before pulling preserved data off the stack | |
262 | @ | |
1ec42c0c | 263 | 1: disable_irq |
1da177e4 LT |
264 | |
265 | @ | |
266 | @ restore SPSR and restart the instruction | |
267 | @ | |
268 | ldr lr, [sp, #S_PSR] @ Get SVC cpsr | |
269 | msr spsr_cxsf, lr | |
270 | ldmia sp, {r0 - pc}^ @ Restore SVC registers | |
271 | ||
272 | .align 5 | |
273 | __pabt_svc: | |
ccea7a19 | 274 | svc_entry |
1da177e4 LT |
275 | |
276 | @ | |
277 | @ re-enable interrupts if appropriate | |
278 | @ | |
279 | mrs r9, cpsr | |
280 | tst r3, #PSR_I_BIT | |
281 | biceq r9, r9, #PSR_I_BIT | |
282 | msr cpsr_c, r9 | |
283 | ||
284 | @ | |
285 | @ set args, then call main handler | |
286 | @ | |
287 | @ r0 - address of faulting instruction | |
288 | @ r1 - pointer to registers on stack | |
289 | @ | |
290 | mov r0, r2 @ address (pc) | |
291 | mov r1, sp @ regs | |
292 | bl do_PrefetchAbort @ call abort handler | |
293 | ||
294 | @ | |
295 | @ IRQs off again before pulling preserved data off the stack | |
296 | @ | |
1ec42c0c | 297 | disable_irq |
1da177e4 LT |
298 | |
299 | @ | |
300 | @ restore SPSR and restart the instruction | |
301 | @ | |
302 | ldr r0, [sp, #S_PSR] | |
303 | msr spsr_cxsf, r0 | |
304 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
305 | ||
306 | .align 5 | |
49f680ea RK |
307 | .LCcralign: |
308 | .word cr_alignment | |
1da177e4 LT |
309 | #ifdef MULTI_ABORT |
310 | .LCprocfns: | |
311 | .word processor | |
312 | #endif | |
313 | .LCfp: | |
314 | .word fp_enter | |
315 | #ifdef CONFIG_PREEMPT | |
316 | .LCirq_stat: | |
317 | .word irq_stat | |
318 | #endif | |
319 | ||
320 | /* | |
321 | * User mode handlers | |
2dede2d8 NP |
322 | * |
323 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 324 | */ |
2dede2d8 NP |
325 | |
326 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
327 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
328 | #endif | |
329 | ||
ccea7a19 RK |
330 | .macro usr_entry |
331 | sub sp, sp, #S_FRAME_SIZE | |
332 | stmib sp, {r1 - r12} | |
333 | ||
334 | ldmia r0, {r1 - r3} | |
335 | add r0, sp, #S_PC @ here for interlock avoidance | |
336 | mov r4, #-1 @ "" "" "" "" | |
337 | ||
338 | str r1, [sp] @ save the "real" r0 copied | |
339 | @ from the exception stack | |
1da177e4 | 340 | |
dcef1f63 | 341 | #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
49bca4c2 NP |
342 | #ifndef CONFIG_MMU |
343 | #warning "NPTL on non MMU needs fixing" | |
344 | #else | |
2d2669b6 | 345 | @ make sure our user space atomic helper is aborted |
f09b9979 | 346 | cmp r2, #TASK_SIZE |
2d2669b6 | 347 | bichs r3, r3, #PSR_Z_BIT |
49bca4c2 | 348 | #endif |
2d2669b6 NP |
349 | #endif |
350 | ||
1da177e4 LT |
351 | @ |
352 | @ We are now ready to fill in the remaining blanks on the stack: | |
353 | @ | |
354 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
355 | @ r3 - spsr_<exception> | |
356 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
357 | @ | |
358 | @ Also, separately save sp_usr and lr_usr | |
359 | @ | |
ccea7a19 RK |
360 | stmia r0, {r2 - r4} |
361 | stmdb r0, {sp, lr}^ | |
1da177e4 LT |
362 | |
363 | @ | |
364 | @ Enable the alignment trap while in kernel mode | |
365 | @ | |
49f680ea | 366 | alignment_trap r0 |
1da177e4 LT |
367 | |
368 | @ | |
369 | @ Clear FP to mark the first stack frame | |
370 | @ | |
371 | zero_fp | |
372 | .endm | |
373 | ||
374 | .align 5 | |
375 | __dabt_usr: | |
ccea7a19 | 376 | usr_entry |
1da177e4 LT |
377 | |
378 | @ | |
379 | @ Call the processor-specific abort handler: | |
380 | @ | |
381 | @ r2 - aborted context pc | |
382 | @ r3 - aborted context cpsr | |
383 | @ | |
384 | @ The abort handler must return the aborted address in r0, and | |
385 | @ the fault status register in r1. | |
386 | @ | |
387 | #ifdef MULTI_ABORT | |
388 | ldr r4, .LCprocfns | |
389 | mov lr, pc | |
390 | ldr pc, [r4] | |
391 | #else | |
392 | bl CPU_ABORT_HANDLER | |
393 | #endif | |
394 | ||
395 | @ | |
396 | @ IRQs on, then call the main handler | |
397 | @ | |
1ec42c0c | 398 | enable_irq |
1da177e4 LT |
399 | mov r2, sp |
400 | adr lr, ret_from_exception | |
401 | b do_DataAbort | |
402 | ||
403 | .align 5 | |
404 | __irq_usr: | |
ccea7a19 | 405 | usr_entry |
1da177e4 | 406 | |
7ad1bcb2 RK |
407 | #ifdef CONFIG_TRACE_IRQFLAGS |
408 | bl trace_hardirqs_off | |
409 | #endif | |
706fdd9f | 410 | get_thread_info tsk |
1da177e4 | 411 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
412 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count |
413 | add r7, r8, #1 @ increment it | |
414 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 415 | #endif |
ccea7a19 | 416 | |
187a51ad | 417 | irq_handler |
1da177e4 | 418 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
419 | ldr r0, [tsk, #TI_PREEMPT] |
420 | str r8, [tsk, #TI_PREEMPT] | |
1da177e4 | 421 | teq r0, r7 |
1da177e4 | 422 | strne r0, [r0, -r0] |
1da177e4 | 423 | #endif |
7ad1bcb2 RK |
424 | #ifdef CONFIG_TRACE_IRQFLAGS |
425 | bl trace_hardirqs_on | |
426 | #endif | |
ccea7a19 | 427 | |
1da177e4 LT |
428 | mov why, #0 |
429 | b ret_to_user | |
430 | ||
431 | .ltorg | |
432 | ||
433 | .align 5 | |
434 | __und_usr: | |
ccea7a19 | 435 | usr_entry |
1da177e4 LT |
436 | |
437 | tst r3, #PSR_T_BIT @ Thumb mode? | |
db6ccbb6 | 438 | bne __und_usr_unknown @ ignore FP |
1da177e4 LT |
439 | sub r4, r2, #4 |
440 | ||
441 | @ | |
442 | @ fall through to the emulation code, which returns using r9 if | |
443 | @ it has emulated the instruction, or the more conventional lr | |
444 | @ if we are to treat this as a real undefined instruction | |
445 | @ | |
446 | @ r0 - instruction | |
447 | @ | |
448 | 1: ldrt r0, [r4] | |
449 | adr r9, ret_from_exception | |
db6ccbb6 | 450 | adr lr, __und_usr_unknown |
1da177e4 LT |
451 | @ |
452 | @ fallthrough to call_fpe | |
453 | @ | |
454 | ||
455 | /* | |
456 | * The out of line fixup for the ldrt above. | |
457 | */ | |
458 | .section .fixup, "ax" | |
459 | 2: mov pc, r9 | |
460 | .previous | |
461 | .section __ex_table,"a" | |
462 | .long 1b, 2b | |
463 | .previous | |
464 | ||
465 | /* | |
466 | * Check whether the instruction is a co-processor instruction. | |
467 | * If yes, we need to call the relevant co-processor handler. | |
468 | * | |
469 | * Note that we don't do a full check here for the co-processor | |
470 | * instructions; all instructions with bit 27 set are well | |
471 | * defined. The only instructions that should fault are the | |
472 | * co-processor instructions. However, we have to watch out | |
473 | * for the ARM6/ARM7 SWI bug. | |
474 | * | |
475 | * Emulators may wish to make use of the following registers: | |
476 | * r0 = instruction opcode. | |
477 | * r2 = PC+4 | |
db6ccbb6 | 478 | * r9 = normal "successful" return address |
1da177e4 | 479 | * r10 = this threads thread_info structure. |
db6ccbb6 | 480 | * lr = unrecognised instruction return address |
1da177e4 LT |
481 | */ |
482 | call_fpe: | |
483 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 | |
484 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) | |
485 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
486 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
487 | #endif | |
488 | moveq pc, lr | |
489 | get_thread_info r10 @ get current thread | |
490 | and r8, r0, #0x00000f00 @ mask out CP number | |
491 | mov r7, #1 | |
492 | add r6, r10, #TI_USED_CP | |
493 | strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] | |
494 | #ifdef CONFIG_IWMMXT | |
495 | @ Test if we need to give access to iWMMXt coprocessors | |
496 | ldr r5, [r10, #TI_FLAGS] | |
497 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
498 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
499 | bcs iwmmxt_task_enable | |
500 | #endif | |
1da177e4 LT |
501 | add pc, pc, r8, lsr #6 |
502 | mov r0, r0 | |
503 | ||
504 | mov pc, lr @ CP#0 | |
505 | b do_fpe @ CP#1 (FPE) | |
506 | b do_fpe @ CP#2 (FPE) | |
507 | mov pc, lr @ CP#3 | |
c17fad11 LB |
508 | #ifdef CONFIG_CRUNCH |
509 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
510 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
511 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
512 | #else | |
1da177e4 LT |
513 | mov pc, lr @ CP#4 |
514 | mov pc, lr @ CP#5 | |
515 | mov pc, lr @ CP#6 | |
c17fad11 | 516 | #endif |
1da177e4 LT |
517 | mov pc, lr @ CP#7 |
518 | mov pc, lr @ CP#8 | |
519 | mov pc, lr @ CP#9 | |
520 | #ifdef CONFIG_VFP | |
521 | b do_vfp @ CP#10 (VFP) | |
522 | b do_vfp @ CP#11 (VFP) | |
523 | #else | |
524 | mov pc, lr @ CP#10 (VFP) | |
525 | mov pc, lr @ CP#11 (VFP) | |
526 | #endif | |
527 | mov pc, lr @ CP#12 | |
528 | mov pc, lr @ CP#13 | |
529 | mov pc, lr @ CP#14 (Debug) | |
530 | mov pc, lr @ CP#15 (Control) | |
531 | ||
532 | do_fpe: | |
5d25ac03 | 533 | enable_irq |
1da177e4 LT |
534 | ldr r4, .LCfp |
535 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
536 | ldr pc, [r4] @ Call FP module USR entry point | |
537 | ||
538 | /* | |
539 | * The FP module is called with these registers set: | |
540 | * r0 = instruction | |
541 | * r2 = PC+4 | |
542 | * r9 = normal "successful" return address | |
543 | * r10 = FP workspace | |
544 | * lr = unrecognised FP instruction return address | |
545 | */ | |
546 | ||
547 | .data | |
548 | ENTRY(fp_enter) | |
db6ccbb6 | 549 | .word no_fp |
1da177e4 LT |
550 | .text |
551 | ||
db6ccbb6 RK |
552 | no_fp: mov pc, lr |
553 | ||
554 | __und_usr_unknown: | |
1da177e4 LT |
555 | mov r0, sp |
556 | adr lr, ret_from_exception | |
557 | b do_undefinstr | |
558 | ||
559 | .align 5 | |
560 | __pabt_usr: | |
ccea7a19 | 561 | usr_entry |
1da177e4 | 562 | |
1ec42c0c | 563 | enable_irq @ Enable interrupts |
1da177e4 LT |
564 | mov r0, r2 @ address (pc) |
565 | mov r1, sp @ regs | |
566 | bl do_PrefetchAbort @ call abort handler | |
567 | /* fall through */ | |
568 | /* | |
569 | * This is the return code to user mode for abort handlers | |
570 | */ | |
571 | ENTRY(ret_from_exception) | |
572 | get_thread_info tsk | |
573 | mov why, #0 | |
574 | b ret_to_user | |
575 | ||
576 | /* | |
577 | * Register switch for ARMv3 and ARMv4 processors | |
578 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
579 | * previous and next are guaranteed not to be the same. | |
580 | */ | |
581 | ENTRY(__switch_to) | |
582 | add ip, r1, #TI_CPU_SAVE | |
583 | ldr r3, [r2, #TI_TP_VALUE] | |
584 | stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack | |
d6551e88 RK |
585 | #ifdef CONFIG_MMU |
586 | ldr r6, [r2, #TI_CPU_DOMAIN] | |
afeb90ca | 587 | #endif |
b876386e | 588 | #if __LINUX_ARM_ARCH__ >= 6 |
43cc1981 | 589 | #ifdef CONFIG_CPU_32v6K |
b876386e RK |
590 | clrex |
591 | #else | |
73394322 | 592 | strex r5, r4, [ip] @ Clear exclusive monitor |
b876386e RK |
593 | #endif |
594 | #endif | |
4b0e07a5 | 595 | #if defined(CONFIG_HAS_TLS_REG) |
2d2669b6 | 596 | mcr p15, 0, r3, c13, c0, 3 @ set TLS register |
4b0e07a5 | 597 | #elif !defined(CONFIG_TLS_REG_EMUL) |
1da177e4 | 598 | mov r4, #0xffff0fff |
2d2669b6 NP |
599 | str r3, [r4, #-15] @ TLS val at 0xffff0ff0 |
600 | #endif | |
afeb90ca | 601 | #ifdef CONFIG_MMU |
1da177e4 | 602 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 603 | #endif |
d6551e88 RK |
604 | mov r5, r0 |
605 | add r4, r2, #TI_CPU_SAVE | |
606 | ldr r0, =thread_notify_head | |
607 | mov r1, #THREAD_NOTIFY_SWITCH | |
608 | bl atomic_notifier_call_chain | |
609 | mov r0, r5 | |
610 | ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously | |
1da177e4 LT |
611 | |
612 | __INIT | |
2d2669b6 NP |
613 | |
614 | /* | |
615 | * User helpers. | |
616 | * | |
617 | * These are segment of kernel provided user code reachable from user space | |
618 | * at a fixed address in kernel memory. This is used to provide user space | |
619 | * with some operations which require kernel help because of unimplemented | |
620 | * native feature and/or instructions in many ARM CPUs. The idea is for | |
621 | * this code to be executed directly in user mode for best efficiency but | |
622 | * which is too intimate with the kernel counter part to be left to user | |
623 | * libraries. In fact this code might even differ from one CPU to another | |
624 | * depending on the available instruction set and restrictions like on | |
625 | * SMP systems. In other words, the kernel reserves the right to change | |
626 | * this code as needed without warning. Only the entry points and their | |
627 | * results are guaranteed to be stable. | |
628 | * | |
629 | * Each segment is 32-byte aligned and will be moved to the top of the high | |
630 | * vector page. New segments (if ever needed) must be added in front of | |
631 | * existing ones. This mechanism should be used only for things that are | |
632 | * really small and justified, and not be abused freely. | |
633 | * | |
634 | * User space is expected to implement those things inline when optimizing | |
635 | * for a processor that has the necessary native support, but only if such | |
636 | * resulting binaries are already to be incompatible with earlier ARM | |
637 | * processors due to the use of unsupported instructions other than what | |
638 | * is provided here. In other words don't make binaries unable to run on | |
639 | * earlier processors just for the sake of not using these kernel helpers | |
640 | * if your compiled code is not going to use the new instructions for other | |
641 | * purpose. | |
642 | */ | |
643 | ||
ba9b5d76 NP |
644 | .macro usr_ret, reg |
645 | #ifdef CONFIG_ARM_THUMB | |
646 | bx \reg | |
647 | #else | |
648 | mov pc, \reg | |
649 | #endif | |
650 | .endm | |
651 | ||
2d2669b6 NP |
652 | .align 5 |
653 | .globl __kuser_helper_start | |
654 | __kuser_helper_start: | |
655 | ||
7c612bfd NP |
656 | /* |
657 | * Reference prototype: | |
658 | * | |
659 | * void __kernel_memory_barrier(void) | |
660 | * | |
661 | * Input: | |
662 | * | |
663 | * lr = return address | |
664 | * | |
665 | * Output: | |
666 | * | |
667 | * none | |
668 | * | |
669 | * Clobbered: | |
670 | * | |
671 | * the Z flag might be lost | |
672 | * | |
673 | * Definition and user space usage example: | |
674 | * | |
675 | * typedef void (__kernel_dmb_t)(void); | |
676 | * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) | |
677 | * | |
678 | * Apply any needed memory barrier to preserve consistency with data modified | |
679 | * manually and __kuser_cmpxchg usage. | |
680 | * | |
681 | * This could be used as follows: | |
682 | * | |
683 | * #define __kernel_dmb() \ | |
684 | * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ | |
6896eec0 | 685 | * : : : "r0", "lr","cc" ) |
7c612bfd NP |
686 | */ |
687 | ||
688 | __kuser_memory_barrier: @ 0xffff0fa0 | |
689 | ||
690 | #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) | |
691 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
692 | #endif | |
ba9b5d76 | 693 | usr_ret lr |
7c612bfd NP |
694 | |
695 | .align 5 | |
696 | ||
2d2669b6 NP |
697 | /* |
698 | * Reference prototype: | |
699 | * | |
700 | * int __kernel_cmpxchg(int oldval, int newval, int *ptr) | |
701 | * | |
702 | * Input: | |
703 | * | |
704 | * r0 = oldval | |
705 | * r1 = newval | |
706 | * r2 = ptr | |
707 | * lr = return address | |
708 | * | |
709 | * Output: | |
710 | * | |
711 | * r0 = returned value (zero or non-zero) | |
712 | * C flag = set if r0 == 0, clear if r0 != 0 | |
713 | * | |
714 | * Clobbered: | |
715 | * | |
716 | * r3, ip, flags | |
717 | * | |
718 | * Definition and user space usage example: | |
719 | * | |
720 | * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); | |
721 | * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) | |
722 | * | |
723 | * Atomically store newval in *ptr if *ptr is equal to oldval for user space. | |
724 | * Return zero if *ptr was changed or non-zero if no exchange happened. | |
725 | * The C flag is also set if *ptr was changed to allow for assembly | |
726 | * optimization in the calling code. | |
727 | * | |
5964eae8 NP |
728 | * Notes: |
729 | * | |
730 | * - This routine already includes memory barriers as needed. | |
731 | * | |
732 | * - A failure might be transient, i.e. it is possible, although unlikely, | |
733 | * that "failure" be returned even if *ptr == oldval. | |
7c612bfd | 734 | * |
2d2669b6 NP |
735 | * For example, a user space atomic_add implementation could look like this: |
736 | * | |
737 | * #define atomic_add(ptr, val) \ | |
738 | * ({ register unsigned int *__ptr asm("r2") = (ptr); \ | |
739 | * register unsigned int __result asm("r1"); \ | |
740 | * asm volatile ( \ | |
741 | * "1: @ atomic_add\n\t" \ | |
742 | * "ldr r0, [r2]\n\t" \ | |
743 | * "mov r3, #0xffff0fff\n\t" \ | |
744 | * "add lr, pc, #4\n\t" \ | |
745 | * "add r1, r0, %2\n\t" \ | |
746 | * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ | |
747 | * "bcc 1b" \ | |
748 | * : "=&r" (__result) \ | |
749 | * : "r" (__ptr), "rIL" (val) \ | |
750 | * : "r0","r3","ip","lr","cc","memory" ); \ | |
751 | * __result; }) | |
752 | */ | |
753 | ||
754 | __kuser_cmpxchg: @ 0xffff0fc0 | |
755 | ||
dcef1f63 | 756 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 757 | |
dcef1f63 NP |
758 | /* |
759 | * Poor you. No fast solution possible... | |
760 | * The kernel itself must perform the operation. | |
761 | * A special ghost syscall is used for that (see traps.c). | |
762 | */ | |
5e097445 NP |
763 | stmfd sp!, {r7, lr} |
764 | mov r7, #0xff00 @ 0xfff0 into r7 for EABI | |
765 | orr r7, r7, #0xf0 | |
dcef1f63 | 766 | swi #0x9ffff0 |
5e097445 | 767 | ldmfd sp!, {r7, pc} |
dcef1f63 NP |
768 | |
769 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 NP |
770 | |
771 | /* | |
772 | * Theory of operation: | |
773 | * | |
774 | * We set the Z flag before loading oldval. If ever an exception | |
775 | * occurs we can not be sure the loaded value will still be the same | |
776 | * when the exception returns, therefore the user exception handler | |
777 | * will clear the Z flag whenever the interrupted user code was | |
778 | * actually from the kernel address space (see the usr_entry macro). | |
779 | * | |
780 | * The post-increment on the str is used to prevent a race with an | |
781 | * exception happening just after the str instruction which would | |
782 | * clear the Z flag although the exchange was done. | |
783 | */ | |
49bca4c2 | 784 | #ifdef CONFIG_MMU |
2d2669b6 NP |
785 | teq ip, ip @ set Z flag |
786 | ldr ip, [r2] @ load current val | |
787 | add r3, r2, #1 @ prepare store ptr | |
788 | teqeq ip, r0 @ compare with oldval if still allowed | |
789 | streq r1, [r3, #-1]! @ store newval if still allowed | |
790 | subs r0, r2, r3 @ if r2 == r3 the str occured | |
49bca4c2 NP |
791 | #else |
792 | #warning "NPTL on non MMU needs fixing" | |
793 | mov r0, #-1 | |
794 | adds r0, r0, #0 | |
795 | #endif | |
ba9b5d76 | 796 | usr_ret lr |
2d2669b6 NP |
797 | |
798 | #else | |
799 | ||
7c612bfd NP |
800 | #ifdef CONFIG_SMP |
801 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
802 | #endif | |
2d2669b6 NP |
803 | ldrex r3, [r2] |
804 | subs r3, r3, r0 | |
805 | strexeq r3, r1, [r2] | |
806 | rsbs r0, r3, #0 | |
7c612bfd NP |
807 | #ifdef CONFIG_SMP |
808 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
809 | #endif | |
ba9b5d76 | 810 | usr_ret lr |
2d2669b6 NP |
811 | |
812 | #endif | |
813 | ||
814 | .align 5 | |
815 | ||
816 | /* | |
817 | * Reference prototype: | |
818 | * | |
819 | * int __kernel_get_tls(void) | |
820 | * | |
821 | * Input: | |
822 | * | |
823 | * lr = return address | |
824 | * | |
825 | * Output: | |
826 | * | |
827 | * r0 = TLS value | |
828 | * | |
829 | * Clobbered: | |
830 | * | |
831 | * the Z flag might be lost | |
832 | * | |
833 | * Definition and user space usage example: | |
834 | * | |
835 | * typedef int (__kernel_get_tls_t)(void); | |
836 | * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) | |
837 | * | |
838 | * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. | |
839 | * | |
840 | * This could be used as follows: | |
841 | * | |
842 | * #define __kernel_get_tls() \ | |
843 | * ({ register unsigned int __val asm("r0"); \ | |
844 | * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ | |
845 | * : "=r" (__val) : : "lr","cc" ); \ | |
846 | * __val; }) | |
847 | */ | |
848 | ||
849 | __kuser_get_tls: @ 0xffff0fe0 | |
850 | ||
4b0e07a5 | 851 | #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) |
2d2669b6 | 852 | ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 |
2d2669b6 | 853 | #else |
2d2669b6 | 854 | mrc p15, 0, r0, c13, c0, 3 @ read TLS register |
2d2669b6 | 855 | #endif |
ba9b5d76 | 856 | usr_ret lr |
2d2669b6 NP |
857 | |
858 | .rep 5 | |
859 | .word 0 @ pad up to __kuser_helper_version | |
860 | .endr | |
861 | ||
862 | /* | |
863 | * Reference declaration: | |
864 | * | |
865 | * extern unsigned int __kernel_helper_version; | |
866 | * | |
867 | * Definition and user space usage example: | |
868 | * | |
869 | * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) | |
870 | * | |
871 | * User space may read this to determine the curent number of helpers | |
872 | * available. | |
873 | */ | |
874 | ||
875 | __kuser_helper_version: @ 0xffff0ffc | |
876 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
877 | ||
878 | .globl __kuser_helper_end | |
879 | __kuser_helper_end: | |
880 | ||
881 | ||
1da177e4 LT |
882 | /* |
883 | * Vector stubs. | |
884 | * | |
7933523d RK |
885 | * This code is copied to 0xffff0200 so we can use branches in the |
886 | * vectors, rather than ldr's. Note that this code must not | |
887 | * exceed 0x300 bytes. | |
1da177e4 LT |
888 | * |
889 | * Common stub entry macro: | |
890 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
891 | * |
892 | * SP points to a minimal amount of processor-private memory, the address | |
893 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 894 | */ |
b7ec4795 | 895 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
896 | .align 5 |
897 | ||
898 | vector_\name: | |
1da177e4 LT |
899 | .if \correction |
900 | sub lr, lr, #\correction | |
901 | .endif | |
ccea7a19 RK |
902 | |
903 | @ | |
904 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
905 | @ (parent CPSR) | |
906 | @ | |
907 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 908 | mrs lr, spsr |
ccea7a19 RK |
909 | str lr, [sp, #8] @ save spsr |
910 | ||
1da177e4 | 911 | @ |
ccea7a19 | 912 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 913 | @ |
ccea7a19 | 914 | mrs r0, cpsr |
b7ec4795 | 915 | eor r0, r0, #(\mode ^ SVC_MODE) |
ccea7a19 | 916 | msr spsr_cxsf, r0 |
1da177e4 | 917 | |
ccea7a19 RK |
918 | @ |
919 | @ the branch table must immediately follow this code | |
920 | @ | |
ccea7a19 | 921 | and lr, lr, #0x0f |
b7ec4795 | 922 | mov r0, sp |
1da177e4 | 923 | ldr lr, [pc, lr, lsl #2] |
ccea7a19 | 924 | movs pc, lr @ branch to handler in SVC mode |
1da177e4 LT |
925 | .endm |
926 | ||
7933523d | 927 | .globl __stubs_start |
1da177e4 LT |
928 | __stubs_start: |
929 | /* | |
930 | * Interrupt dispatcher | |
931 | */ | |
b7ec4795 | 932 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
933 | |
934 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
935 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
936 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
937 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
938 | .long __irq_invalid @ 4 | |
939 | .long __irq_invalid @ 5 | |
940 | .long __irq_invalid @ 6 | |
941 | .long __irq_invalid @ 7 | |
942 | .long __irq_invalid @ 8 | |
943 | .long __irq_invalid @ 9 | |
944 | .long __irq_invalid @ a | |
945 | .long __irq_invalid @ b | |
946 | .long __irq_invalid @ c | |
947 | .long __irq_invalid @ d | |
948 | .long __irq_invalid @ e | |
949 | .long __irq_invalid @ f | |
950 | ||
951 | /* | |
952 | * Data abort dispatcher | |
953 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
954 | */ | |
b7ec4795 | 955 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
956 | |
957 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
958 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
959 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
960 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
961 | .long __dabt_invalid @ 4 | |
962 | .long __dabt_invalid @ 5 | |
963 | .long __dabt_invalid @ 6 | |
964 | .long __dabt_invalid @ 7 | |
965 | .long __dabt_invalid @ 8 | |
966 | .long __dabt_invalid @ 9 | |
967 | .long __dabt_invalid @ a | |
968 | .long __dabt_invalid @ b | |
969 | .long __dabt_invalid @ c | |
970 | .long __dabt_invalid @ d | |
971 | .long __dabt_invalid @ e | |
972 | .long __dabt_invalid @ f | |
973 | ||
974 | /* | |
975 | * Prefetch abort dispatcher | |
976 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
977 | */ | |
b7ec4795 | 978 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
979 | |
980 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
981 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
982 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
983 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
984 | .long __pabt_invalid @ 4 | |
985 | .long __pabt_invalid @ 5 | |
986 | .long __pabt_invalid @ 6 | |
987 | .long __pabt_invalid @ 7 | |
988 | .long __pabt_invalid @ 8 | |
989 | .long __pabt_invalid @ 9 | |
990 | .long __pabt_invalid @ a | |
991 | .long __pabt_invalid @ b | |
992 | .long __pabt_invalid @ c | |
993 | .long __pabt_invalid @ d | |
994 | .long __pabt_invalid @ e | |
995 | .long __pabt_invalid @ f | |
996 | ||
997 | /* | |
998 | * Undef instr entry dispatcher | |
999 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1000 | */ | |
b7ec4795 | 1001 | vector_stub und, UND_MODE |
1da177e4 LT |
1002 | |
1003 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1004 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1005 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1006 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1007 | .long __und_invalid @ 4 | |
1008 | .long __und_invalid @ 5 | |
1009 | .long __und_invalid @ 6 | |
1010 | .long __und_invalid @ 7 | |
1011 | .long __und_invalid @ 8 | |
1012 | .long __und_invalid @ 9 | |
1013 | .long __und_invalid @ a | |
1014 | .long __und_invalid @ b | |
1015 | .long __und_invalid @ c | |
1016 | .long __und_invalid @ d | |
1017 | .long __und_invalid @ e | |
1018 | .long __und_invalid @ f | |
1019 | ||
1020 | .align 5 | |
1021 | ||
1022 | /*============================================================================= | |
1023 | * Undefined FIQs | |
1024 | *----------------------------------------------------------------------------- | |
1025 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
1026 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
1027 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
1028 | * damage alert! I don't think that we can execute any code in here in any | |
1029 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
1030 | * get out of that mode without clobbering one register. | |
1031 | */ | |
1032 | vector_fiq: | |
1033 | disable_fiq | |
1034 | subs pc, lr, #4 | |
1035 | ||
1036 | /*============================================================================= | |
1037 | * Address exception handler | |
1038 | *----------------------------------------------------------------------------- | |
1039 | * These aren't too critical. | |
1040 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1041 | */ | |
1042 | ||
1043 | vector_addrexcptn: | |
1044 | b vector_addrexcptn | |
1045 | ||
1046 | /* | |
1047 | * We group all the following data together to optimise | |
1048 | * for CPUs with separate I & D caches. | |
1049 | */ | |
1050 | .align 5 | |
1051 | ||
1052 | .LCvswi: | |
1053 | .word vector_swi | |
1054 | ||
7933523d | 1055 | .globl __stubs_end |
1da177e4 LT |
1056 | __stubs_end: |
1057 | ||
7933523d | 1058 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1059 | |
7933523d RK |
1060 | .globl __vectors_start |
1061 | __vectors_start: | |
1da177e4 | 1062 | swi SYS_ERROR0 |
7933523d RK |
1063 | b vector_und + stubs_offset |
1064 | ldr pc, .LCvswi + stubs_offset | |
1065 | b vector_pabt + stubs_offset | |
1066 | b vector_dabt + stubs_offset | |
1067 | b vector_addrexcptn + stubs_offset | |
1068 | b vector_irq + stubs_offset | |
1069 | b vector_fiq + stubs_offset | |
1070 | ||
1071 | .globl __vectors_end | |
1072 | __vectors_end: | |
1da177e4 LT |
1073 | |
1074 | .data | |
1075 | ||
1da177e4 LT |
1076 | .globl cr_alignment |
1077 | .globl cr_no_alignment | |
1078 | cr_alignment: | |
1079 | .space 4 | |
1080 | cr_no_alignment: | |
1081 | .space 4 |