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Merge with git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
[linux-2.6-block.git] / arch / arm / kernel / bios32.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/arm/kernel/bios32.c
3 *
4 * PCI bios-type initialisation for PCI machines
5 *
6 * Bits taken from various places.
7 */
8#include <linux/config.h>
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/init.h>
14
15#include <asm/io.h>
16#include <asm/mach-types.h>
17#include <asm/mach/pci.h>
18
19static int debug_pci;
20static int use_firmware;
21
22/*
23 * We can't use pci_find_device() here since we are
24 * called from interrupt context.
25 */
26static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
27{
28 struct pci_dev *dev;
29
30 list_for_each_entry(dev, &bus->devices, bus_list) {
31 u16 status;
32
33 /*
34 * ignore host bridge - we handle
35 * that separately
36 */
37 if (dev->bus->number == 0 && dev->devfn == 0)
38 continue;
39
40 pci_read_config_word(dev, PCI_STATUS, &status);
41 if (status == 0xffff)
42 continue;
43
44 if ((status & status_mask) == 0)
45 continue;
46
47 /* clear the status errors */
48 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
49
50 if (warn)
51 printk("(%s: %04X) ", pci_name(dev), status);
52 }
53
54 list_for_each_entry(dev, &bus->devices, bus_list)
55 if (dev->subordinate)
56 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
57}
58
59void pcibios_report_status(u_int status_mask, int warn)
60{
61 struct list_head *l;
62
63 list_for_each(l, &pci_root_buses) {
64 struct pci_bus *bus = pci_bus_b(l);
65
66 pcibios_bus_report_status(bus, status_mask, warn);
67 }
68}
69
70/*
71 * We don't use this to fix the device, but initialisation of it.
72 * It's not the correct use for this, but it works.
73 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
74 * the following area:
75 * 1. park on CPU
76 * 2. ISA bridge ping-pong
77 * 3. ISA bridge master handling of target RETRY
78 *
79 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
80 * live with bug 2.
81 */
82static void __devinit pci_fixup_83c553(struct pci_dev *dev)
83{
84 /*
85 * Set memory region to start at address 0, and enable IO
86 */
87 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
88 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
89
90 dev->resource[0].end -= dev->resource[0].start;
91 dev->resource[0].start = 0;
92
93 /*
94 * All memory requests from ISA to be channelled to PCI
95 */
96 pci_write_config_byte(dev, 0x48, 0xff);
97
98 /*
99 * Enable ping-pong on bus master to ISA bridge transactions.
100 * This improves the sound DMA substantially. The fixed
101 * priority arbiter also helps (see below).
102 */
103 pci_write_config_byte(dev, 0x42, 0x01);
104
105 /*
106 * Enable PCI retry
107 */
108 pci_write_config_byte(dev, 0x40, 0x22);
109
110 /*
111 * We used to set the arbiter to "park on last master" (bit
112 * 1 set), but unfortunately the CyberPro does not park the
113 * bus. We must therefore park on CPU. Unfortunately, this
114 * may trigger yet another bug in the 553.
115 */
116 pci_write_config_byte(dev, 0x83, 0x02);
117
118 /*
119 * Make the ISA DMA request lowest priority, and disable
120 * rotating priorities completely.
121 */
122 pci_write_config_byte(dev, 0x80, 0x11);
123 pci_write_config_byte(dev, 0x81, 0x00);
124
125 /*
126 * Route INTA input to IRQ 11, and set IRQ11 to be level
127 * sensitive.
128 */
129 pci_write_config_word(dev, 0x44, 0xb000);
130 outb(0x08, 0x4d1);
131}
132DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
133
134static void __devinit pci_fixup_unassign(struct pci_dev *dev)
135{
136 dev->resource[0].end -= dev->resource[0].start;
137 dev->resource[0].start = 0;
138}
139DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
140
141/*
142 * Prevent the PCI layer from seeing the resources allocated to this device
143 * if it is the host bridge by marking it as such. These resources are of
144 * no consequence to the PCI layer (they are handled elsewhere).
145 */
146static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
147{
148 int i;
149
150 if (dev->devfn == 0) {
151 dev->class &= 0xff;
152 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
153 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
154 dev->resource[i].start = 0;
155 dev->resource[i].end = 0;
156 dev->resource[i].flags = 0;
157 }
158 }
159}
160DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
161
162/*
163 * Same as above. The PrPMC800 carrier board for the PrPMC1100
164 * card maps the host-bridge @ 00:01:00 for some reason and it
165 * ends up getting scanned. Note that we only want to do this
166 * fixup when we find the IXP4xx on a PrPMC system, which is why
167 * we check the machine type. We could be running on a board
168 * with an IXP4xx target device and we don't want to kill the
169 * resources in that case.
170 */
171static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev)
172{
173 int i;
174
175 if (machine_is_prpmc1100()) {
176 dev->class &= 0xff;
177 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
178 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
179 dev->resource[i].start = 0;
180 dev->resource[i].end = 0;
181 dev->resource[i].flags = 0;
182 }
183 }
184}
185DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100);
186
187/*
188 * PCI IDE controllers use non-standard I/O port decoding, respect it.
189 */
190static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
191{
192 struct resource *r;
193 int i;
194
195 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
196 return;
197
198 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
199 r = dev->resource + i;
200 if ((r->start & ~0x80) == 0x374) {
201 r->start |= 2;
202 r->end = r->start;
203 }
204 }
205}
206DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
207
208/*
209 * Put the DEC21142 to sleep
210 */
211static void __devinit pci_fixup_dec21142(struct pci_dev *dev)
212{
213 pci_write_config_dword(dev, 0x40, 0x80000000);
214}
215DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
216
217/*
218 * The CY82C693 needs some rather major fixups to ensure that it does
219 * the right thing. Idea from the Alpha people, with a few additions.
220 *
221 * We ensure that the IDE base registers are set to 1f0/3f4 for the
222 * primary bus, and 170/374 for the secondary bus. Also, hide them
223 * from the PCI subsystem view as well so we won't try to perform
224 * our own auto-configuration on them.
225 *
226 * In addition, we ensure that the PCI IDE interrupts are routed to
227 * IRQ 14 and IRQ 15 respectively.
228 *
229 * The above gets us to a point where the IDE on this device is
230 * functional. However, The CY82C693U _does not work_ in bus
231 * master mode without locking the PCI bus solid.
232 */
233static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
234{
235 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
236 u32 base0, base1;
237
238 if (dev->class & 0x80) { /* primary */
239 base0 = 0x1f0;
240 base1 = 0x3f4;
241 } else { /* secondary */
242 base0 = 0x170;
243 base1 = 0x374;
244 }
245
246 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
247 base0 | PCI_BASE_ADDRESS_SPACE_IO);
248 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
249 base1 | PCI_BASE_ADDRESS_SPACE_IO);
250
251 dev->resource[0].start = 0;
252 dev->resource[0].end = 0;
253 dev->resource[0].flags = 0;
254
255 dev->resource[1].start = 0;
256 dev->resource[1].end = 0;
257 dev->resource[1].flags = 0;
258 } else if (PCI_FUNC(dev->devfn) == 0) {
259 /*
260 * Setup IDE IRQ routing.
261 */
262 pci_write_config_byte(dev, 0x4b, 14);
263 pci_write_config_byte(dev, 0x4c, 15);
264
265 /*
266 * Disable FREQACK handshake, enable USB.
267 */
268 pci_write_config_byte(dev, 0x4d, 0x41);
269
270 /*
271 * Enable PCI retry, and PCI post-write buffer.
272 */
273 pci_write_config_byte(dev, 0x44, 0x17);
274
275 /*
276 * Enable ISA master and DMA post write buffering.
277 */
278 pci_write_config_byte(dev, 0x45, 0x03);
279 }
280}
281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
282
283void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
284{
285 if (debug_pci)
286 printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev));
287 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
288}
289
290/*
291 * If the bus contains any of these devices, then we must not turn on
292 * parity checking of any kind. Currently this is CyberPro 20x0 only.
293 */
294static inline int pdev_bad_for_parity(struct pci_dev *dev)
295{
296 return (dev->vendor == PCI_VENDOR_ID_INTERG &&
297 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
298 dev->device == PCI_DEVICE_ID_INTERG_2010));
299}
300
301/*
302 * Adjust the device resources from bus-centric to Linux-centric.
303 */
304static void __devinit
305pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev)
306{
307 unsigned long offset;
308 int i;
309
310 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
311 if (dev->resource[i].start == 0)
312 continue;
313 if (dev->resource[i].flags & IORESOURCE_MEM)
314 offset = root->mem_offset;
315 else
316 offset = root->io_offset;
317
318 dev->resource[i].start += offset;
319 dev->resource[i].end += offset;
320 }
321}
322
323static void __devinit
324pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root)
325{
326 struct pci_dev *dev = bus->self;
327 int i;
328
329 if (!dev) {
330 /*
331 * Assign root bus resources.
332 */
333 for (i = 0; i < 3; i++)
334 bus->resource[i] = root->resource[i];
335 }
336}
337
338/*
339 * pcibios_fixup_bus - Called after each bus is probed,
340 * but before its children are examined.
341 */
342void __devinit pcibios_fixup_bus(struct pci_bus *bus)
343{
344 struct pci_sys_data *root = bus->sysdata;
345 struct pci_dev *dev;
346 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
347
348 pbus_assign_bus_resources(bus, root);
349
350 /*
351 * Walk the devices on this bus, working out what we can
352 * and can't support.
353 */
354 list_for_each_entry(dev, &bus->devices, bus_list) {
355 u16 status;
356
357 pdev_fixup_device_resources(root, dev);
358
359 pci_read_config_word(dev, PCI_STATUS, &status);
360
361 /*
362 * If any device on this bus does not support fast back
363 * to back transfers, then the bus as a whole is not able
364 * to support them. Having fast back to back transfers
365 * on saves us one PCI cycle per transaction.
366 */
367 if (!(status & PCI_STATUS_FAST_BACK))
368 features &= ~PCI_COMMAND_FAST_BACK;
369
370 if (pdev_bad_for_parity(dev))
371 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
372
373 switch (dev->class >> 8) {
374#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
375 case PCI_CLASS_BRIDGE_ISA:
376 case PCI_CLASS_BRIDGE_EISA:
377 /*
378 * If this device is an ISA bridge, set isa_bridge
379 * to point at this device. We will then go looking
380 * for things like keyboard, etc.
381 */
382 isa_bridge = dev;
383 break;
384#endif
385 case PCI_CLASS_BRIDGE_PCI:
386 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
387 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
388 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
389 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
390 break;
391
392 case PCI_CLASS_BRIDGE_CARDBUS:
393 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
394 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
395 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
396 break;
397 }
398 }
399
400 /*
401 * Now walk the devices again, this time setting them up.
402 */
403 list_for_each_entry(dev, &bus->devices, bus_list) {
404 u16 cmd;
405
406 pci_read_config_word(dev, PCI_COMMAND, &cmd);
407 cmd |= features;
408 pci_write_config_word(dev, PCI_COMMAND, cmd);
409
410 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
411 L1_CACHE_BYTES >> 2);
412 }
413
414 /*
415 * Propagate the flags to the PCI bridge.
416 */
417 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
418 if (features & PCI_COMMAND_FAST_BACK)
419 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
420 if (features & PCI_COMMAND_PARITY)
421 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
422 }
423
424 /*
425 * Report what we did for this bus
426 */
427 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
428 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
429}
430
431/*
432 * Convert from Linux-centric to bus-centric addresses for bridge devices.
433 */
434void __devinit
435pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
436 struct resource *res)
437{
438 struct pci_sys_data *root = dev->sysdata;
439 unsigned long offset = 0;
440
441 if (res->flags & IORESOURCE_IO)
442 offset = root->io_offset;
443 if (res->flags & IORESOURCE_MEM)
444 offset = root->mem_offset;
445
446 region->start = res->start - offset;
447 region->end = res->end - offset;
448}
449
43c34735
DB		 450void __devinit
451pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
452 struct pci_bus_region *region)
453{
454 struct pci_sys_data *root = dev->sysdata;
455 unsigned long offset = 0;
456
457 if (res->flags & IORESOURCE_IO)
458 offset = root->io_offset;
459 if (res->flags & IORESOURCE_MEM)
460 offset = root->mem_offset;
461
462 res->start = region->start + offset;
463 res->end = region->end + offset;
464}
465
1da177e4
LT		 466#ifdef CONFIG_HOTPLUG
467EXPORT_SYMBOL(pcibios_fixup_bus);
468EXPORT_SYMBOL(pcibios_resource_to_bus);
43c34735 469EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4
LT		 470#endif
471
472/*
473 * This is the standard PCI-PCI bridge swizzling algorithm:
474 *
475 * Dev: 0 1 2 3
476 * A A B C D
477 * B B C D A
478 * C C D A B
479 * D D A B C
480 * ^^^^^^^^^^ irq pin on bridge
481 */
482u8 __devinit pci_std_swizzle(struct pci_dev *dev, u8 *pinp)
483{
484 int pin = *pinp - 1;
485
486 while (dev->bus->self) {
487 pin = (pin + PCI_SLOT(dev->devfn)) & 3;
488 /*
489 * move up the chain of bridges,
490 * swizzling as we go.
491 */
492 dev = dev->bus->self;
493 }
494 *pinp = pin + 1;
495
496 return PCI_SLOT(dev->devfn);
497}
498
499/*
500 * Swizzle the device pin each time we cross a bridge.
501 * This might update pin and returns the slot number.
502 */
503static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
504{
505 struct pci_sys_data *sys = dev->sysdata;
506 int slot = 0, oldpin = *pin;
507
508 if (sys->swizzle)
509 slot = sys->swizzle(dev, pin);
510
511 if (debug_pci)
512 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
513 pci_name(dev), oldpin, *pin, slot);
514
515 return slot;
516}
517
518/*
519 * Map a slot/pin to an IRQ.
520 */
521static int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
522{
523 struct pci_sys_data *sys = dev->sysdata;
524 int irq = -1;
525
526 if (sys->map_irq)
527 irq = sys->map_irq(dev, slot, pin);
528
529 if (debug_pci)
530 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
531 pci_name(dev), slot, pin, irq);
532
533 return irq;
534}
535
536static void __init pcibios_init_hw(struct hw_pci *hw)
537{
538 struct pci_sys_data *sys = NULL;
539 int ret;
540 int nr, busnr;
541
542 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
d2a02b93 543 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
1da177e4
LT		 544 if (!sys)
545 panic("PCI: unable to allocate sys data!");
546
1da177e4
LT		 547 sys->hw = hw;
548 sys->busnr = busnr;
549 sys->swizzle = hw->swizzle;
550 sys->map_irq = hw->map_irq;
551 sys->resource[0] = &ioport_resource;
552 sys->resource[1] = &iomem_resource;
553
554 ret = hw->setup(nr, sys);
555
556 if (ret > 0) {
557 sys->bus = hw->scan(nr, sys);
558
559 if (!sys->bus)
560 panic("PCI: unable to scan bus!");
561
562 busnr = sys->bus->subordinate + 1;
563
564 list_add(&sys->node, &hw->buses);
565 } else {
566 kfree(sys);
567 if (ret < 0)
568 break;
569 }
570 }
571}
572
573void __init pci_common_init(struct hw_pci *hw)
574{
575 struct pci_sys_data *sys;
576
577 INIT_LIST_HEAD(&hw->buses);
578
579 if (hw->preinit)
580 hw->preinit();
581 pcibios_init_hw(hw);
582 if (hw->postinit)
583 hw->postinit();
584
585 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
586
587 list_for_each_entry(sys, &hw->buses, node) {
588 struct pci_bus *bus = sys->bus;
589
590 if (!use_firmware) {
591 /*
592 * Size the bridge windows.
593 */
594 pci_bus_size_bridges(bus);
595
596 /*
597 * Assign resources.
598 */
599 pci_bus_assign_resources(bus);
600 }
601
602 /*
603 * Tell drivers about devices found.
604 */
605 pci_bus_add_devices(bus);
606 }
607}
608
609char * __init pcibios_setup(char *str)
610{
611 if (!strcmp(str, "debug")) {
612 debug_pci = 1;
613 return NULL;
614 } else if (!strcmp(str, "firmware")) {
615 use_firmware = 1;
616 return NULL;
617 }
618 return str;
619}
620
621/*
622 * From arch/i386/kernel/pci-i386.c:
623 *
624 * We need to avoid collisions with `mirrored' VGA ports
625 * and other strange ISA hardware, so we always want the
626 * addresses to be allocated in the 0x000-0x0ff region
627 * modulo 0x400.
628 *
629 * Why? Because some silly external IO cards only decode
630 * the low 10 bits of the IO address. The 0x00-0xff region
631 * is reserved for motherboard devices that decode all 16
632 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
633 * but we want to try to avoid allocating at 0x2900-0x2bff
634 * which might be mirrored at 0x0100-0x03ff..
635 */
636void pcibios_align_resource(void *data, struct resource *res,
637 unsigned long size, unsigned long align)
638{
639 unsigned long start = res->start;
640
641 if (res->flags & IORESOURCE_IO && start & 0x300)
642 start = (start + 0x3ff) & ~0x3ff;
643
644 res->start = (start + align - 1) & ~(align - 1);
645}
646
647/**
648 * pcibios_enable_device - Enable I/O and memory.
649 * @dev: PCI device to be enabled
650 */
651int pcibios_enable_device(struct pci_dev *dev, int mask)
652{
653 u16 cmd, old_cmd;
654 int idx;
655 struct resource *r;
656
657 pci_read_config_word(dev, PCI_COMMAND, &cmd);
658 old_cmd = cmd;
659 for (idx = 0; idx < 6; idx++) {
660 /* Only set up the requested stuff */
661 if (!(mask & (1 << idx)))
662 continue;
663
664 r = dev->resource + idx;
665 if (!r->start && r->end) {
666 printk(KERN_ERR "PCI: Device %s not available because"
667 " of resource collisions\n", pci_name(dev));
668 return -EINVAL;
669 }
670 if (r->flags & IORESOURCE_IO)
671 cmd |= PCI_COMMAND_IO;
672 if (r->flags & IORESOURCE_MEM)
673 cmd |= PCI_COMMAND_MEMORY;
674 }
675
676 /*
677 * Bridges (eg, cardbus bridges) need to be fully enabled
678 */
679 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
680 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
681
682 if (cmd != old_cmd) {
683 printk("PCI: enabling device %s (%04x -> %04x)\n",
684 pci_name(dev), old_cmd, cmd);
685 pci_write_config_word(dev, PCI_COMMAND, cmd);
686 }
687 return 0;
688}
689
690int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
691 enum pci_mmap_state mmap_state, int write_combine)
692{
693 struct pci_sys_data *root = dev->sysdata;
694 unsigned long phys;
695
696 if (mmap_state == pci_mmap_io) {
697 return -EINVAL;
698 } else {
699 phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
700 }
701
702 /*
703 * Mark this as IO
704 */
705 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
706 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
707
708 if (remap_pfn_range(vma, vma->vm_start, phys,
709 vma->vm_end - vma->vm_start,
710 vma->vm_page_prot))
711 return -EAGAIN;
712
713 return 0;
714}
Linux 6.x block layer and io_uring tree(s)