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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 1995-2003 Russell King | |
3 | * 2001-2002 Keith Owens | |
4 | * | |
5 | * Generate definitions needed by assembly language modules. | |
6 | * This code generates raw asm output which is post-processed to extract | |
7 | * and format the required data. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/sched.h> | |
14 | #include <linux/mm.h> | |
a9c9147e | 15 | #include <linux/dma-mapping.h> |
f6b0fa02 | 16 | #include <asm/cacheflush.h> |
753790e7 RK |
17 | #include <asm/glue-df.h> |
18 | #include <asm/glue-pf.h> | |
1da177e4 LT |
19 | #include <asm/mach/arch.h> |
20 | #include <asm/thread_info.h> | |
21 | #include <asm/memory.h> | |
ee90dabc | 22 | #include <asm/procinfo.h> |
91c2ebb9 | 23 | #include <asm/hardware/cache-l2x0.h> |
02cbe474 | 24 | #include <linux/kbuild.h> |
1da177e4 LT |
25 | |
26 | /* | |
27 | * Make sure that the compiler and target are compatible. | |
28 | */ | |
29 | #if defined(__APCS_26__) | |
30 | #error Sorry, your compiler targets APCS-26 but this kernel requires APCS-32 | |
31 | #endif | |
32 | /* | |
1da177e4 LT |
33 | * GCC 3.0, 3.1: general bad code generation. |
34 | * GCC 3.2.0: incorrect function argument offset calculation. | |
35 | * GCC 3.2.x: miscompiles NEW_AUX_ENT in fs/binfmt_elf.c | |
36 | * (http://gcc.gnu.org/PR8896) and incorrect structure | |
37 | * initialisation in fs/jffs2/erase.c | |
38 | */ | |
a1365647 | 39 | #if (__GNUC__ == 3 && __GNUC_MINOR__ < 3) |
1da177e4 | 40 | #error Your compiler is too buggy; it is known to miscompile kernels. |
a1365647 | 41 | #error Known good compilers: 3.3 |
1da177e4 LT |
42 | #endif |
43 | ||
1da177e4 LT |
44 | int main(void) |
45 | { | |
46 | DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); | |
df0698be NP |
47 | #ifdef CONFIG_CC_STACKPROTECTOR |
48 | DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary)); | |
49 | #endif | |
1da177e4 LT |
50 | BLANK(); |
51 | DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); | |
52 | DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); | |
53 | DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit)); | |
54 | DEFINE(TI_TASK, offsetof(struct thread_info, task)); | |
55 | DEFINE(TI_EXEC_DOMAIN, offsetof(struct thread_info, exec_domain)); | |
56 | DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); | |
57 | DEFINE(TI_CPU_DOMAIN, offsetof(struct thread_info, cpu_domain)); | |
58 | DEFINE(TI_CPU_SAVE, offsetof(struct thread_info, cpu_context)); | |
59 | DEFINE(TI_USED_CP, offsetof(struct thread_info, used_cp)); | |
60 | DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value)); | |
61 | DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate)); | |
9fc31ddc | 62 | #ifdef CONFIG_VFP |
1da177e4 | 63 | DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate)); |
f8f2a852 RK |
64 | #ifdef CONFIG_SMP |
65 | DEFINE(VFP_CPU, offsetof(union vfp_state, hard.cpu)); | |
66 | #endif | |
9fc31ddc | 67 | #endif |
d7f864be CM |
68 | #ifdef CONFIG_ARM_THUMBEE |
69 | DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state)); | |
70 | #endif | |
cdaabbd7 RK |
71 | #ifdef CONFIG_IWMMXT |
72 | DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt)); | |
c17fad11 LB |
73 | #endif |
74 | #ifdef CONFIG_CRUNCH | |
75 | DEFINE(TI_CRUNCH_STATE, offsetof(struct thread_info, crunchstate)); | |
cdaabbd7 | 76 | #endif |
1da177e4 | 77 | BLANK(); |
925c8a1a RK |
78 | DEFINE(S_R0, offsetof(struct pt_regs, ARM_r0)); |
79 | DEFINE(S_R1, offsetof(struct pt_regs, ARM_r1)); | |
80 | DEFINE(S_R2, offsetof(struct pt_regs, ARM_r2)); | |
81 | DEFINE(S_R3, offsetof(struct pt_regs, ARM_r3)); | |
82 | DEFINE(S_R4, offsetof(struct pt_regs, ARM_r4)); | |
83 | DEFINE(S_R5, offsetof(struct pt_regs, ARM_r5)); | |
84 | DEFINE(S_R6, offsetof(struct pt_regs, ARM_r6)); | |
85 | DEFINE(S_R7, offsetof(struct pt_regs, ARM_r7)); | |
86 | DEFINE(S_R8, offsetof(struct pt_regs, ARM_r8)); | |
87 | DEFINE(S_R9, offsetof(struct pt_regs, ARM_r9)); | |
88 | DEFINE(S_R10, offsetof(struct pt_regs, ARM_r10)); | |
89 | DEFINE(S_FP, offsetof(struct pt_regs, ARM_fp)); | |
90 | DEFINE(S_IP, offsetof(struct pt_regs, ARM_ip)); | |
91 | DEFINE(S_SP, offsetof(struct pt_regs, ARM_sp)); | |
92 | DEFINE(S_LR, offsetof(struct pt_regs, ARM_lr)); | |
93 | DEFINE(S_PC, offsetof(struct pt_regs, ARM_pc)); | |
94 | DEFINE(S_PSR, offsetof(struct pt_regs, ARM_cpsr)); | |
95 | DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0)); | |
96 | DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); | |
97 | BLANK(); | |
91c2ebb9 BS |
98 | #ifdef CONFIG_CACHE_L2X0 |
99 | DEFINE(L2X0_R_PHY_BASE, offsetof(struct l2x0_regs, phy_base)); | |
100 | DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl)); | |
101 | DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency)); | |
102 | DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency)); | |
103 | DEFINE(L2X0_R_FILTER_START, offsetof(struct l2x0_regs, filter_start)); | |
104 | DEFINE(L2X0_R_FILTER_END, offsetof(struct l2x0_regs, filter_end)); | |
105 | DEFINE(L2X0_R_PREFETCH_CTRL, offsetof(struct l2x0_regs, prefetch_ctrl)); | |
106 | DEFINE(L2X0_R_PWR_CTRL, offsetof(struct l2x0_regs, pwr_ctrl)); | |
107 | BLANK(); | |
108 | #endif | |
516793c6 | 109 | #ifdef CONFIG_CPU_HAS_ASID |
1da177e4 LT |
110 | DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); |
111 | BLANK(); | |
112 | #endif | |
113 | DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm)); | |
114 | DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags)); | |
115 | BLANK(); | |
116 | DEFINE(VM_EXEC, VM_EXEC); | |
117 | BLANK(); | |
118 | DEFINE(PAGE_SZ, PAGE_SIZE); | |
1da177e4 LT |
119 | BLANK(); |
120 | DEFINE(SYS_ERROR0, 0x9f0000); | |
121 | BLANK(); | |
122 | DEFINE(SIZEOF_MACHINE_DESC, sizeof(struct machine_desc)); | |
2eb9d315 UZ |
123 | DEFINE(MACHINFO_TYPE, offsetof(struct machine_desc, nr)); |
124 | DEFINE(MACHINFO_NAME, offsetof(struct machine_desc, name)); | |
2ceec0c8 UZ |
125 | BLANK(); |
126 | DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list)); | |
2eb9d315 | 127 | DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush)); |
8799ee9f RK |
128 | DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags)); |
129 | DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags)); | |
48d7927b PB |
130 | BLANK(); |
131 | #ifdef MULTI_DABORT | |
132 | DEFINE(PROCESSOR_DABT_FUNC, offsetof(struct processor, _data_abort)); | |
133 | #endif | |
134 | #ifdef MULTI_PABORT | |
135 | DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort)); | |
f6b0fa02 RK |
136 | #endif |
137 | #ifdef MULTI_CPU | |
138 | DEFINE(CPU_SLEEP_SIZE, offsetof(struct processor, suspend_size)); | |
139 | DEFINE(CPU_DO_SUSPEND, offsetof(struct processor, do_suspend)); | |
140 | DEFINE(CPU_DO_RESUME, offsetof(struct processor, do_resume)); | |
141 | #endif | |
142 | #ifdef MULTI_CACHE | |
143 | DEFINE(CACHE_FLUSH_KERN_ALL, offsetof(struct cpu_cache_fns, flush_kern_all)); | |
48d7927b | 144 | #endif |
a9c9147e RK |
145 | BLANK(); |
146 | DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL); | |
147 | DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE); | |
148 | DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE); | |
1da177e4 LT |
149 | return 0; |
150 | } |