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f8c95fe6 SG |
1 | /* |
2 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef __DEBUG_IMX_UART_H | |
10 | #define __DEBUG_IMX_UART_H | |
11 | ||
12 | #define IMX1_UART1_BASE_ADDR 0x00206000 | |
13 | #define IMX1_UART2_BASE_ADDR 0x00207000 | |
14 | #define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR | |
15 | #define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n) | |
16 | ||
17 | #define IMX21_UART1_BASE_ADDR 0x1000a000 | |
18 | #define IMX21_UART2_BASE_ADDR 0x1000b000 | |
19 | #define IMX21_UART3_BASE_ADDR 0x1000c000 | |
20 | #define IMX21_UART4_BASE_ADDR 0x1000d000 | |
21 | #define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR | |
22 | #define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n) | |
23 | ||
24 | #define IMX25_UART1_BASE_ADDR 0x43f90000 | |
25 | #define IMX25_UART2_BASE_ADDR 0x43f94000 | |
26 | #define IMX25_UART3_BASE_ADDR 0x5000c000 | |
27 | #define IMX25_UART4_BASE_ADDR 0x50008000 | |
28 | #define IMX25_UART5_BASE_ADDR 0x5002c000 | |
29 | #define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR | |
30 | #define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n) | |
31 | ||
32 | #define IMX31_UART1_BASE_ADDR 0x43f90000 | |
33 | #define IMX31_UART2_BASE_ADDR 0x43f94000 | |
34 | #define IMX31_UART3_BASE_ADDR 0x5000c000 | |
35 | #define IMX31_UART4_BASE_ADDR 0x43fb0000 | |
36 | #define IMX31_UART5_BASE_ADDR 0x43fb4000 | |
37 | #define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR | |
38 | #define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n) | |
39 | ||
40 | #define IMX35_UART1_BASE_ADDR 0x43f90000 | |
41 | #define IMX35_UART2_BASE_ADDR 0x43f94000 | |
42 | #define IMX35_UART3_BASE_ADDR 0x5000c000 | |
43 | #define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR | |
44 | #define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n) | |
45 | ||
46 | #define IMX51_UART1_BASE_ADDR 0x73fbc000 | |
47 | #define IMX51_UART2_BASE_ADDR 0x73fc0000 | |
48 | #define IMX51_UART3_BASE_ADDR 0x7000c000 | |
49 | #define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR | |
50 | #define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n) | |
51 | ||
52 | #define IMX53_UART1_BASE_ADDR 0x53fbc000 | |
53 | #define IMX53_UART2_BASE_ADDR 0x53fc0000 | |
54 | #define IMX53_UART3_BASE_ADDR 0x5000c000 | |
55 | #define IMX53_UART4_BASE_ADDR 0x53ff0000 | |
56 | #define IMX53_UART5_BASE_ADDR 0x63f90000 | |
57 | #define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR | |
58 | #define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n) | |
59 | ||
60 | #define IMX6Q_UART1_BASE_ADDR 0x02020000 | |
61 | #define IMX6Q_UART2_BASE_ADDR 0x021e8000 | |
62 | #define IMX6Q_UART3_BASE_ADDR 0x021ec000 | |
63 | #define IMX6Q_UART4_BASE_ADDR 0x021f0000 | |
64 | #define IMX6Q_UART5_BASE_ADDR 0x021f4000 | |
65 | #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR | |
66 | #define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) | |
67 | ||
68 | #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) | |
69 | ||
70 | #ifdef CONFIG_DEBUG_IMX1_UART | |
71 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX1) | |
72 | #elif defined(CONFIG_DEBUG_IMX21_IMX27_UART) | |
73 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX21) | |
74 | #elif defined(CONFIG_DEBUG_IMX25_UART) | |
75 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX25) | |
76 | #elif defined(CONFIG_DEBUG_IMX31_UART) | |
77 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) | |
78 | #elif defined(CONFIG_DEBUG_IMX35_UART) | |
79 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX35) | |
80 | #elif defined(CONFIG_DEBUG_IMX51_UART) | |
81 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX51) | |
82 | #elif defined(CONFIG_DEBUG_IMX53_UART) | |
83 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) | |
84 | #elif defined(CONFIG_DEBUG_IMX6Q_UART) | |
85 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) | |
86 | #endif | |
87 | ||
88 | #endif /* __DEBUG_IMX_UART_H */ |