Commit | Line | Data |
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1da177e4 | 1 | /* |
4baa9922 | 2 | * arch/arm/include/asm/tlbflush.h |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1999-2003 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #ifndef _ASMARM_TLBFLUSH_H | |
11 | #define _ASMARM_TLBFLUSH_H | |
12 | ||
0157903e HC |
13 | |
14 | #ifndef CONFIG_MMU | |
15 | ||
16 | #define tlb_flush(tlb) ((void) tlb) | |
17 | ||
fb1c7762 | 18 | #else /* CONFIG_MMU */ |
0157903e | 19 | |
1da177e4 LT |
20 | #include <asm/glue.h> |
21 | ||
22 | #define TLB_V3_PAGE (1 << 0) | |
23 | #define TLB_V4_U_PAGE (1 << 1) | |
24 | #define TLB_V4_D_PAGE (1 << 2) | |
25 | #define TLB_V4_I_PAGE (1 << 3) | |
26 | #define TLB_V6_U_PAGE (1 << 4) | |
27 | #define TLB_V6_D_PAGE (1 << 5) | |
28 | #define TLB_V6_I_PAGE (1 << 6) | |
29 | ||
30 | #define TLB_V3_FULL (1 << 8) | |
31 | #define TLB_V4_U_FULL (1 << 9) | |
32 | #define TLB_V4_D_FULL (1 << 10) | |
33 | #define TLB_V4_I_FULL (1 << 11) | |
34 | #define TLB_V6_U_FULL (1 << 12) | |
35 | #define TLB_V6_D_FULL (1 << 13) | |
36 | #define TLB_V6_I_FULL (1 << 14) | |
37 | ||
38 | #define TLB_V6_U_ASID (1 << 16) | |
39 | #define TLB_V6_D_ASID (1 << 17) | |
40 | #define TLB_V6_I_ASID (1 << 18) | |
41 | ||
bba7d0b9 | 42 | #define TLB_BTB (1 << 28) |
faa7bc51 CM |
43 | |
44 | /* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */ | |
45 | #define TLB_V7_UIS_PAGE (1 << 19) | |
46 | #define TLB_V7_UIS_FULL (1 << 20) | |
47 | #define TLB_V7_UIS_ASID (1 << 21) | |
48 | ||
b8349b56 CM |
49 | /* Inner Shareable BTB operation (ARMv7 MP extensions) */ |
50 | #define TLB_V7_IS_BTB (1 << 22) | |
51 | ||
99c6dc11 | 52 | #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ |
1da177e4 LT |
53 | #define TLB_DCLEAN (1 << 30) |
54 | #define TLB_WB (1 << 31) | |
55 | ||
56 | /* | |
57 | * MMU TLB Model | |
58 | * ============= | |
59 | * | |
60 | * We have the following to choose from: | |
61 | * v3 - ARMv3 | |
62 | * v4 - ARMv4 without write buffer | |
63 | * v4wb - ARMv4 with write buffer without I TLB flush entry instruction | |
64 | * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction | |
99c6dc11 | 65 | * fr - Feroceon (v4wbi with non-outer-cacheable page table walks) |
28853ac8 | 66 | * fa - Faraday (v4 with write buffer with UTLB and branch target buffer (BTB)) |
1da177e4 | 67 | * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction |
61db7fb1 | 68 | * v7wbi - identical to v6wbi |
1da177e4 LT |
69 | */ |
70 | #undef _TLB | |
71 | #undef MULTI_TLB | |
72 | ||
73 | #define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE) | |
74 | ||
75 | #ifdef CONFIG_CPU_TLB_V3 | |
76 | # define v3_possible_flags v3_tlb_flags | |
77 | # define v3_always_flags v3_tlb_flags | |
78 | # ifdef _TLB | |
79 | # define MULTI_TLB 1 | |
80 | # else | |
81 | # define _TLB v3 | |
82 | # endif | |
83 | #else | |
84 | # define v3_possible_flags 0 | |
85 | # define v3_always_flags (-1UL) | |
86 | #endif | |
87 | ||
88 | #define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE) | |
89 | ||
90 | #ifdef CONFIG_CPU_TLB_V4WT | |
91 | # define v4_possible_flags v4_tlb_flags | |
92 | # define v4_always_flags v4_tlb_flags | |
93 | # ifdef _TLB | |
94 | # define MULTI_TLB 1 | |
95 | # else | |
96 | # define _TLB v4 | |
97 | # endif | |
98 | #else | |
99 | # define v4_possible_flags 0 | |
100 | # define v4_always_flags (-1UL) | |
101 | #endif | |
102 | ||
28853ac8 PZ |
103 | #define fa_tlb_flags (TLB_WB | TLB_BTB | TLB_DCLEAN | \ |
104 | TLB_V4_U_FULL | TLB_V4_U_PAGE) | |
105 | ||
106 | #ifdef CONFIG_CPU_TLB_FA | |
107 | # define fa_possible_flags fa_tlb_flags | |
108 | # define fa_always_flags fa_tlb_flags | |
109 | # ifdef _TLB | |
110 | # define MULTI_TLB 1 | |
111 | # else | |
112 | # define _TLB fa | |
113 | # endif | |
114 | #else | |
115 | # define fa_possible_flags 0 | |
116 | # define fa_always_flags (-1UL) | |
117 | #endif | |
118 | ||
1da177e4 LT |
119 | #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \ |
120 | TLB_V4_I_FULL | TLB_V4_D_FULL | \ | |
121 | TLB_V4_I_PAGE | TLB_V4_D_PAGE) | |
122 | ||
123 | #ifdef CONFIG_CPU_TLB_V4WBI | |
124 | # define v4wbi_possible_flags v4wbi_tlb_flags | |
125 | # define v4wbi_always_flags v4wbi_tlb_flags | |
126 | # ifdef _TLB | |
127 | # define MULTI_TLB 1 | |
128 | # else | |
129 | # define _TLB v4wbi | |
130 | # endif | |
131 | #else | |
132 | # define v4wbi_possible_flags 0 | |
133 | # define v4wbi_always_flags (-1UL) | |
134 | #endif | |
135 | ||
99c6dc11 LB |
136 | #define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \ |
137 | TLB_V4_I_FULL | TLB_V4_D_FULL | \ | |
138 | TLB_V4_I_PAGE | TLB_V4_D_PAGE) | |
139 | ||
140 | #ifdef CONFIG_CPU_TLB_FEROCEON | |
141 | # define fr_possible_flags fr_tlb_flags | |
142 | # define fr_always_flags fr_tlb_flags | |
143 | # ifdef _TLB | |
144 | # define MULTI_TLB 1 | |
145 | # else | |
146 | # define _TLB v4wbi | |
147 | # endif | |
148 | #else | |
149 | # define fr_possible_flags 0 | |
150 | # define fr_always_flags (-1UL) | |
151 | #endif | |
152 | ||
1da177e4 LT |
153 | #define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \ |
154 | TLB_V4_I_FULL | TLB_V4_D_FULL | \ | |
155 | TLB_V4_D_PAGE) | |
156 | ||
157 | #ifdef CONFIG_CPU_TLB_V4WB | |
158 | # define v4wb_possible_flags v4wb_tlb_flags | |
159 | # define v4wb_always_flags v4wb_tlb_flags | |
160 | # ifdef _TLB | |
161 | # define MULTI_TLB 1 | |
162 | # else | |
163 | # define _TLB v4wb | |
164 | # endif | |
165 | #else | |
166 | # define v4wb_possible_flags 0 | |
167 | # define v4wb_always_flags (-1UL) | |
168 | #endif | |
169 | ||
bba7d0b9 | 170 | #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ |
1da177e4 LT |
171 | TLB_V6_I_FULL | TLB_V6_D_FULL | \ |
172 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ | |
173 | TLB_V6_I_ASID | TLB_V6_D_ASID) | |
174 | ||
175 | #ifdef CONFIG_CPU_TLB_V6 | |
176 | # define v6wbi_possible_flags v6wbi_tlb_flags | |
177 | # define v6wbi_always_flags v6wbi_tlb_flags | |
178 | # ifdef _TLB | |
179 | # define MULTI_TLB 1 | |
180 | # else | |
181 | # define _TLB v6wbi | |
182 | # endif | |
183 | #else | |
184 | # define v6wbi_possible_flags 0 | |
185 | # define v6wbi_always_flags (-1UL) | |
186 | #endif | |
187 | ||
faa7bc51 | 188 | #ifdef CONFIG_SMP |
b8349b56 | 189 | #define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \ |
faa7bc51 CM |
190 | TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID) |
191 | #else | |
192 | #define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ | |
193 | TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID) | |
194 | #endif | |
195 | ||
2ccdd1e7 | 196 | #ifdef CONFIG_CPU_TLB_V7 |
faa7bc51 CM |
197 | # define v7wbi_possible_flags v7wbi_tlb_flags |
198 | # define v7wbi_always_flags v7wbi_tlb_flags | |
2ccdd1e7 CM |
199 | # ifdef _TLB |
200 | # define MULTI_TLB 1 | |
201 | # else | |
202 | # define _TLB v7wbi | |
203 | # endif | |
204 | #else | |
205 | # define v7wbi_possible_flags 0 | |
206 | # define v7wbi_always_flags (-1UL) | |
207 | #endif | |
208 | ||
1da177e4 LT |
209 | #ifndef _TLB |
210 | #error Unknown TLB model | |
211 | #endif | |
212 | ||
213 | #ifndef __ASSEMBLY__ | |
214 | ||
e8edc6e0 AD |
215 | #include <linux/sched.h> |
216 | ||
1da177e4 LT |
217 | struct cpu_tlb_fns { |
218 | void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *); | |
219 | void (*flush_kern_range)(unsigned long, unsigned long); | |
220 | unsigned long tlb_flags; | |
221 | }; | |
222 | ||
223 | /* | |
224 | * Select the calling method | |
225 | */ | |
226 | #ifdef MULTI_TLB | |
227 | ||
228 | #define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range | |
229 | #define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range | |
230 | ||
231 | #else | |
232 | ||
233 | #define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range) | |
234 | #define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range) | |
235 | ||
236 | extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *); | |
237 | extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long); | |
238 | ||
239 | #endif | |
240 | ||
241 | extern struct cpu_tlb_fns cpu_tlb; | |
242 | ||
243 | #define __cpu_tlb_flags cpu_tlb.tlb_flags | |
244 | ||
245 | /* | |
246 | * TLB Management | |
247 | * ============== | |
248 | * | |
249 | * The arch/arm/mm/tlb-*.S files implement these methods. | |
250 | * | |
251 | * The TLB specific code is expected to perform whatever tests it | |
252 | * needs to determine if it should invalidate the TLB for each | |
253 | * call. Start addresses are inclusive and end addresses are | |
254 | * exclusive; it is safe to round these addresses down. | |
255 | * | |
256 | * flush_tlb_all() | |
257 | * | |
258 | * Invalidate the entire TLB. | |
259 | * | |
260 | * flush_tlb_mm(mm) | |
261 | * | |
262 | * Invalidate all TLB entries in a particular address | |
263 | * space. | |
264 | * - mm - mm_struct describing address space | |
265 | * | |
266 | * flush_tlb_range(mm,start,end) | |
267 | * | |
268 | * Invalidate a range of TLB entries in the specified | |
269 | * address space. | |
270 | * - mm - mm_struct describing address space | |
271 | * - start - start address (may not be aligned) | |
272 | * - end - end address (exclusive, may not be aligned) | |
273 | * | |
274 | * flush_tlb_page(vaddr,vma) | |
275 | * | |
276 | * Invalidate the specified page in the specified address range. | |
277 | * - vaddr - virtual address (may not be aligned) | |
278 | * - vma - vma_struct describing address range | |
279 | * | |
280 | * flush_kern_tlb_page(kaddr) | |
281 | * | |
282 | * Invalidate the TLB entry for the specified page. The address | |
283 | * will be in the kernels virtual memory space. Current uses | |
284 | * only require the D-TLB to be invalidated. | |
285 | * - kaddr - Kernel virtual memory address | |
286 | */ | |
287 | ||
288 | /* | |
289 | * We optimise the code below by: | |
290 | * - building a set of TLB flags that might be set in __cpu_tlb_flags | |
291 | * - building a set of TLB flags that will always be set in __cpu_tlb_flags | |
292 | * - if we're going to need __cpu_tlb_flags, access it once and only once | |
293 | * | |
294 | * This allows us to build optimal assembly for the single-CPU type case, | |
295 | * and as close to optimal given the compiler constrants for multi-CPU | |
296 | * case. We could do better for the multi-CPU case if the compiler | |
297 | * implemented the "%?" method, but this has been discontinued due to too | |
298 | * many people getting it wrong. | |
299 | */ | |
300 | #define possible_tlb_flags (v3_possible_flags | \ | |
301 | v4_possible_flags | \ | |
302 | v4wbi_possible_flags | \ | |
99c6dc11 | 303 | fr_possible_flags | \ |
1da177e4 | 304 | v4wb_possible_flags | \ |
28853ac8 | 305 | fa_possible_flags | \ |
61db7fb1 PW |
306 | v6wbi_possible_flags | \ |
307 | v7wbi_possible_flags) | |
1da177e4 LT |
308 | |
309 | #define always_tlb_flags (v3_always_flags & \ | |
310 | v4_always_flags & \ | |
311 | v4wbi_always_flags & \ | |
99c6dc11 | 312 | fr_always_flags & \ |
1da177e4 | 313 | v4wb_always_flags & \ |
28853ac8 | 314 | fa_always_flags & \ |
61db7fb1 PW |
315 | v6wbi_always_flags & \ |
316 | v7wbi_always_flags) | |
1da177e4 LT |
317 | |
318 | #define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f))) | |
319 | ||
603fff54 | 320 | static inline void local_flush_tlb_all(void) |
1da177e4 LT |
321 | { |
322 | const int zero = 0; | |
323 | const unsigned int __tlb_flag = __cpu_tlb_flags; | |
324 | ||
325 | if (tlb_flag(TLB_WB)) | |
e6a5d66f | 326 | dsb(); |
1da177e4 LT |
327 | |
328 | if (tlb_flag(TLB_V3_FULL)) | |
6a39dd62 | 329 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); |
1da177e4 | 330 | if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL)) |
6a39dd62 | 331 | asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc"); |
1da177e4 | 332 | if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL)) |
6a39dd62 | 333 | asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); |
1da177e4 | 334 | if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) |
6a39dd62 | 335 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); |
faa7bc51 CM |
336 | if (tlb_flag(TLB_V7_UIS_FULL)) |
337 | asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc"); | |
e6a5d66f | 338 | |
bba7d0b9 | 339 | if (tlb_flag(TLB_BTB)) { |
e6a5d66f CM |
340 | /* flush the branch target cache */ |
341 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | |
342 | dsb(); | |
343 | isb(); | |
344 | } | |
b8349b56 CM |
345 | if (tlb_flag(TLB_V7_IS_BTB)) { |
346 | /* flush the branch target cache */ | |
347 | asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc"); | |
348 | dsb(); | |
349 | isb(); | |
350 | } | |
1da177e4 LT |
351 | } |
352 | ||
603fff54 | 353 | static inline void local_flush_tlb_mm(struct mm_struct *mm) |
1da177e4 LT |
354 | { |
355 | const int zero = 0; | |
356 | const int asid = ASID(mm); | |
357 | const unsigned int __tlb_flag = __cpu_tlb_flags; | |
358 | ||
359 | if (tlb_flag(TLB_WB)) | |
e6a5d66f | 360 | dsb(); |
1da177e4 | 361 | |
daaeb6c9 | 362 | if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) { |
1da177e4 | 363 | if (tlb_flag(TLB_V3_FULL)) |
6a39dd62 | 364 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); |
1da177e4 | 365 | if (tlb_flag(TLB_V4_U_FULL)) |
6a39dd62 | 366 | asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc"); |
1da177e4 | 367 | if (tlb_flag(TLB_V4_D_FULL)) |
6a39dd62 | 368 | asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); |
1da177e4 | 369 | if (tlb_flag(TLB_V4_I_FULL)) |
6a39dd62 | 370 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); |
1da177e4 | 371 | } |
daaeb6c9 | 372 | put_cpu(); |
1da177e4 LT |
373 | |
374 | if (tlb_flag(TLB_V6_U_ASID)) | |
6a39dd62 | 375 | asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc"); |
1da177e4 | 376 | if (tlb_flag(TLB_V6_D_ASID)) |
6a39dd62 | 377 | asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc"); |
1da177e4 | 378 | if (tlb_flag(TLB_V6_I_ASID)) |
6a39dd62 | 379 | asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); |
faa7bc51 CM |
380 | if (tlb_flag(TLB_V7_UIS_ASID)) |
381 | asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc"); | |
e6a5d66f | 382 | |
bba7d0b9 | 383 | if (tlb_flag(TLB_BTB)) { |
e6a5d66f CM |
384 | /* flush the branch target cache */ |
385 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | |
386 | dsb(); | |
387 | } | |
b8349b56 CM |
388 | if (tlb_flag(TLB_V7_IS_BTB)) { |
389 | /* flush the branch target cache */ | |
390 | asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc"); | |
391 | dsb(); | |
392 | isb(); | |
393 | } | |
1da177e4 LT |
394 | } |
395 | ||
396 | static inline void | |
603fff54 | 397 | local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) |
1da177e4 LT |
398 | { |
399 | const int zero = 0; | |
400 | const unsigned int __tlb_flag = __cpu_tlb_flags; | |
401 | ||
402 | uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); | |
403 | ||
404 | if (tlb_flag(TLB_WB)) | |
e6a5d66f | 405 | dsb(); |
1da177e4 | 406 | |
56f8ba83 | 407 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { |
1da177e4 | 408 | if (tlb_flag(TLB_V3_PAGE)) |
6a39dd62 | 409 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc"); |
1da177e4 | 410 | if (tlb_flag(TLB_V4_U_PAGE)) |
6a39dd62 | 411 | asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc"); |
1da177e4 | 412 | if (tlb_flag(TLB_V4_D_PAGE)) |
6a39dd62 | 413 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); |
1da177e4 | 414 | if (tlb_flag(TLB_V4_I_PAGE)) |
6a39dd62 | 415 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); |
1da177e4 | 416 | if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) |
6a39dd62 | 417 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); |
1da177e4 LT |
418 | } |
419 | ||
420 | if (tlb_flag(TLB_V6_U_PAGE)) | |
6a39dd62 | 421 | asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc"); |
1da177e4 | 422 | if (tlb_flag(TLB_V6_D_PAGE)) |
6a39dd62 | 423 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); |
1da177e4 | 424 | if (tlb_flag(TLB_V6_I_PAGE)) |
6a39dd62 | 425 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); |
faa7bc51 CM |
426 | if (tlb_flag(TLB_V7_UIS_PAGE)) |
427 | asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc"); | |
e6a5d66f | 428 | |
bba7d0b9 | 429 | if (tlb_flag(TLB_BTB)) { |
e6a5d66f CM |
430 | /* flush the branch target cache */ |
431 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | |
432 | dsb(); | |
433 | } | |
b8349b56 CM |
434 | if (tlb_flag(TLB_V7_IS_BTB)) { |
435 | /* flush the branch target cache */ | |
436 | asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc"); | |
437 | dsb(); | |
438 | isb(); | |
439 | } | |
1da177e4 LT |
440 | } |
441 | ||
603fff54 | 442 | static inline void local_flush_tlb_kernel_page(unsigned long kaddr) |
1da177e4 LT |
443 | { |
444 | const int zero = 0; | |
445 | const unsigned int __tlb_flag = __cpu_tlb_flags; | |
446 | ||
447 | kaddr &= PAGE_MASK; | |
448 | ||
449 | if (tlb_flag(TLB_WB)) | |
e6a5d66f | 450 | dsb(); |
1da177e4 LT |
451 | |
452 | if (tlb_flag(TLB_V3_PAGE)) | |
6a39dd62 | 453 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc"); |
1da177e4 | 454 | if (tlb_flag(TLB_V4_U_PAGE)) |
6a39dd62 | 455 | asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc"); |
1da177e4 | 456 | if (tlb_flag(TLB_V4_D_PAGE)) |
6a39dd62 | 457 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); |
1da177e4 | 458 | if (tlb_flag(TLB_V4_I_PAGE)) |
6a39dd62 | 459 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); |
1da177e4 | 460 | if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) |
6a39dd62 | 461 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); |
1da177e4 LT |
462 | |
463 | if (tlb_flag(TLB_V6_U_PAGE)) | |
6a39dd62 | 464 | asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc"); |
1da177e4 | 465 | if (tlb_flag(TLB_V6_D_PAGE)) |
6a39dd62 | 466 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); |
1da177e4 | 467 | if (tlb_flag(TLB_V6_I_PAGE)) |
6a39dd62 | 468 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); |
faa7bc51 CM |
469 | if (tlb_flag(TLB_V7_UIS_PAGE)) |
470 | asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc"); | |
6a0e2430 | 471 | |
bba7d0b9 | 472 | if (tlb_flag(TLB_BTB)) { |
e6a5d66f CM |
473 | /* flush the branch target cache */ |
474 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | |
475 | dsb(); | |
476 | isb(); | |
477 | } | |
b8349b56 CM |
478 | if (tlb_flag(TLB_V7_IS_BTB)) { |
479 | /* flush the branch target cache */ | |
480 | asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc"); | |
481 | dsb(); | |
482 | isb(); | |
483 | } | |
1da177e4 LT |
484 | } |
485 | ||
486 | /* | |
487 | * flush_pmd_entry | |
488 | * | |
489 | * Flush a PMD entry (word aligned, or double-word aligned) to | |
490 | * RAM if the TLB for the CPU we are running on requires this. | |
491 | * This is typically used when we are creating PMD entries. | |
492 | * | |
493 | * clean_pmd_entry | |
494 | * | |
495 | * Clean (but don't drain the write buffer) if the CPU requires | |
496 | * these operations. This is typically used when we are removing | |
497 | * PMD entries. | |
498 | */ | |
499 | static inline void flush_pmd_entry(pmd_t *pmd) | |
500 | { | |
1da177e4 LT |
501 | const unsigned int __tlb_flag = __cpu_tlb_flags; |
502 | ||
503 | if (tlb_flag(TLB_DCLEAN)) | |
6a39dd62 DJ |
504 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" |
505 | : : "r" (pmd) : "cc"); | |
99c6dc11 LB |
506 | |
507 | if (tlb_flag(TLB_L2CLEAN_FR)) | |
508 | asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd" | |
509 | : : "r" (pmd) : "cc"); | |
510 | ||
1da177e4 | 511 | if (tlb_flag(TLB_WB)) |
e6a5d66f | 512 | dsb(); |
1da177e4 LT |
513 | } |
514 | ||
515 | static inline void clean_pmd_entry(pmd_t *pmd) | |
516 | { | |
517 | const unsigned int __tlb_flag = __cpu_tlb_flags; | |
518 | ||
519 | if (tlb_flag(TLB_DCLEAN)) | |
6a39dd62 DJ |
520 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" |
521 | : : "r" (pmd) : "cc"); | |
99c6dc11 LB |
522 | |
523 | if (tlb_flag(TLB_L2CLEAN_FR)) | |
524 | asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd" | |
525 | : : "r" (pmd) : "cc"); | |
1da177e4 LT |
526 | } |
527 | ||
528 | #undef tlb_flag | |
529 | #undef always_tlb_flags | |
530 | #undef possible_tlb_flags | |
531 | ||
532 | /* | |
533 | * Convert calls to our calling convention. | |
534 | */ | |
603fff54 RK |
535 | #define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma) |
536 | #define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e) | |
537 | ||
538 | #ifndef CONFIG_SMP | |
539 | #define flush_tlb_all local_flush_tlb_all | |
540 | #define flush_tlb_mm local_flush_tlb_mm | |
541 | #define flush_tlb_page local_flush_tlb_page | |
542 | #define flush_tlb_kernel_page local_flush_tlb_kernel_page | |
543 | #define flush_tlb_range local_flush_tlb_range | |
544 | #define flush_tlb_kernel_range local_flush_tlb_kernel_range | |
545 | #else | |
546 | extern void flush_tlb_all(void); | |
547 | extern void flush_tlb_mm(struct mm_struct *mm); | |
548 | extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr); | |
549 | extern void flush_tlb_kernel_page(unsigned long kaddr); | |
550 | extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); | |
551 | extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); | |
552 | #endif | |
1da177e4 LT |
553 | |
554 | /* | |
555 | * if PG_dcache_dirty is set for the page, we need to ensure that any | |
556 | * cache entries for the kernels virtual memory range are written | |
557 | * back to the page. | |
558 | */ | |
4b3073e1 RK |
559 | extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, |
560 | pte_t *ptep); | |
1da177e4 | 561 | |
1da177e4 LT |
562 | #endif |
563 | ||
0157903e HC |
564 | #endif /* CONFIG_MMU */ |
565 | ||
1da177e4 | 566 | #endif |