[linux-2.6-block.git] / arch / arm / include / asm / ptrace.h

/*
 *  arch/arm/include/asm/ptrace.h
 *
 *  Copyright (C) 1996-2003 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __ASM_ARM_PTRACE_H
#define __ASM_ARM_PTRACE_H

#include <asm/hwcap.h>

#define PTRACE_GETREGS		12
#define PTRACE_SETREGS		13
#define PTRACE_GETFPREGS	14
#define PTRACE_SETFPREGS	15
/* PTRACE_ATTACH is 16 */
/* PTRACE_DETACH is 17 */
#define PTRACE_GETWMMXREGS	18
#define PTRACE_SETWMMXREGS	19
/* 20 is unused */
#define PTRACE_OLDSETOPTIONS	21
#define PTRACE_GET_THREAD_AREA	22
#define PTRACE_SET_SYSCALL	23
/* PTRACE_SYSCALL is 24 */
#define PTRACE_GETCRUNCHREGS	25
#define PTRACE_SETCRUNCHREGS	26
#define PTRACE_GETVFPREGS	27
#define PTRACE_SETVFPREGS	28
#define PTRACE_GETHBPREGS	29
#define PTRACE_SETHBPREGS	30

/*
 * PSR bits
 */
#define USR26_MODE	0x00000000
#define FIQ26_MODE	0x00000001
#define IRQ26_MODE	0x00000002
#define SVC26_MODE	0x00000003
#define USR_MODE	0x00000010
#define FIQ_MODE	0x00000011
#define IRQ_MODE	0x00000012
#define SVC_MODE	0x00000013
#define ABT_MODE	0x00000017
#define UND_MODE	0x0000001b
#define SYSTEM_MODE	0x0000001f
#define MODE32_BIT	0x00000010
#define MODE_MASK	0x0000001f
#define PSR_T_BIT	0x00000020
#define PSR_F_BIT	0x00000040
#define PSR_I_BIT	0x00000080
#define PSR_A_BIT	0x00000100
#define PSR_E_BIT	0x00000200
#define PSR_J_BIT	0x01000000
#define PSR_Q_BIT	0x08000000
#define PSR_V_BIT	0x10000000
#define PSR_C_BIT	0x20000000
#define PSR_Z_BIT	0x40000000
#define PSR_N_BIT	0x80000000

/*
 * Groups of PSR bits
 */
#define PSR_f		0xff000000	/* Flags		*/
#define PSR_s		0x00ff0000	/* Status		*/
#define PSR_x		0x0000ff00	/* Extension		*/
#define PSR_c		0x000000ff	/* Control		*/

/*
 * ARMv7 groups of PSR bits
 */
#define APSR_MASK	0xf80f0000	/* N, Z, C, V, Q and GE flags */
#define PSR_ISET_MASK	0x01000010	/* ISA state (J, T) mask */
#define PSR_IT_MASK	0x0600fc00	/* If-Then execution state mask */
#define PSR_ENDIAN_MASK	0x00000200	/* Endianness state mask */

/*
 * Default endianness state
 */
#ifdef CONFIG_CPU_ENDIAN_BE8
#define PSR_ENDSTATE	PSR_E_BIT
#else
#define PSR_ENDSTATE	0
#endif

/* 
 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
 * process is located in memory.
 */
#define PT_TEXT_ADDR		0x10000
#define PT_DATA_ADDR		0x10004
#define PT_TEXT_END_ADDR	0x10008

#ifndef __ASSEMBLY__

/*
 * This struct defines the way the registers are stored on the
 * stack during a system call.  Note that sizeof(struct pt_regs)
 * has to be a multiple of 8.
 */
#ifndef __KERNEL__
struct pt_regs {
	long uregs[18];
};
#else /* __KERNEL__ */
struct pt_regs {
	unsigned long uregs[18];
};
#endif /* __KERNEL__ */

#define ARM_cpsr	uregs[16]
#define ARM_pc		uregs[15]
#define ARM_lr		uregs[14]
#define ARM_sp		uregs[13]
#define ARM_ip		uregs[12]
#define ARM_fp		uregs[11]
#define ARM_r10		uregs[10]
#define ARM_r9		uregs[9]
#define ARM_r8		uregs[8]
#define ARM_r7		uregs[7]
#define ARM_r6		uregs[6]
#define ARM_r5		uregs[5]
#define ARM_r4		uregs[4]
#define ARM_r3		uregs[3]
#define ARM_r2		uregs[2]
#define ARM_r1		uregs[1]
#define ARM_r0		uregs[0]
#define ARM_ORIG_r0	uregs[17]

/*
 * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
 * and core dumps.
 */
#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ )

#ifdef __KERNEL__

#define user_mode(regs)	\
	(((regs)->ARM_cpsr & 0xf) == 0)

#ifdef CONFIG_ARM_THUMB
#define thumb_mode(regs) \
	(((regs)->ARM_cpsr & PSR_T_BIT))
#else
#define thumb_mode(regs) (0)
#endif

#define isa_mode(regs) \
	((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
	 (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))

#define processor_mode(regs) \
	((regs)->ARM_cpsr & MODE_MASK)

#define interrupts_enabled(regs) \
	(!((regs)->ARM_cpsr & PSR_I_BIT))

#define fast_interrupts_enabled(regs) \
	(!((regs)->ARM_cpsr & PSR_F_BIT))

/* Are the current registers suitable for user mode?
 * (used to maintain security in signal handlers)
 */
static inline int valid_user_regs(struct pt_regs *regs)
{
	unsigned long mode = regs->ARM_cpsr & MODE_MASK;

	/*
	 * Always clear the F (FIQ) and A (delayed abort) bits
	 */
	regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);

	if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
		if (mode == USR_MODE)
			return 1;
		if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
			return 1;
	}

	/*
	 * Force CPSR to something logical...
	 */
	regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
	if (!(elf_hwcap & HWCAP_26BIT))
		regs->ARM_cpsr |= USR_MODE;

	return 0;
}

static inline long regs_return_value(struct pt_regs *regs)
{
	return regs->ARM_r0;
}

#define instruction_pointer(regs)	(regs)->ARM_pc

#ifdef CONFIG_SMP
extern unsigned long profile_pc(struct pt_regs *regs);
#else
#define profile_pc(regs) instruction_pointer(regs)
#endif

#define predicate(x)		((x) & 0xf0000000)
#define PREDICATE_ALWAYS	0xe0000000

/*
 * True if instr is a 32-bit thumb instruction. This works if instr
 * is the first or only half-word of a thumb instruction. It also works
 * when instr holds all 32-bits of a wide thumb instruction if stored
 * in the form (first_half<<16)|(second_half)
 */
#define is_wide_instruction(instr)	((unsigned)(instr) >= 0xe800)

/*
 * kprobe-based event tracer support
 */
#include <linux/stddef.h>
#include <linux/types.h>
#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))

extern int regs_query_register_offset(const char *name);
extern const char *regs_query_register_name(unsigned int offset);
extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
					       unsigned int n);

/**
 * regs_get_register() - get register value from its offset
 * @regs:	   pt_regs from which register value is gotten
 * @offset:    offset number of the register.
 *
 * regs_get_register returns the value of a register whose offset from @regs.
 * The @offset is the offset of the register in struct pt_regs.
 * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
 */
static inline unsigned long regs_get_register(struct pt_regs *regs,
					      unsigned int offset)
{
	if (unlikely(offset > MAX_REG_OFFSET))
		return 0;
	return *(unsigned long *)((unsigned long)regs + offset);
}

/* Valid only for Kernel mode traps. */
static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
{
	return regs->ARM_sp;
}

static inline unsigned long user_stack_pointer(struct pt_regs *regs)
{
	return regs->ARM_sp;
}

#define current_pt_regs(void) ({				\
	register unsigned long sp asm ("sp");			\
	(struct pt_regs *)((sp | (THREAD_SIZE - 1)) - 7) - 1;	\
})

#endif /* __KERNEL__ */

#endif /* __ASSEMBLY__ */

#endif
Commit	Line	Data
1da177e4	1	/*
4baa9922	2	* arch/arm/include/asm/ptrace.h
1da177e4 LT	3	*
	4	* Copyright (C) 1996-2003 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef __ASM_ARM_PTRACE_H
	11	#define __ASM_ARM_PTRACE_H
	12
d1cbbd6b CM	13	#include <asm/hwcap.h>
d1cbbd6b CM	14
1da177e4 LT	15	#define PTRACE_GETREGS 12
	16	#define PTRACE_SETREGS 13
	17	#define PTRACE_GETFPREGS 14
	18	#define PTRACE_SETFPREGS 15
1b116522 RK	19	/* PTRACE_ATTACH is 16 */
1b116522 RK	20	/* PTRACE_DETACH is 17 */
1da177e4 LT	21	#define PTRACE_GETWMMXREGS 18
1da177e4 LT	22	#define PTRACE_SETWMMXREGS 19
1b116522	23	/* 20 is unused */
1da177e4	24	#define PTRACE_OLDSETOPTIONS 21
1da177e4	25	#define PTRACE_GET_THREAD_AREA 22
3f471126	26	#define PTRACE_SET_SYSCALL 23
5429b060	27	/* PTRACE_SYSCALL is 24 */
5429b060 LB	28	#define PTRACE_GETCRUNCHREGS 25
5429b060 LB	29	#define PTRACE_SETCRUNCHREGS 26
3d1228ea CM	30	#define PTRACE_GETVFPREGS 27
3d1228ea CM	31	#define PTRACE_SETVFPREGS 28
864232fa WD	32	#define PTRACE_GETHBPREGS 29
864232fa WD	33	#define PTRACE_SETHBPREGS 30
5429b060	34
1da177e4 LT	35	/*
	36	* PSR bits
	37	*/
	38	#define USR26_MODE 0x00000000
	39	#define FIQ26_MODE 0x00000001
	40	#define IRQ26_MODE 0x00000002
	41	#define SVC26_MODE 0x00000003
	42	#define USR_MODE 0x00000010
	43	#define FIQ_MODE 0x00000011
	44	#define IRQ_MODE 0x00000012
	45	#define SVC_MODE 0x00000013
	46	#define ABT_MODE 0x00000017
	47	#define UND_MODE 0x0000001b
	48	#define SYSTEM_MODE 0x0000001f
	49	#define MODE32_BIT 0x00000010
	50	#define MODE_MASK 0x0000001f
	51	#define PSR_T_BIT 0x00000020
	52	#define PSR_F_BIT 0x00000040
	53	#define PSR_I_BIT 0x00000080
d1cbbd6b	54	#define PSR_A_BIT 0x00000100
26584853	55	#define PSR_E_BIT 0x00000200
1da177e4 LT	56	#define PSR_J_BIT 0x01000000
	57	#define PSR_Q_BIT 0x08000000
	58	#define PSR_V_BIT 0x10000000
	59	#define PSR_C_BIT 0x20000000
	60	#define PSR_Z_BIT 0x40000000
	61	#define PSR_N_BIT 0x80000000
1da177e4 LT	62
	63	/*
	64	* Groups of PSR bits
	65	*/
	66	#define PSR_f 0xff000000 /* Flags */
	67	#define PSR_s 0x00ff0000 /* Status */
	68	#define PSR_x 0x0000ff00 /* Extension */
	69	#define PSR_c 0x000000ff /* Control */
	70
d71e1352	71	/*
7460bce4	72	* ARMv7 groups of PSR bits
d71e1352	73	*/
7460bce4	74	#define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */
d71e1352 CM	75	#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */
	76	#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
	77	#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */
	78
26584853 CM	79	/*
	80	* Default endianness state
	81	*/
	82	#ifdef CONFIG_CPU_ENDIAN_BE8
	83	#define PSR_ENDSTATE PSR_E_BIT
	84	#else
	85	#define PSR_ENDSTATE 0
	86	#endif
	87
68b7f715 PB	88	/*
	89	* These are 'magic' values for PTRACE_PEEKUSR that return info about where a
	90	* process is located in memory.
	91	*/
	92	#define PT_TEXT_ADDR 0x10000
	93	#define PT_DATA_ADDR 0x10004
	94	#define PT_TEXT_END_ADDR 0x10008
	95
1da177e4 LT	96	#ifndef __ASSEMBLY__
1da177e4 LT	97
2dede2d8 NP	98	/*
	99	* This struct defines the way the registers are stored on the
	100	* stack during a system call. Note that sizeof(struct pt_regs)
	101	* has to be a multiple of 8.
	102	*/
092a4e95	103	#ifndef __KERNEL__
1da177e4 LT	104	struct pt_regs {
	105	long uregs[18];
	106	};
092a4e95 JI	107	#else /* __KERNEL__ */
	108	struct pt_regs {
	109	unsigned long uregs[18];
	110	};
	111	#endif /* __KERNEL__ */
1da177e4 LT	112
	113	#define ARM_cpsr uregs[16]
	114	#define ARM_pc uregs[15]
	115	#define ARM_lr uregs[14]
	116	#define ARM_sp uregs[13]
	117	#define ARM_ip uregs[12]
	118	#define ARM_fp uregs[11]
	119	#define ARM_r10 uregs[10]
	120	#define ARM_r9 uregs[9]
	121	#define ARM_r8 uregs[8]
	122	#define ARM_r7 uregs[7]
	123	#define ARM_r6 uregs[6]
	124	#define ARM_r5 uregs[5]
	125	#define ARM_r4 uregs[4]
	126	#define ARM_r3 uregs[3]
	127	#define ARM_r2 uregs[2]
	128	#define ARM_r1 uregs[1]
	129	#define ARM_r0 uregs[0]
	130	#define ARM_ORIG_r0 uregs[17]
	131
5be6f62b DM	132	/*
	133	* The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
	134	* and core dumps.
	135	*/
	136	#define ARM_VFPREGS_SIZE ( 32 * 8 /fpregs/ + 4 /fpscr/ )
	137
1da177e4 LT	138	#ifdef __KERNEL__
	139
	140	#define user_mode(regs) \
	141	(((regs)->ARM_cpsr & 0xf) == 0)
	142
	143	#ifdef CONFIG_ARM_THUMB
	144	#define thumb_mode(regs) \
	145	(((regs)->ARM_cpsr & PSR_T_BIT))
	146	#else
	147	#define thumb_mode(regs) (0)
	148	#endif
	149
909d6c6c GD	150	#define isa_mode(regs) \
	151	((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) \| \
	152	(((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
	153
1da177e4 LT	154	#define processor_mode(regs) \
	155	((regs)->ARM_cpsr & MODE_MASK)
	156
	157	#define interrupts_enabled(regs) \
	158	(!((regs)->ARM_cpsr & PSR_I_BIT))
	159
	160	#define fast_interrupts_enabled(regs) \
	161	(!((regs)->ARM_cpsr & PSR_F_BIT))
	162
1da177e4 LT	163	/* Are the current registers suitable for user mode?
	164	* (used to maintain security in signal handlers)
	165	*/
	166	static inline int valid_user_regs(struct pt_regs *regs)
	167	{
41e2e8fd RK	168	unsigned long mode = regs->ARM_cpsr & MODE_MASK;
	169
	170	/*
	171	* Always clear the F (FIQ) and A (delayed abort) bits
	172	*/
	173	regs->ARM_cpsr &= ~(PSR_F_BIT \| PSR_A_BIT);
	174
	175	if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
	176	if (mode == USR_MODE)
	177	return 1;
	178	if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
	179	return 1;
d1cbbd6b	180	}
1da177e4 LT	181
	182	/*
	183	* Force CPSR to something logical...
	184	*/
41e2e8fd	185	regs->ARM_cpsr &= PSR_f \| PSR_s \| PSR_x \| PSR_T_BIT \| MODE32_BIT;
d1cbbd6b CM	186	if (!(elf_hwcap & HWCAP_26BIT))
d1cbbd6b CM	187	regs->ARM_cpsr \|= USR_MODE;
1da177e4 LT	188
	189	return 0;
	190	}
	191
29ef73b7 NH	192	static inline long regs_return_value(struct pt_regs *regs)
	193	{
	194	return regs->ARM_r0;
	195	}
	196
1de765c1	197	#define instruction_pointer(regs) (regs)->ARM_pc
1da177e4 LT	198
	199	#ifdef CONFIG_SMP
	200	extern unsigned long profile_pc(struct pt_regs *regs);
	201	#else
	202	#define profile_pc(regs) instruction_pointer(regs)
	203	#endif
	204
652a12ef	205	#define predicate(x) ((x) & 0xf0000000)
1da177e4	206	#define PREDICATE_ALWAYS 0xe0000000
f22ab814	207
592201a9 JM	208	/*
	209	* True if instr is a 32-bit thumb instruction. This works if instr
	210	* is the first or only half-word of a thumb instruction. It also works
	211	* when instr holds all 32-bits of a wide thumb instruction if stored
	212	* in the form (first_half<<16)\|(second_half)
	213	*/
	214	#define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800)
	215
e513f8bf WD	216	/*
	217	* kprobe-based event tracer support
	218	*/
	219	#include <linux/stddef.h>
	220	#include <linux/types.h>
	221	#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
	222
	223	extern int regs_query_register_offset(const char *name);
	224	extern const char *regs_query_register_name(unsigned int offset);
	225	extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
	226	extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
	227	unsigned int n);
	228
	229	/**
	230	* regs_get_register() - get register value from its offset
	231	* @regs: pt_regs from which register value is gotten
	232	* @offset: offset number of the register.
	233	*
	234	* regs_get_register returns the value of a register whose offset from @regs.
	235	* The @offset is the offset of the register in struct pt_regs.
	236	* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
	237	*/
	238	static inline unsigned long regs_get_register(struct pt_regs *regs,
	239	unsigned int offset)
	240	{
	241	if (unlikely(offset > MAX_REG_OFFSET))
	242	return 0;
	243	return (unsigned long )((unsigned long)regs + offset);
	244	}
	245
	246	/* Valid only for Kernel mode traps. */
	247	static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
	248	{
	249	return regs->ARM_sp;
	250	}
	251
0693bf68 WF	252	static inline unsigned long user_stack_pointer(struct pt_regs *regs)
	253	{
	254	return regs->ARM_sp;
	255	}
	256
bfd170d5 AV	257	#define current_pt_regs(void) ({ \
	258	register unsigned long sp asm ("sp"); \
	259	(struct pt_regs *)((sp \| (THREAD_SIZE - 1)) - 7) - 1; \
	260	})
	261
f22ab814	262	#endif /* __KERNEL__ */
1da177e4 LT	263
	264	#endif /* __ASSEMBLY__ */
	265
	266	#endif
	267