[linux-2.6-block.git] / arch / arm / include / asm / pgtable.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  arch/arm/include/asm/pgtable.h
 *
 *  Copyright (C) 1995-2002 Russell King
 */
#ifndef _ASMARM_PGTABLE_H
#define _ASMARM_PGTABLE_H

#include <linux/const.h>
#include <asm/proc-fns.h>

#ifndef __ASSEMBLY__
/*
 * ZERO_PAGE is a global shared page that is always zero: used
 * for zero-mapped memory areas etc..
 */
extern struct page *empty_zero_page;
#define ZERO_PAGE(vaddr)	(empty_zero_page)
#endif

#ifndef CONFIG_MMU

#include <asm-generic/pgtable-nopud.h>
#include <asm/pgtable-nommu.h>

#else

#include <asm-generic/pgtable-nopud.h>
#include <asm/page.h>
#include <asm/pgtable-hwdef.h>


#include <asm/tlbflush.h>

#ifdef CONFIG_ARM_LPAE
#include <asm/pgtable-3level.h>
#else
#include <asm/pgtable-2level.h>
#endif

/*
 * Just any arbitrary offset to the start of the vmalloc VM area: the
 * current 8MB value just means that there will be a 8MB "hole" after the
 * physical memory until the kernel virtual memory starts.  That means that
 * any out-of-bounds memory accesses will hopefully be caught.
 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 * area for the same reason. ;)
 */
#define VMALLOC_OFFSET		(8*1024*1024)
#define VMALLOC_START		(((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END		0xff800000UL

#define LIBRARY_TEXT_START	0x0c000000

#ifndef __ASSEMBLY__
extern void __pte_error(const char *file, int line, pte_t);
extern void __pmd_error(const char *file, int line, pmd_t);
extern void __pgd_error(const char *file, int line, pgd_t);

#define pte_ERROR(pte)		__pte_error(__FILE__, __LINE__, pte)
#define pmd_ERROR(pmd)		__pmd_error(__FILE__, __LINE__, pmd)
#define pgd_ERROR(pgd)		__pgd_error(__FILE__, __LINE__, pgd)

/*
 * This is the lowest virtual address we can permit any user space
 * mapping to be mapped at.  This is particularly important for
 * non-high vector CPUs.
 */
#define FIRST_USER_ADDRESS	(PAGE_SIZE * 2)

/*
 * Use TASK_SIZE as the ceiling argument for free_pgtables() and
 * free_pgd_range() to avoid freeing the modules pmd when LPAE is enabled (pmd
 * page shared between user and kernel).
 */
#ifdef CONFIG_ARM_LPAE
#define USER_PGTABLES_CEILING	TASK_SIZE
#endif

/*
 * The pgprot_* and protection_map entries will be fixed up in runtime
 * to include the cachable and bufferable bits based on memory policy,
 * as well as any architecture dependent bits like global/ASID and SMP
 * shared mapping bits.
 */
#define _L_PTE_DEFAULT	L_PTE_PRESENT | L_PTE_YOUNG

extern pgprot_t		pgprot_user;
extern pgprot_t		pgprot_kernel;

#define _MOD_PROT(p, b)	__pgprot(pgprot_val(p) | (b))

#define PAGE_NONE		_MOD_PROT(pgprot_user, L_PTE_XN | L_PTE_RDONLY | L_PTE_NONE)
#define PAGE_SHARED		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_XN)
#define PAGE_SHARED_EXEC	_MOD_PROT(pgprot_user, L_PTE_USER)
#define PAGE_COPY		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
#define PAGE_COPY_EXEC		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
#define PAGE_READONLY		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
#define PAGE_READONLY_EXEC	_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
#define PAGE_KERNEL		_MOD_PROT(pgprot_kernel, L_PTE_XN)
#define PAGE_KERNEL_EXEC	pgprot_kernel

#define __PAGE_NONE		__pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
#define __PAGE_SHARED		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
#define __PAGE_SHARED_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER)
#define __PAGE_COPY		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
#define __PAGE_COPY_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
#define __PAGE_READONLY		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
#define __PAGE_READONLY_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)

#define __pgprot_modify(prot,mask,bits)		\
	__pgprot((pgprot_val(prot) & ~(mask)) | (bits))

#define pgprot_noncached(prot) \
	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)

#define pgprot_writecombine(prot) \
	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)

#define pgprot_stronglyordered(prot) \
	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)

#define pgprot_device(prot) \
	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_SHARED | L_PTE_SHARED | L_PTE_DIRTY | L_PTE_XN)

#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
#define pgprot_dmacoherent(prot) \
	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
#define __HAVE_PHYS_MEM_ACCESS_PROT
struct file;
extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
				     unsigned long size, pgprot_t vma_prot);
#else
#define pgprot_dmacoherent(prot) \
	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
#endif

#endif /* __ASSEMBLY__ */

/*
 * The table below defines the page protection levels that we insert into our
 * Linux page table version.  These get translated into the best that the
 * architecture can perform.  Note that on most ARM hardware:
 *  1) We cannot do execute protection
 *  2) If we could do execute protection, then read is implied
 *  3) write implies read permissions
 */

#ifndef __ASSEMBLY__

extern pgd_t swapper_pg_dir[PTRS_PER_PGD];

#define pgdp_get(pgpd)		READ_ONCE(*pgdp)

#define pud_page(pud)		pmd_page(__pmd(pud_val(pud)))
#define pud_write(pud)		pmd_write(__pmd(pud_val(pud)))

#define pmd_none(pmd)		(!pmd_val(pmd))

static inline pte_t *pmd_page_vaddr(pmd_t pmd)
{
	return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
}

#define pmd_page(pmd)		pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))

#define pte_pfn(pte)		((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
#define pfn_pte(pfn,prot)	__pte(__pfn_to_phys(pfn) | pgprot_val(prot))

#define pte_page(pte)		pfn_to_page(pte_pfn(pte))
#define mk_pte(page,prot)	pfn_pte(page_to_pfn(page), prot)

#define pte_clear(mm,addr,ptep)	set_pte_ext(ptep, __pte(0), 0)

#define pte_isset(pte, val)	((u32)(val) == (val) ? pte_val(pte) & (val) \
						: !!(pte_val(pte) & (val)))
#define pte_isclear(pte, val)	(!(pte_val(pte) & (val)))

#define pte_none(pte)		(!pte_val(pte))
#define pte_present(pte)	(pte_isset((pte), L_PTE_PRESENT))
#define pte_valid(pte)		(pte_isset((pte), L_PTE_VALID))
#define pte_accessible(mm, pte)	(mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
#define pte_write(pte)		(pte_isclear((pte), L_PTE_RDONLY))
#define pte_dirty(pte)		(pte_isset((pte), L_PTE_DIRTY))
#define pte_young(pte)		(pte_isset((pte), L_PTE_YOUNG))
#define pte_exec(pte)		(pte_isclear((pte), L_PTE_XN))

#define pte_valid_user(pte)	\
	(pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte))

static inline bool pte_access_permitted(pte_t pte, bool write)
{
	pteval_t mask = L_PTE_PRESENT | L_PTE_USER;
	pteval_t needed = mask;

	if (write)
		mask |= L_PTE_RDONLY;

	return (pte_val(pte) & mask) == needed;
}
#define pte_access_permitted pte_access_permitted

#if __LINUX_ARM_ARCH__ < 6
static inline void __sync_icache_dcache(pte_t pteval)
{
}
#else
extern void __sync_icache_dcache(pte_t pteval);
#endif

#define PFN_PTE_SHIFT		PAGE_SHIFT

void set_ptes(struct mm_struct *mm, unsigned long addr,
		      pte_t *ptep, pte_t pteval, unsigned int nr);
#define set_ptes set_ptes

static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
{
	pte_val(pte) &= ~pgprot_val(prot);
	return pte;
}

static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
{
	pte_val(pte) |= pgprot_val(prot);
	return pte;
}

static inline pte_t pte_wrprotect(pte_t pte)
{
	return set_pte_bit(pte, __pgprot(L_PTE_RDONLY));
}

static inline pte_t pte_mkwrite_novma(pte_t pte)
{
	return clear_pte_bit(pte, __pgprot(L_PTE_RDONLY));
}

static inline pte_t pte_mkclean(pte_t pte)
{
	return clear_pte_bit(pte, __pgprot(L_PTE_DIRTY));
}

static inline pte_t pte_mkdirty(pte_t pte)
{
	return set_pte_bit(pte, __pgprot(L_PTE_DIRTY));
}

static inline pte_t pte_mkold(pte_t pte)
{
	return clear_pte_bit(pte, __pgprot(L_PTE_YOUNG));
}

static inline pte_t pte_mkyoung(pte_t pte)
{
	return set_pte_bit(pte, __pgprot(L_PTE_YOUNG));
}

static inline pte_t pte_mkexec(pte_t pte)
{
	return clear_pte_bit(pte, __pgprot(L_PTE_XN));
}

static inline pte_t pte_mknexec(pte_t pte)
{
	return set_pte_bit(pte, __pgprot(L_PTE_XN));
}

static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
	const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
		L_PTE_NONE | L_PTE_VALID;
	pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
	return pte;
}

/*
 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
 * are !pte_none() && !pte_present().
 *
 * Format of swap PTEs:
 *
 *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 *   <------------------- offset ------------------> E < type -> 0 0
 *
 *   E is the exclusive marker that is not stored in swap entries.
 *
 * This gives us up to 31 swap files and 64GB per swap file.  Note that
 * the offset field is always non-zero.
 */
#define __SWP_TYPE_SHIFT	2
#define __SWP_TYPE_BITS		5
#define __SWP_TYPE_MASK		((1 << __SWP_TYPE_BITS) - 1)
#define __SWP_OFFSET_SHIFT	(__SWP_TYPE_BITS + __SWP_TYPE_SHIFT + 1)

#define __swp_type(x)		(((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
#define __swp_offset(x)		((x).val >> __SWP_OFFSET_SHIFT)
#define __swp_entry(type, offset) ((swp_entry_t) { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \
						   ((offset) << __SWP_OFFSET_SHIFT) })

#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(swp)	__pte((swp).val)

static inline int pte_swp_exclusive(pte_t pte)
{
	return pte_isset(pte, L_PTE_SWP_EXCLUSIVE);
}

static inline pte_t pte_swp_mkexclusive(pte_t pte)
{
	return set_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
}

static inline pte_t pte_swp_clear_exclusive(pte_t pte)
{
	return clear_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
}

/*
 * It is an error for the kernel to have more swap files than we can
 * encode in the PTEs.  This ensures that we know when MAX_SWAPFILES
 * is increased beyond what we presently support.
 */
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)

/*
 * We provide our own arch_get_unmapped_area to cope with VIPT caches.
 */
#define HAVE_ARCH_UNMAPPED_AREA
#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN

#endif /* !__ASSEMBLY__ */

#endif /* CONFIG_MMU */

#endif /* _ASMARM_PGTABLE_H */
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
1da177e4	2	/*
4baa9922	3	* arch/arm/include/asm/pgtable.h
1da177e4 LT	4	*
1da177e4 LT	5	* Copyright (C) 1995-2002 Russell King
1da177e4 LT	6	*/
	7	#ifndef _ASMARM_PGTABLE_H
	8	#define _ASMARM_PGTABLE_H
	9
f6e3354d	10	#include <linux/const.h>
002547b4 RK	11	#include <asm/proc-fns.h>
002547b4 RK	12
340a9828 GB	13	#ifndef __ASSEMBLY__
	14	/*
	15	* ZERO_PAGE is a global shared page that is always zero: used
	16	* for zero-mapped memory areas etc..
	17	*/
	18	extern struct page *empty_zero_page;
	19	#define ZERO_PAGE(vaddr) (empty_zero_page)
	20	#endif
	21
002547b4 RK	22	#ifndef CONFIG_MMU
002547b4 RK	23
aa662823	24	#include <asm-generic/pgtable-nopud.h>
a1ce3928	25	#include <asm/pgtable-nommu.h>
002547b4 RK	26
002547b4 RK	27	#else
1da177e4	28
a32618d2	29	#include <asm-generic/pgtable-nopud.h>
a9ff6961	30	#include <asm/page.h>
ad1ae2fe	31	#include <asm/pgtable-hwdef.h>
1da177e4	32
8d962507 CM	33
	34	#include <asm/tlbflush.h>
	35
dcfdae04 CM	36	#ifdef CONFIG_ARM_LPAE
	37	#include <asm/pgtable-3level.h>
	38	#else
17f57211	39	#include <asm/pgtable-2level.h>
dcfdae04	40	#endif
17f57211	41
5c3073e6 RK	42	/*
	43	* Just any arbitrary offset to the start of the vmalloc VM area: the
	44	* current 8MB value just means that there will be a 8MB "hole" after the
	45	* physical memory until the kernel virtual memory starts. That means that
	46	* any out-of-bounds memory accesses will hopefully be caught.
	47	* The vmalloc() routines leaves a hole of 4kB between each vmalloced
	48	* area for the same reason. ;)
5c3073e6	49	*/
5c3073e6 RK	50	#define VMALLOC_OFFSET (810241024)
5c3073e6 RK	51	#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
6ff09660	52	#define VMALLOC_END 0xff800000UL
5c3073e6	53
1da177e4 LT	54	#define LIBRARY_TEXT_START 0x0c000000
	55
	56	#ifndef __ASSEMBLY__
69529c0e RK	57	extern void __pte_error(const char *file, int line, pte_t);
	58	extern void __pmd_error(const char *file, int line, pmd_t);
	59	extern void __pgd_error(const char *file, int line, pgd_t);
1da177e4	60
69529c0e RK	61	#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte)
	62	#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd)
	63	#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd)
1da177e4	64
6119be0b HD	65	/*
	66	* This is the lowest virtual address we can permit any user space
	67	* mapping to be mapped at. This is particularly important for
	68	* non-high vector CPUs.
	69	*/
d8aa712c	70	#define FIRST_USER_ADDRESS (PAGE_SIZE * 2)
6119be0b	71
104ad3b3 CM	72	/*
	73	* Use TASK_SIZE as the ceiling argument for free_pgtables() and
	74	* free_pgd_range() to avoid freeing the modules pmd when LPAE is enabled (pmd
	75	* page shared between user and kernel).
	76	*/
	77	#ifdef CONFIG_ARM_LPAE
	78	#define USER_PGTABLES_CEILING TASK_SIZE
	79	#endif
	80
1da177e4	81	/*
44b18693 I	82	* The pgprot_* and protection_map entries will be fixed up in runtime
	83	* to include the cachable and bufferable bits based on memory policy,
	84	* as well as any architecture dependent bits like global/ASID and SMP
	85	* shared mapping bits.
1da177e4	86	*/
bb30f36f	87	#define _L_PTE_DEFAULT L_PTE_PRESENT \| L_PTE_YOUNG
1da177e4	88
44b18693	89	extern pgprot_t pgprot_user;
1da177e4 LT	90	extern pgprot_t pgprot_kernel;
1da177e4 LT	91
8ec53663	92	#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) \| (b))
1da177e4	93
26ffd0d4	94	#define PAGE_NONE _MOD_PROT(pgprot_user, L_PTE_XN \| L_PTE_RDONLY \| L_PTE_NONE)
36bb94ba RK	95	#define PAGE_SHARED _MOD_PROT(pgprot_user, L_PTE_USER \| L_PTE_XN)
	96	#define PAGE_SHARED_EXEC _MOD_PROT(pgprot_user, L_PTE_USER)
	97	#define PAGE_COPY _MOD_PROT(pgprot_user, L_PTE_USER \| L_PTE_RDONLY \| L_PTE_XN)
	98	#define PAGE_COPY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER \| L_PTE_RDONLY)
	99	#define PAGE_READONLY _MOD_PROT(pgprot_user, L_PTE_USER \| L_PTE_RDONLY \| L_PTE_XN)
	100	#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER \| L_PTE_RDONLY)
9522d7e4 RK	101	#define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN)
	102	#define PAGE_KERNEL_EXEC pgprot_kernel
	103
26ffd0d4	104	#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT \| L_PTE_RDONLY \| L_PTE_XN \| L_PTE_NONE)
36bb94ba RK	105	#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT \| L_PTE_USER \| L_PTE_XN)
	106	#define __PAGE_SHARED_EXEC __pgprot(_L_PTE_DEFAULT \| L_PTE_USER)
	107	#define __PAGE_COPY __pgprot(_L_PTE_DEFAULT \| L_PTE_USER \| L_PTE_RDONLY \| L_PTE_XN)
	108	#define __PAGE_COPY_EXEC __pgprot(_L_PTE_DEFAULT \| L_PTE_USER \| L_PTE_RDONLY)
	109	#define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT \| L_PTE_USER \| L_PTE_RDONLY \| L_PTE_XN)
	110	#define __PAGE_READONLY_EXEC __pgprot(_L_PTE_DEFAULT \| L_PTE_USER \| L_PTE_RDONLY)
44b18693	111
eb9b2b69 RK	112	#define __pgprot_modify(prot,mask,bits) \
	113	__pgprot((pgprot_val(prot) & ~(mask)) \| (bits))
	114
	115	#define pgprot_noncached(prot) \
	116	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
	117
	118	#define pgprot_writecombine(prot) \
	119	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
	120
8fb54284 SS	121	#define pgprot_stronglyordered(prot) \
	122	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
	123
58ca3382 VW	124	#define pgprot_device(prot) \
	125	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_SHARED \| L_PTE_SHARED \| L_PTE_DIRTY \| L_PTE_XN)
	126
eb9b2b69 RK	127	#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
eb9b2b69 RK	128	#define pgprot_dmacoherent(prot) \
9522d7e4	129	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE \| L_PTE_XN)
eb9b2b69 RK	130	#define __HAVE_PHYS_MEM_ACCESS_PROT
	131	struct file;
	132	extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
	133	unsigned long size, pgprot_t vma_prot);
	134	#else
	135	#define pgprot_dmacoherent(prot) \
9522d7e4	136	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED \| L_PTE_XN)
eb9b2b69 RK	137	#endif
eb9b2b69 RK	138
1da177e4 LT	139	#endif /* __ASSEMBLY__ */
	140
	141	/*
	142	* The table below defines the page protection levels that we insert into our
	143	* Linux page table version. These get translated into the best that the
	144	* architecture can perform. Note that on most ARM hardware:
	145	* 1) We cannot do execute protection
	146	* 2) If we could do execute protection, then read is implied
	147	* 3) write implies read permissions
	148	*/
1da177e4 LT	149
1da177e4 LT	150	#ifndef __ASSEMBLY__
4eec4b13 RK	151
	152	extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
	153
eba2591d AG	154	#define pgdp_get(pgpd) READ_ONCE(*pgdp)
eba2591d AG	155
972472c7 NP	156	#define pud_page(pud) pmd_page(__pmd(pud_val(pud)))
	157	#define pud_write(pud) pmd_write(__pmd(pud_val(pud)))
	158
b510b049	159	#define pmd_none(pmd) (!pmd_val(pmd))
b510b049 RK	160
	161	static inline pte_t *pmd_page_vaddr(pmd_t pmd)
	162	{
d7c5d0dc	163	return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
b510b049 RK	164	}
b510b049 RK	165
d7c5d0dc	166	#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
b510b049	167
d7c5d0dc	168	#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
cae6292b	169	#define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) \| pgprot_val(prot))
b510b049 RK	170
	171	#define pte_page(pte) pfn_to_page(pte_pfn(pte))
	172	#define mk_pte(page,prot) pfn_pte(page_to_pfn(page), prot)
	173
b510b049	174	#define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
ad1ae2fe	175
f2950706 SC	176	#define pte_isset(pte, val) ((u32)(val) == (val) ? pte_val(pte) & (val) \
	177	: !!(pte_val(pte) & (val)))
	178	#define pte_isclear(pte, val) (!(pte_val(pte) & (val)))
	179
47f12043	180	#define pte_none(pte) (!pte_val(pte))
f2950706 SC	181	#define pte_present(pte) (pte_isset((pte), L_PTE_PRESENT))
f2950706 SC	182	#define pte_valid(pte) (pte_isset((pte), L_PTE_VALID))
1971188a	183	#define pte_accessible(mm, pte) (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
f2950706 SC	184	#define pte_write(pte) (pte_isclear((pte), L_PTE_RDONLY))
	185	#define pte_dirty(pte) (pte_isset((pte), L_PTE_DIRTY))
	186	#define pte_young(pte) (pte_isset((pte), L_PTE_YOUNG))
	187	#define pte_exec(pte) (pte_isclear((pte), L_PTE_XN))
47f12043	188
1971188a	189	#define pte_valid_user(pte) \
f2950706	190	(pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte))
47f12043	191
1ee5e87f RK	192	static inline bool pte_access_permitted(pte_t pte, bool write)
	193	{
	194	pteval_t mask = L_PTE_PRESENT \| L_PTE_USER;
	195	pteval_t needed = mask;
	196
	197	if (write)
	198	mask \|= L_PTE_RDONLY;
	199
	200	return (pte_val(pte) & mask) == needed;
	201	}
	202	#define pte_access_permitted pte_access_permitted
	203
6012191a CM	204	#if __LINUX_ARM_ARCH__ < 6
	205	static inline void __sync_icache_dcache(pte_t pteval)
	206	{
	207	}
	208	#else
	209	extern void __sync_icache_dcache(pte_t pteval);
	210	#endif
	211
12b884f2 DH	212	#define PFN_PTE_SHIFT PAGE_SHIFT
12b884f2 DH	213
8b5989f3 MWO	214	void set_ptes(struct mm_struct *mm, unsigned long addr,
	215	pte_t *ptep, pte_t pteval, unsigned int nr);
	216	#define set_ptes set_ptes
6012191a	217
1f92f77a JL	218	static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
	219	{
	220	pte_val(pte) &= ~pgprot_val(prot);
	221	return pte;
	222	}
	223
	224	static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
	225	{
	226	pte_val(pte) \|= pgprot_val(prot);
	227	return pte;
	228	}
	229
	230	static inline pte_t pte_wrprotect(pte_t pte)
	231	{
	232	return set_pte_bit(pte, __pgprot(L_PTE_RDONLY));
	233	}
	234
2f0584f3	235	static inline pte_t pte_mkwrite_novma(pte_t pte)
1f92f77a JL	236	{
	237	return clear_pte_bit(pte, __pgprot(L_PTE_RDONLY));
	238	}
	239
	240	static inline pte_t pte_mkclean(pte_t pte)
	241	{
	242	return clear_pte_bit(pte, __pgprot(L_PTE_DIRTY));
	243	}
	244
	245	static inline pte_t pte_mkdirty(pte_t pte)
	246	{
	247	return set_pte_bit(pte, __pgprot(L_PTE_DIRTY));
	248	}
	249
	250	static inline pte_t pte_mkold(pte_t pte)
	251	{
	252	return clear_pte_bit(pte, __pgprot(L_PTE_YOUNG));
	253	}
	254
	255	static inline pte_t pte_mkyoung(pte_t pte)
	256	{
	257	return set_pte_bit(pte, __pgprot(L_PTE_YOUNG));
	258	}
	259
	260	static inline pte_t pte_mkexec(pte_t pte)
	261	{
	262	return clear_pte_bit(pte, __pgprot(L_PTE_XN));
	263	}
	264
	265	static inline pte_t pte_mknexec(pte_t pte)
	266	{
	267	return set_pte_bit(pte, __pgprot(L_PTE_XN));
	268	}
1da177e4	269
1da177e4 LT	270	static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4 LT	271	{
69dde4c5 CM	272	const pteval_t mask = L_PTE_XN \| L_PTE_RDONLY \| L_PTE_USER \|
69dde4c5 CM	273	L_PTE_NONE \| L_PTE_VALID;
1da177e4 LT	274	pte_val(pte) = (pte_val(pte) & ~mask) \| (pgprot_val(newprot) & mask);
	275	return pte;
	276	}
	277
fb93a1c7	278	/*
20aae9ef DH	279	* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
	280	* are !pte_none() && !pte_present().
	281	*
	282	* Format of swap PTEs:
fb93a1c7 RK	283	*
	284	* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
	285	* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
20aae9ef DH	286	* <------------------- offset ------------------> E < type -> 0 0
	287	*
	288	* E is the exclusive marker that is not stored in swap entries.
1da177e4	289	*
20aae9ef	290	* This gives us up to 31 swap files and 64GB per swap file. Note that
fb93a1c7	291	* the offset field is always non-zero.
1da177e4	292	*/
b007ea79	293	#define __SWP_TYPE_SHIFT 2
f5f2025e	294	#define __SWP_TYPE_BITS 5
fb93a1c7	295	#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
20aae9ef	296	#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT + 1)
fb93a1c7 RK	297
	298	#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
	299	#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
6f74c0ec	300	#define __swp_entry(type, offset) ((swp_entry_t) { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) \| \
20aae9ef	301	((offset) << __SWP_OFFSET_SHIFT) })
fb93a1c7	302
1da177e4	303	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
20aae9ef DH	304	#define __swp_entry_to_pte(swp) __pte((swp).val)
20aae9ef DH	305
20aae9ef DH	306	static inline int pte_swp_exclusive(pte_t pte)
	307	{
	308	return pte_isset(pte, L_PTE_SWP_EXCLUSIVE);
	309	}
	310
	311	static inline pte_t pte_swp_mkexclusive(pte_t pte)
	312	{
	313	return set_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
	314	}
	315
	316	static inline pte_t pte_swp_clear_exclusive(pte_t pte)
	317	{
	318	return clear_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
	319	}
1da177e4	320
fb93a1c7 RK	321	/*
	322	* It is an error for the kernel to have more swap files than we can
	323	* encode in the PTEs. This ensures that we know when MAX_SWAPFILES
	324	* is increased beyond what we presently support.
	325	*/
	326	#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
	327
1da177e4 LT	328	/*
	329	* We provide our own arch_get_unmapped_area to cope with VIPT caches.
	330	*/
	331	#define HAVE_ARCH_UNMAPPED_AREA
7dbaa466	332	#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
1da177e4	333
1da177e4 LT	334	#endif /* !__ASSEMBLY__ */
1da177e4 LT	335
002547b4 RK	336	#endif /* CONFIG_MMU */
002547b4 RK	337
1da177e4	338	#endif /* _ASMARM_PGTABLE_H */