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0c9030de LL |
1 | /* |
2 | * arch/arm/include/asm/opcodes.h | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef __ASM_ARM_OPCODES_H | |
10 | #define __ASM_ARM_OPCODES_H | |
11 | ||
12 | #ifndef __ASSEMBLY__ | |
13 | extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); | |
14 | #endif | |
15 | ||
16 | #define ARM_OPCODE_CONDTEST_FAIL 0 | |
17 | #define ARM_OPCODE_CONDTEST_PASS 1 | |
18 | #define ARM_OPCODE_CONDTEST_UNCOND 2 | |
19 | ||
f5f51954 | 20 | |
0ce3de23 DM |
21 | /* |
22 | * Assembler opcode byteswap helpers. | |
23 | * These are only intended for use by this header: don't use them directly, | |
24 | * because they will be suboptimal in most cases. | |
25 | */ | |
26 | #define ___asm_opcode_swab32(x) ( \ | |
27 | (((x) << 24) & 0xFF000000) \ | |
28 | | (((x) << 8) & 0x00FF0000) \ | |
29 | | (((x) >> 8) & 0x0000FF00) \ | |
30 | | (((x) >> 24) & 0x000000FF) \ | |
31 | ) | |
32 | #define ___asm_opcode_swab16(x) ( \ | |
33 | (((x) << 8) & 0xFF00) \ | |
34 | | (((x) >> 8) & 0x00FF) \ | |
35 | ) | |
36 | #define ___asm_opcode_swahb32(x) ( \ | |
37 | (((x) << 8) & 0xFF00FF00) \ | |
38 | | (((x) >> 8) & 0x00FF00FF) \ | |
39 | ) | |
40 | #define ___asm_opcode_swahw32(x) ( \ | |
41 | (((x) << 16) & 0xFFFF0000) \ | |
42 | | (((x) >> 16) & 0x0000FFFF) \ | |
43 | ) | |
44 | #define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF) | |
45 | #define ___asm_opcode_identity16(x) ((x) & 0xFFFF) | |
46 | ||
47 | ||
f5f51954 DM |
48 | /* |
49 | * Opcode byteswap helpers | |
50 | * | |
51 | * These macros help with converting instructions between a canonical integer | |
52 | * format and in-memory representation, in an endianness-agnostic manner. | |
53 | * | |
54 | * __mem_to_opcode_*() convert from in-memory representation to canonical form. | |
55 | * __opcode_to_mem_*() convert from canonical form to in-memory representation. | |
56 | * | |
57 | * | |
58 | * Canonical instruction representation: | |
59 | * | |
60 | * ARM: 0xKKLLMMNN | |
61 | * Thumb 16-bit: 0x0000KKLL, where KK < 0xE8 | |
62 | * Thumb 32-bit: 0xKKLLMMNN, where KK >= 0xE8 | |
63 | * | |
64 | * There is no way to distinguish an ARM instruction in canonical representation | |
65 | * from a Thumb instruction (just as these cannot be distinguished in memory). | |
66 | * Where this distinction is important, it needs to be tracked separately. | |
67 | * | |
68 | * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not | |
69 | * represent any valid Thumb-2 instruction. For this range, | |
70 | * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false. | |
0ce3de23 DM |
71 | * |
72 | * The ___asm variants are intended only for use by this header, in situations | |
73 | * involving inline assembler. For .S files, the normal __opcode_*() macros | |
74 | * should do the right thing. | |
f5f51954 | 75 | */ |
0ce3de23 | 76 | #ifdef __ASSEMBLY__ |
f5f51954 | 77 | |
0ce3de23 DM |
78 | #define ___opcode_swab32(x) ___asm_opcode_swab32(x) |
79 | #define ___opcode_swab16(x) ___asm_opcode_swab16(x) | |
80 | #define ___opcode_swahb32(x) ___asm_opcode_swahb32(x) | |
81 | #define ___opcode_swahw32(x) ___asm_opcode_swahw32(x) | |
82 | #define ___opcode_identity32(x) ___asm_opcode_identity32(x) | |
83 | #define ___opcode_identity16(x) ___asm_opcode_identity16(x) | |
84 | ||
85 | #else /* ! __ASSEMBLY__ */ | |
f5f51954 DM |
86 | |
87 | #include <linux/types.h> | |
88 | #include <linux/swab.h> | |
89 | ||
0ce3de23 DM |
90 | #define ___opcode_swab32(x) swab32(x) |
91 | #define ___opcode_swab16(x) swab16(x) | |
92 | #define ___opcode_swahb32(x) swahb32(x) | |
93 | #define ___opcode_swahw32(x) swahw32(x) | |
94 | #define ___opcode_identity32(x) ((u32)(x)) | |
95 | #define ___opcode_identity16(x) ((u16)(x)) | |
96 | ||
97 | #endif /* ! __ASSEMBLY__ */ | |
98 | ||
99 | ||
f5f51954 | 100 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
57b9da32 | 101 | |
0ce3de23 DM |
102 | #define __opcode_to_mem_arm(x) ___opcode_swab32(x) |
103 | #define __opcode_to_mem_thumb16(x) ___opcode_swab16(x) | |
104 | #define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x) | |
105 | #define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x) | |
106 | #define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x) | |
107 | #define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x) | |
57b9da32 DM |
108 | |
109 | #else /* ! CONFIG_CPU_ENDIAN_BE8 */ | |
110 | ||
0ce3de23 DM |
111 | #define __opcode_to_mem_arm(x) ___opcode_identity32(x) |
112 | #define __opcode_to_mem_thumb16(x) ___opcode_identity16(x) | |
113 | #define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x) | |
114 | #define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x) | |
57b9da32 DM |
115 | #ifndef CONFIG_CPU_ENDIAN_BE32 |
116 | /* | |
117 | * On BE32 systems, using 32-bit accesses to store Thumb instructions will not | |
118 | * work in all cases, due to alignment constraints. For now, a correct | |
119 | * version is not provided for BE32. | |
120 | */ | |
0ce3de23 DM |
121 | #define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x) |
122 | #define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x) | |
f5f51954 DM |
123 | #endif |
124 | ||
57b9da32 DM |
125 | #endif /* ! CONFIG_CPU_ENDIAN_BE8 */ |
126 | ||
f5f51954 DM |
127 | #define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x) |
128 | #define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x) | |
57b9da32 | 129 | #ifndef CONFIG_CPU_ENDIAN_BE32 |
f5f51954 | 130 | #define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x) |
57b9da32 | 131 | #endif |
f5f51954 DM |
132 | |
133 | /* Operations specific to Thumb opcodes */ | |
134 | ||
135 | /* Instruction size checks: */ | |
0ce3de23 DM |
136 | #define __opcode_is_thumb32(x) ( \ |
137 | ((x) & 0xF8000000) == 0xE8000000 \ | |
138 | || ((x) & 0xF0000000) == 0xF0000000 \ | |
139 | ) | |
140 | #define __opcode_is_thumb16(x) ( \ | |
141 | ((x) & 0xFFFF0000) == 0 \ | |
142 | && !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000) \ | |
143 | ) | |
f5f51954 DM |
144 | |
145 | /* Operations to construct or split 32-bit Thumb instructions: */ | |
0ce3de23 DM |
146 | #define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16)) |
147 | #define __opcode_thumb32_second(x) (___opcode_identity16(x)) | |
148 | #define __opcode_thumb32_compose(first, second) ( \ | |
149 | (___opcode_identity32(___opcode_identity16(first)) << 16) \ | |
150 | | ___opcode_identity32(___opcode_identity16(second)) \ | |
151 | ) | |
152 | #define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16)) | |
153 | #define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x)) | |
154 | #define ___asm_opcode_thumb32_compose(first, second) ( \ | |
155 | (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \ | |
156 | | ___asm_opcode_identity32(___asm_opcode_identity16(second)) \ | |
157 | ) | |
f5f51954 | 158 | |
a61a41a0 DM |
159 | /* |
160 | * Opcode injection helpers | |
161 | * | |
162 | * In rare cases it is necessary to assemble an opcode which the | |
163 | * assembler does not support directly, or which would normally be | |
164 | * rejected because of the CFLAGS or AFLAGS used to build the affected | |
165 | * file. | |
166 | * | |
167 | * Before using these macros, consider carefully whether it is feasible | |
168 | * instead to change the build flags for your file, or whether it really | |
169 | * makes sense to support old assembler versions when building that | |
170 | * particular kernel feature. | |
171 | * | |
172 | * The macros defined here should only be used where there is no viable | |
173 | * alternative. | |
174 | * | |
175 | * | |
176 | * __inst_arm(x): emit the specified ARM opcode | |
177 | * __inst_thumb16(x): emit the specified 16-bit Thumb opcode | |
178 | * __inst_thumb32(x): emit the specified 32-bit Thumb opcode | |
179 | * | |
180 | * __inst_arm_thumb16(arm, thumb): emit either the specified arm or | |
181 | * 16-bit Thumb opcode, depending on whether an ARM or Thumb-2 | |
182 | * kernel is being built | |
183 | * | |
184 | * __inst_arm_thumb32(arm, thumb): emit either the specified arm or | |
185 | * 32-bit Thumb opcode, depending on whether an ARM or Thumb-2 | |
186 | * kernel is being built | |
187 | * | |
188 | * | |
189 | * Note that using these macros directly is poor practice. Instead, you | |
190 | * should use them to define human-readable wrapper macros to encode the | |
191 | * instructions that you care about. In code which might run on ARMv7 or | |
192 | * above, you can usually use the __inst_arm_thumb{16,32} macros to | |
193 | * specify the ARM and Thumb alternatives at the same time. This ensures | |
194 | * that the correct opcode gets emitted depending on the instruction set | |
195 | * used for the kernel build. | |
508514ed DM |
196 | * |
197 | * Look at opcodes-virt.h for an example of how to use these macros. | |
a61a41a0 DM |
198 | */ |
199 | #include <linux/stringify.h> | |
200 | ||
201 | #define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x)) | |
202 | #define __inst_thumb32(x) ___inst_thumb32( \ | |
203 | ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)), \ | |
204 | ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x)) \ | |
205 | ) | |
206 | #define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x)) | |
207 | ||
208 | #ifdef CONFIG_THUMB2_KERNEL | |
209 | #define __inst_arm_thumb16(arm_opcode, thumb_opcode) \ | |
210 | __inst_thumb16(thumb_opcode) | |
211 | #define __inst_arm_thumb32(arm_opcode, thumb_opcode) \ | |
212 | __inst_thumb32(thumb_opcode) | |
213 | #else | |
214 | #define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode) | |
215 | #define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode) | |
216 | #endif | |
217 | ||
218 | /* Helpers for the helpers. Don't use these directly. */ | |
219 | #ifdef __ASSEMBLY__ | |
220 | #define ___inst_arm(x) .long x | |
221 | #define ___inst_thumb16(x) .short x | |
222 | #define ___inst_thumb32(first, second) .short first, second | |
223 | #else | |
224 | #define ___inst_arm(x) ".long " __stringify(x) "\n\t" | |
225 | #define ___inst_thumb16(x) ".short " __stringify(x) "\n\t" | |
226 | #define ___inst_thumb32(first, second) \ | |
227 | ".short " __stringify(first) ", " __stringify(second) "\n\t" | |
228 | #endif | |
229 | ||
0c9030de | 230 | #endif /* __ASM_ARM_OPCODES_H */ |