projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 342cd0ab CD |
1 | /* |
| 2 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
| 3 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License, version 2, as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License | |
| 15 | * along with this program; if not, write to the Free Software | |
| 16 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
| 17 | */ | |
| 18 | ||
| 19 | #ifndef __ARM_KVM_MMU_H__ | |
| 20 | #define __ARM_KVM_MMU_H__ | |
| 21 | ||
| c62ee2b2 MZ |
22 | #include <asm/cacheflush.h> |
| 23 | #include <asm/pgalloc.h> | |
| 24 | ||
| 06e8c3b0 MZ |
25 | /* |
| 26 | * We directly use the kernel VA for the HYP, as we can directly share | |
| 27 | * the mapping (HTTBR "covers" TTBR1). | |
| 28 | */ | |
| 29 | #define HYP_PAGE_OFFSET_MASK (~0UL) | |
| 30 | #define HYP_PAGE_OFFSET PAGE_OFFSET | |
| 31 | #define KERN_TO_HYP(kva) (kva) | |
| 32 | ||
| 342cd0ab CD |
33 | int create_hyp_mappings(void *from, void *to); |
| 34 | int create_hyp_io_mappings(void *from, void *to, phys_addr_t); | |
| 35 | void free_hyp_pmds(void); | |
| 36 | ||
| d5d8184d CD |
37 | int kvm_alloc_stage2_pgd(struct kvm *kvm); |
| 38 | void kvm_free_stage2_pgd(struct kvm *kvm); | |
| 39 | int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, | |
| 40 | phys_addr_t pa, unsigned long size); | |
| 41 | ||
| 42 | int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run); | |
| 43 | ||
| 44 | void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu); | |
| 45 | ||
| 342cd0ab CD |
46 | phys_addr_t kvm_mmu_get_httbr(void); |
| 47 | int kvm_mmu_init(void); | |
| 48 | void kvm_clear_hyp_idmap(void); | |
| 94f8e641 | 49 | |
| c62ee2b2 MZ |
50 | static inline void kvm_set_pte(pte_t *pte, pte_t new_pte) |
| 51 | { | |
| 52 | pte_val(*pte) = new_pte; | |
| 53 | /* | |
| 54 | * flush_pmd_entry just takes a void pointer and cleans the necessary | |
| 55 | * cache entries, so we can reuse the function for ptes. | |
| 56 | */ | |
| 57 | flush_pmd_entry(pte); | |
| 58 | } | |
| 59 | ||
| 94f8e641 CD |
60 | static inline bool kvm_is_write_fault(unsigned long hsr) |
| 61 | { | |
| 62 | unsigned long hsr_ec = hsr >> HSR_EC_SHIFT; | |
| 63 | if (hsr_ec == HSR_EC_IABT) | |
| 64 | return false; | |
| 65 | else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR)) | |
| 66 | return false; | |
| 67 | else | |
| 68 | return true; | |
| 69 | } | |
| 70 | ||
| c62ee2b2 MZ |
71 | static inline void kvm_clean_pgd(pgd_t *pgd) |
| 72 | { | |
| 73 | clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t)); | |
| 74 | } | |
| 75 | ||
| 76 | static inline void kvm_clean_pmd_entry(pmd_t *pmd) | |
| 77 | { | |
| 78 | clean_pmd_entry(pmd); | |
| 79 | } | |
| 80 | ||
| 81 | static inline void kvm_clean_pte(pte_t *pte) | |
| 82 | { | |
| 83 | clean_pte_table(pte); | |
| 84 | } | |
| 85 | ||
| 86 | static inline void kvm_set_s2pte_writable(pte_t *pte) | |
| 87 | { | |
| 88 | pte_val(*pte) |= L_PTE_S2_RDWR; | |
| 89 | } | |
| 90 | ||
| 91 | struct kvm; | |
| 92 | ||
| 93 | static inline void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn) | |
| 94 | { | |
| 95 | /* | |
| 96 | * If we are going to insert an instruction page and the icache is | |
| 97 | * either VIPT or PIPT, there is a potential problem where the host | |
| 98 | * (or another VM) may have used the same page as this guest, and we | |
| 99 | * read incorrect data from the icache. If we're using a PIPT cache, | |
| 100 | * we can invalidate just that page, but if we are using a VIPT cache | |
| 101 | * we need to invalidate the entire icache - damn shame - as written | |
| 102 | * in the ARM ARM (DDI 0406C.b - Page B3-1393). | |
| 103 | * | |
| 104 | * VIVT caches are tagged using both the ASID and the VMID and doesn't | |
| 105 | * need any kind of flushing (DDI 0406C.b - Page B3-1392). | |
| 106 | */ | |
| 107 | if (icache_is_pipt()) { | |
| 108 | unsigned long hva = gfn_to_hva(kvm, gfn); | |
| 109 | __cpuc_coherent_user_range(hva, hva + PAGE_SIZE); | |
| 110 | } else if (!icache_is_vivt_asid_tagged()) { | |
| 111 | /* any kind of VIPT cache */ | |
| 112 | __flush_icache_all(); | |
| 113 | } | |
| 114 | } | |
| 115 | ||
| 342cd0ab | 116 | #endif /* __ARM_KVM_MMU_H__ */ |