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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
9f97da78 DH |
2 | #ifndef __ASM_BARRIER_H |
3 | #define __ASM_BARRIER_H | |
4 | ||
5 | #ifndef __ASSEMBLY__ | |
6 | ||
7 | #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); | |
8 | ||
9 | #if __LINUX_ARM_ARCH__ >= 7 || \ | |
10 | (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K)) | |
11 | #define sev() __asm__ __volatile__ ("sev" : : : "memory") | |
12 | #define wfe() __asm__ __volatile__ ("wfe" : : : "memory") | |
13 | #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") | |
14 | #endif | |
15 | ||
16 | #if __LINUX_ARM_ARCH__ >= 7 | |
3ea12806 WD |
17 | #define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory") |
18 | #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") | |
19 | #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory") | |
a78d1565 RK |
20 | #ifdef CONFIG_THUMB2_KERNEL |
21 | #define CSDB ".inst.w 0xf3af8014" | |
22 | #else | |
23 | #define CSDB ".inst 0xe320f014" | |
24 | #endif | |
25 | #define csdb() __asm__ __volatile__(CSDB : : : "memory") | |
9f97da78 | 26 | #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 |
3ea12806 | 27 | #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ |
9f97da78 | 28 | : : "r" (0) : "memory") |
3ea12806 | 29 | #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ |
9f97da78 | 30 | : : "r" (0) : "memory") |
3ea12806 | 31 | #define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ |
9f97da78 DH |
32 | : : "r" (0) : "memory") |
33 | #elif defined(CONFIG_CPU_FA526) | |
3ea12806 | 34 | #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ |
9f97da78 | 35 | : : "r" (0) : "memory") |
3ea12806 | 36 | #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ |
9f97da78 | 37 | : : "r" (0) : "memory") |
3ea12806 | 38 | #define dmb(x) __asm__ __volatile__ ("" : : : "memory") |
9f97da78 | 39 | #else |
3ea12806 WD |
40 | #define isb(x) __asm__ __volatile__ ("" : : : "memory") |
41 | #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ | |
9f97da78 | 42 | : : "r" (0) : "memory") |
3ea12806 | 43 | #define dmb(x) __asm__ __volatile__ ("" : : : "memory") |
9f97da78 DH |
44 | #endif |
45 | ||
a78d1565 RK |
46 | #ifndef CSDB |
47 | #define CSDB | |
48 | #endif | |
49 | #ifndef csdb | |
50 | #define csdb() | |
51 | #endif | |
52 | ||
f8130906 | 53 | #ifdef CONFIG_ARM_HEAVY_MB |
4e1f8a6f | 54 | extern void (*soc_mb)(void); |
f8130906 RK |
55 | extern void arm_heavy_mb(void); |
56 | #define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0) | |
57 | #else | |
58 | #define __arm_heavy_mb(x...) dsb(x) | |
59 | #endif | |
60 | ||
520319de | 61 | #if defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP) |
f8130906 | 62 | #define mb() __arm_heavy_mb() |
9f97da78 | 63 | #define rmb() dsb() |
f8130906 | 64 | #define wmb() __arm_heavy_mb(st) |
1077fa36 AD |
65 | #define dma_rmb() dmb(osh) |
66 | #define dma_wmb() dmb(oshst) | |
9f97da78 | 67 | #else |
48aa820f RH |
68 | #define mb() barrier() |
69 | #define rmb() barrier() | |
70 | #define wmb() barrier() | |
1077fa36 AD |
71 | #define dma_rmb() barrier() |
72 | #define dma_wmb() barrier() | |
9f97da78 DH |
73 | #endif |
74 | ||
2b1f3de1 MT |
75 | #define __smp_mb() dmb(ish) |
76 | #define __smp_rmb() __smp_mb() | |
77 | #define __smp_wmb() dmb(ishst) | |
9f97da78 | 78 | |
1d4238c5 RK |
79 | #ifdef CONFIG_CPU_SPECTRE |
80 | static inline unsigned long array_index_mask_nospec(unsigned long idx, | |
81 | unsigned long sz) | |
82 | { | |
83 | unsigned long mask; | |
84 | ||
85 | asm volatile( | |
86 | "cmp %1, %2\n" | |
87 | " sbc %0, %1, %1\n" | |
88 | CSDB | |
89 | : "=r" (mask) | |
90 | : "r" (idx), "Ir" (sz) | |
91 | : "cc"); | |
92 | ||
93 | return mask; | |
94 | } | |
95 | #define array_index_mask_nospec array_index_mask_nospec | |
96 | #endif | |
97 | ||
335390d6 | 98 | #include <asm-generic/barrier.h> |
030d0178 | 99 | |
9f97da78 DH |
100 | #endif /* !__ASSEMBLY__ */ |
101 | #endif /* __ASM_BARRIER_H */ |