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fa0fe48f RK |
1 | /* |
2 | * linux/arch/arm/common/vic.c | |
3 | * | |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | #include <linux/init.h> | |
22 | #include <linux/list.h> | |
23 | ||
24 | #include <asm/io.h> | |
25 | #include <asm/irq.h> | |
26 | #include <asm/mach/irq.h> | |
27 | #include <asm/hardware/vic.h> | |
28 | ||
29 | static void __iomem *vic_base; | |
30 | ||
31 | static void vic_mask_irq(unsigned int irq) | |
32 | { | |
33 | irq -= IRQ_VIC_START; | |
34 | writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR); | |
35 | } | |
36 | ||
37 | static void vic_unmask_irq(unsigned int irq) | |
38 | { | |
39 | irq -= IRQ_VIC_START; | |
40 | writel(1 << irq, vic_base + VIC_INT_ENABLE); | |
41 | } | |
42 | ||
43 | static struct irqchip vic_chip = { | |
44 | .ack = vic_mask_irq, | |
45 | .mask = vic_mask_irq, | |
46 | .unmask = vic_unmask_irq, | |
47 | }; | |
48 | ||
49 | void __init vic_init(void __iomem *base, u32 vic_sources) | |
50 | { | |
51 | unsigned int i; | |
52 | ||
53 | vic_base = base; | |
54 | ||
55 | /* Disable all interrupts initially. */ | |
56 | ||
57 | writel(0, vic_base + VIC_INT_SELECT); | |
58 | writel(0, vic_base + VIC_INT_ENABLE); | |
59 | writel(~0, vic_base + VIC_INT_ENABLE_CLEAR); | |
60 | writel(0, vic_base + VIC_IRQ_STATUS); | |
61 | writel(0, vic_base + VIC_ITCR); | |
62 | writel(~0, vic_base + VIC_INT_SOFT_CLEAR); | |
63 | ||
64 | /* | |
65 | * Make sure we clear all existing interrupts | |
66 | */ | |
67 | writel(0, vic_base + VIC_VECT_ADDR); | |
68 | for (i = 0; i < 19; i++) { | |
69 | unsigned int value; | |
70 | ||
71 | value = readl(vic_base + VIC_VECT_ADDR); | |
72 | writel(value, vic_base + VIC_VECT_ADDR); | |
73 | } | |
74 | ||
75 | for (i = 0; i < 16; i++) { | |
76 | void __iomem *reg = vic_base + VIC_VECT_CNTL0 + (i * 4); | |
77 | writel(VIC_VECT_CNTL_ENABLE | i, reg); | |
78 | } | |
79 | ||
80 | writel(32, vic_base + VIC_DEF_VECT_ADDR); | |
81 | ||
82 | for (i = 0; i < 32; i++) { | |
83 | unsigned int irq = IRQ_VIC_START + i; | |
84 | ||
85 | set_irq_chip(irq, &vic_chip); | |
86 | ||
87 | if (vic_sources & (1 << i)) { | |
88 | set_irq_handler(irq, do_level_IRQ); | |
89 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
90 | } | |
91 | } | |
92 | } |