Commit | Line | Data |
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1da177e4 | 1 | /* |
f30c2269 | 2 | * linux/arch/arm/common/sa1111.c |
1da177e4 LT |
3 | * |
4 | * SA1111 support | |
5 | * | |
6 | * Original code by John Dorsey | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This file contains all generic SA1111 support. | |
13 | * | |
14 | * All initialization functions provided here are intended to be called | |
15 | * from machine specific code with proper arguments when required. | |
16 | */ | |
1da177e4 LT |
17 | #include <linux/module.h> |
18 | #include <linux/init.h> | |
36d31213 | 19 | #include <linux/irq.h> |
1da177e4 LT |
20 | #include <linux/kernel.h> |
21 | #include <linux/delay.h> | |
1da177e4 LT |
22 | #include <linux/errno.h> |
23 | #include <linux/ioport.h> | |
d052d1be | 24 | #include <linux/platform_device.h> |
1da177e4 LT |
25 | #include <linux/slab.h> |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/dma-mapping.h> | |
97d654f8 | 28 | #include <linux/clk.h> |
fced80c7 | 29 | #include <linux/io.h> |
1da177e4 | 30 | |
a09e64fb | 31 | #include <mach/hardware.h> |
1da177e4 | 32 | #include <asm/mach/irq.h> |
36d31213 | 33 | #include <asm/mach-types.h> |
45e109d0 | 34 | #include <asm/sizes.h> |
1da177e4 LT |
35 | |
36 | #include <asm/hardware/sa1111.h> | |
37 | ||
19851c58 EM |
38 | /* SA1111 IRQs */ |
39 | #define IRQ_GPAIN0 (0) | |
40 | #define IRQ_GPAIN1 (1) | |
41 | #define IRQ_GPAIN2 (2) | |
42 | #define IRQ_GPAIN3 (3) | |
43 | #define IRQ_GPBIN0 (4) | |
44 | #define IRQ_GPBIN1 (5) | |
45 | #define IRQ_GPBIN2 (6) | |
46 | #define IRQ_GPBIN3 (7) | |
47 | #define IRQ_GPBIN4 (8) | |
48 | #define IRQ_GPBIN5 (9) | |
49 | #define IRQ_GPCIN0 (10) | |
50 | #define IRQ_GPCIN1 (11) | |
51 | #define IRQ_GPCIN2 (12) | |
52 | #define IRQ_GPCIN3 (13) | |
53 | #define IRQ_GPCIN4 (14) | |
54 | #define IRQ_GPCIN5 (15) | |
55 | #define IRQ_GPCIN6 (16) | |
56 | #define IRQ_GPCIN7 (17) | |
57 | #define IRQ_MSTXINT (18) | |
58 | #define IRQ_MSRXINT (19) | |
59 | #define IRQ_MSSTOPERRINT (20) | |
60 | #define IRQ_TPTXINT (21) | |
61 | #define IRQ_TPRXINT (22) | |
62 | #define IRQ_TPSTOPERRINT (23) | |
63 | #define SSPXMTINT (24) | |
64 | #define SSPRCVINT (25) | |
65 | #define SSPROR (26) | |
66 | #define AUDXMTDMADONEA (32) | |
67 | #define AUDRCVDMADONEA (33) | |
68 | #define AUDXMTDMADONEB (34) | |
69 | #define AUDRCVDMADONEB (35) | |
70 | #define AUDTFSR (36) | |
71 | #define AUDRFSR (37) | |
72 | #define AUDTUR (38) | |
73 | #define AUDROR (39) | |
74 | #define AUDDTS (40) | |
75 | #define AUDRDD (41) | |
76 | #define AUDSTO (42) | |
77 | #define IRQ_USBPWR (43) | |
78 | #define IRQ_HCIM (44) | |
79 | #define IRQ_HCIBUFFACC (45) | |
80 | #define IRQ_HCIRMTWKP (46) | |
81 | #define IRQ_NHCIMFCIR (47) | |
82 | #define IRQ_USB_PORT_RESUME (48) | |
83 | #define IRQ_S0_READY_NINT (49) | |
84 | #define IRQ_S1_READY_NINT (50) | |
85 | #define IRQ_S0_CD_VALID (51) | |
86 | #define IRQ_S1_CD_VALID (52) | |
87 | #define IRQ_S0_BVD1_STSCHG (53) | |
88 | #define IRQ_S1_BVD1_STSCHG (54) | |
36d31213 | 89 | #define SA1111_IRQ_NR (55) |
19851c58 | 90 | |
29c140b6 RK |
91 | extern void sa1110_mb_enable(void); |
92 | extern void sa1110_mb_disable(void); | |
1da177e4 LT |
93 | |
94 | /* | |
95 | * We keep the following data for the overall SA1111. Note that the | |
96 | * struct device and struct resource are "fake"; they should be supplied | |
97 | * by the bus above us. However, in the interests of getting all SA1111 | |
98 | * drivers converted over to the device model, we provide this as an | |
99 | * anchor point for all the other drivers. | |
100 | */ | |
101 | struct sa1111 { | |
102 | struct device *dev; | |
97d654f8 | 103 | struct clk *clk; |
1da177e4 LT |
104 | unsigned long phys; |
105 | int irq; | |
19851c58 | 106 | int irq_base; /* base for cascaded on-chip IRQs */ |
1da177e4 LT |
107 | spinlock_t lock; |
108 | void __iomem *base; | |
ae99ddbc | 109 | struct sa1111_platform_data *pdata; |
93160c63 RW |
110 | #ifdef CONFIG_PM |
111 | void *saved_state; | |
112 | #endif | |
1da177e4 LT |
113 | }; |
114 | ||
115 | /* | |
116 | * We _really_ need to eliminate this. Its only users | |
117 | * are the PWM and DMA checking code. | |
118 | */ | |
119 | static struct sa1111 *g_sa1111; | |
120 | ||
121 | struct sa1111_dev_info { | |
122 | unsigned long offset; | |
123 | unsigned long skpcr_mask; | |
21d1c770 | 124 | bool dma; |
1da177e4 LT |
125 | unsigned int devid; |
126 | unsigned int irq[6]; | |
127 | }; | |
128 | ||
129 | static struct sa1111_dev_info sa1111_devices[] = { | |
130 | { | |
131 | .offset = SA1111_USB, | |
132 | .skpcr_mask = SKPCR_UCLKEN, | |
21d1c770 | 133 | .dma = true, |
1da177e4 LT |
134 | .devid = SA1111_DEVID_USB, |
135 | .irq = { | |
136 | IRQ_USBPWR, | |
137 | IRQ_HCIM, | |
138 | IRQ_HCIBUFFACC, | |
139 | IRQ_HCIRMTWKP, | |
140 | IRQ_NHCIMFCIR, | |
141 | IRQ_USB_PORT_RESUME | |
142 | }, | |
143 | }, | |
144 | { | |
145 | .offset = 0x0600, | |
146 | .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN, | |
21d1c770 | 147 | .dma = true, |
1da177e4 LT |
148 | .devid = SA1111_DEVID_SAC, |
149 | .irq = { | |
150 | AUDXMTDMADONEA, | |
151 | AUDXMTDMADONEB, | |
152 | AUDRCVDMADONEA, | |
153 | AUDRCVDMADONEB | |
154 | }, | |
155 | }, | |
156 | { | |
157 | .offset = 0x0800, | |
158 | .skpcr_mask = SKPCR_SCLKEN, | |
159 | .devid = SA1111_DEVID_SSP, | |
160 | }, | |
161 | { | |
162 | .offset = SA1111_KBD, | |
163 | .skpcr_mask = SKPCR_PTCLKEN, | |
e5c0fc41 | 164 | .devid = SA1111_DEVID_PS2_KBD, |
1da177e4 LT |
165 | .irq = { |
166 | IRQ_TPRXINT, | |
167 | IRQ_TPTXINT | |
168 | }, | |
169 | }, | |
170 | { | |
171 | .offset = SA1111_MSE, | |
172 | .skpcr_mask = SKPCR_PMCLKEN, | |
e5c0fc41 | 173 | .devid = SA1111_DEVID_PS2_MSE, |
1da177e4 LT |
174 | .irq = { |
175 | IRQ_MSRXINT, | |
176 | IRQ_MSTXINT | |
177 | }, | |
178 | }, | |
179 | { | |
180 | .offset = 0x1800, | |
181 | .skpcr_mask = 0, | |
182 | .devid = SA1111_DEVID_PCMCIA, | |
183 | .irq = { | |
184 | IRQ_S0_READY_NINT, | |
185 | IRQ_S0_CD_VALID, | |
186 | IRQ_S0_BVD1_STSCHG, | |
187 | IRQ_S1_READY_NINT, | |
188 | IRQ_S1_CD_VALID, | |
189 | IRQ_S1_BVD1_STSCHG, | |
190 | }, | |
191 | }, | |
192 | }; | |
193 | ||
194 | /* | |
195 | * SA1111 interrupt support. Since clearing an IRQ while there are | |
196 | * active IRQs causes the interrupt output to pulse, the upper levels | |
197 | * will call us again if there are more interrupts to process. | |
198 | */ | |
bd0b9ac4 | 199 | static void sa1111_irq_handler(struct irq_desc *desc) |
1da177e4 LT |
200 | { |
201 | unsigned int stat0, stat1, i; | |
f575398b | 202 | struct sa1111 *sachip = irq_desc_get_handler_data(desc); |
19851c58 | 203 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
1da177e4 | 204 | |
19851c58 EM |
205 | stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); |
206 | stat1 = sa1111_readl(mapbase + SA1111_INTSTATCLR1); | |
1da177e4 | 207 | |
19851c58 | 208 | sa1111_writel(stat0, mapbase + SA1111_INTSTATCLR0); |
1da177e4 | 209 | |
8231e741 | 210 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
1da177e4 | 211 | |
19851c58 | 212 | sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1); |
1da177e4 LT |
213 | |
214 | if (stat0 == 0 && stat1 == 0) { | |
bd0b9ac4 | 215 | do_bad_IRQ(desc); |
1da177e4 LT |
216 | return; |
217 | } | |
218 | ||
19851c58 | 219 | for (i = 0; stat0; i++, stat0 >>= 1) |
1da177e4 | 220 | if (stat0 & 1) |
19851c58 | 221 | generic_handle_irq(i + sachip->irq_base); |
1da177e4 | 222 | |
19851c58 | 223 | for (i = 32; stat1; i++, stat1 >>= 1) |
1da177e4 | 224 | if (stat1 & 1) |
19851c58 | 225 | generic_handle_irq(i + sachip->irq_base); |
1da177e4 LT |
226 | |
227 | /* For level-based interrupts */ | |
8231e741 | 228 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
1da177e4 LT |
229 | } |
230 | ||
19851c58 EM |
231 | #define SA1111_IRQMASK_LO(x) (1 << (x - sachip->irq_base)) |
232 | #define SA1111_IRQMASK_HI(x) (1 << (x - sachip->irq_base - 32)) | |
1da177e4 | 233 | |
8231e741 | 234 | static void sa1111_ack_irq(struct irq_data *d) |
1da177e4 LT |
235 | { |
236 | } | |
237 | ||
8231e741 | 238 | static void sa1111_mask_lowirq(struct irq_data *d) |
1da177e4 | 239 | { |
8231e741 | 240 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 241 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
1da177e4 LT |
242 | unsigned long ie0; |
243 | ||
244 | ie0 = sa1111_readl(mapbase + SA1111_INTEN0); | |
8231e741 | 245 | ie0 &= ~SA1111_IRQMASK_LO(d->irq); |
1da177e4 LT |
246 | writel(ie0, mapbase + SA1111_INTEN0); |
247 | } | |
248 | ||
8231e741 | 249 | static void sa1111_unmask_lowirq(struct irq_data *d) |
1da177e4 | 250 | { |
8231e741 | 251 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 252 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
1da177e4 LT |
253 | unsigned long ie0; |
254 | ||
255 | ie0 = sa1111_readl(mapbase + SA1111_INTEN0); | |
8231e741 | 256 | ie0 |= SA1111_IRQMASK_LO(d->irq); |
1da177e4 LT |
257 | sa1111_writel(ie0, mapbase + SA1111_INTEN0); |
258 | } | |
259 | ||
260 | /* | |
261 | * Attempt to re-trigger the interrupt. The SA1111 contains a register | |
262 | * (INTSET) which claims to do this. However, in practice no amount of | |
263 | * manipulation of INTEN and INTSET guarantees that the interrupt will | |
264 | * be triggered. In fact, its very difficult, if not impossible to get | |
265 | * INTSET to re-trigger the interrupt. | |
266 | */ | |
8231e741 | 267 | static int sa1111_retrigger_lowirq(struct irq_data *d) |
1da177e4 | 268 | { |
8231e741 | 269 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 270 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 271 | unsigned int mask = SA1111_IRQMASK_LO(d->irq); |
1da177e4 LT |
272 | unsigned long ip0; |
273 | int i; | |
274 | ||
275 | ip0 = sa1111_readl(mapbase + SA1111_INTPOL0); | |
276 | for (i = 0; i < 8; i++) { | |
277 | sa1111_writel(ip0 ^ mask, mapbase + SA1111_INTPOL0); | |
278 | sa1111_writel(ip0, mapbase + SA1111_INTPOL0); | |
cae39988 | 279 | if (sa1111_readl(mapbase + SA1111_INTSTATCLR0) & mask) |
1da177e4 LT |
280 | break; |
281 | } | |
282 | ||
283 | if (i == 8) | |
4ed89f22 RK |
284 | pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n", |
285 | d->irq); | |
1da177e4 LT |
286 | return i == 8 ? -1 : 0; |
287 | } | |
288 | ||
8231e741 | 289 | static int sa1111_type_lowirq(struct irq_data *d, unsigned int flags) |
1da177e4 | 290 | { |
8231e741 | 291 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 292 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 293 | unsigned int mask = SA1111_IRQMASK_LO(d->irq); |
1da177e4 LT |
294 | unsigned long ip0; |
295 | ||
6cab4860 | 296 | if (flags == IRQ_TYPE_PROBE) |
1da177e4 LT |
297 | return 0; |
298 | ||
6cab4860 | 299 | if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) |
1da177e4 LT |
300 | return -EINVAL; |
301 | ||
302 | ip0 = sa1111_readl(mapbase + SA1111_INTPOL0); | |
6cab4860 | 303 | if (flags & IRQ_TYPE_EDGE_RISING) |
1da177e4 LT |
304 | ip0 &= ~mask; |
305 | else | |
306 | ip0 |= mask; | |
307 | sa1111_writel(ip0, mapbase + SA1111_INTPOL0); | |
308 | sa1111_writel(ip0, mapbase + SA1111_WAKEPOL0); | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
8231e741 | 313 | static int sa1111_wake_lowirq(struct irq_data *d, unsigned int on) |
1da177e4 | 314 | { |
8231e741 | 315 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 316 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 317 | unsigned int mask = SA1111_IRQMASK_LO(d->irq); |
1da177e4 LT |
318 | unsigned long we0; |
319 | ||
320 | we0 = sa1111_readl(mapbase + SA1111_WAKEEN0); | |
321 | if (on) | |
322 | we0 |= mask; | |
323 | else | |
324 | we0 &= ~mask; | |
325 | sa1111_writel(we0, mapbase + SA1111_WAKEEN0); | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
38c677cb DB |
330 | static struct irq_chip sa1111_low_chip = { |
331 | .name = "SA1111-l", | |
8231e741 LB |
332 | .irq_ack = sa1111_ack_irq, |
333 | .irq_mask = sa1111_mask_lowirq, | |
334 | .irq_unmask = sa1111_unmask_lowirq, | |
335 | .irq_retrigger = sa1111_retrigger_lowirq, | |
336 | .irq_set_type = sa1111_type_lowirq, | |
337 | .irq_set_wake = sa1111_wake_lowirq, | |
1da177e4 LT |
338 | }; |
339 | ||
8231e741 | 340 | static void sa1111_mask_highirq(struct irq_data *d) |
1da177e4 | 341 | { |
8231e741 | 342 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 343 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
1da177e4 LT |
344 | unsigned long ie1; |
345 | ||
346 | ie1 = sa1111_readl(mapbase + SA1111_INTEN1); | |
8231e741 | 347 | ie1 &= ~SA1111_IRQMASK_HI(d->irq); |
1da177e4 LT |
348 | sa1111_writel(ie1, mapbase + SA1111_INTEN1); |
349 | } | |
350 | ||
8231e741 | 351 | static void sa1111_unmask_highirq(struct irq_data *d) |
1da177e4 | 352 | { |
8231e741 | 353 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 354 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
1da177e4 LT |
355 | unsigned long ie1; |
356 | ||
357 | ie1 = sa1111_readl(mapbase + SA1111_INTEN1); | |
8231e741 | 358 | ie1 |= SA1111_IRQMASK_HI(d->irq); |
1da177e4 LT |
359 | sa1111_writel(ie1, mapbase + SA1111_INTEN1); |
360 | } | |
361 | ||
362 | /* | |
363 | * Attempt to re-trigger the interrupt. The SA1111 contains a register | |
364 | * (INTSET) which claims to do this. However, in practice no amount of | |
365 | * manipulation of INTEN and INTSET guarantees that the interrupt will | |
366 | * be triggered. In fact, its very difficult, if not impossible to get | |
367 | * INTSET to re-trigger the interrupt. | |
368 | */ | |
8231e741 | 369 | static int sa1111_retrigger_highirq(struct irq_data *d) |
1da177e4 | 370 | { |
8231e741 | 371 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 372 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 373 | unsigned int mask = SA1111_IRQMASK_HI(d->irq); |
1da177e4 LT |
374 | unsigned long ip1; |
375 | int i; | |
376 | ||
377 | ip1 = sa1111_readl(mapbase + SA1111_INTPOL1); | |
378 | for (i = 0; i < 8; i++) { | |
379 | sa1111_writel(ip1 ^ mask, mapbase + SA1111_INTPOL1); | |
380 | sa1111_writel(ip1, mapbase + SA1111_INTPOL1); | |
381 | if (sa1111_readl(mapbase + SA1111_INTSTATCLR1) & mask) | |
382 | break; | |
383 | } | |
384 | ||
385 | if (i == 8) | |
4ed89f22 RK |
386 | pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n", |
387 | d->irq); | |
1da177e4 LT |
388 | return i == 8 ? -1 : 0; |
389 | } | |
390 | ||
8231e741 | 391 | static int sa1111_type_highirq(struct irq_data *d, unsigned int flags) |
1da177e4 | 392 | { |
8231e741 | 393 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 394 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 395 | unsigned int mask = SA1111_IRQMASK_HI(d->irq); |
1da177e4 LT |
396 | unsigned long ip1; |
397 | ||
6cab4860 | 398 | if (flags == IRQ_TYPE_PROBE) |
1da177e4 LT |
399 | return 0; |
400 | ||
6cab4860 | 401 | if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) |
1da177e4 LT |
402 | return -EINVAL; |
403 | ||
404 | ip1 = sa1111_readl(mapbase + SA1111_INTPOL1); | |
6cab4860 | 405 | if (flags & IRQ_TYPE_EDGE_RISING) |
1da177e4 LT |
406 | ip1 &= ~mask; |
407 | else | |
408 | ip1 |= mask; | |
409 | sa1111_writel(ip1, mapbase + SA1111_INTPOL1); | |
410 | sa1111_writel(ip1, mapbase + SA1111_WAKEPOL1); | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
8231e741 | 415 | static int sa1111_wake_highirq(struct irq_data *d, unsigned int on) |
1da177e4 | 416 | { |
8231e741 | 417 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 418 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 419 | unsigned int mask = SA1111_IRQMASK_HI(d->irq); |
1da177e4 LT |
420 | unsigned long we1; |
421 | ||
422 | we1 = sa1111_readl(mapbase + SA1111_WAKEEN1); | |
423 | if (on) | |
424 | we1 |= mask; | |
425 | else | |
426 | we1 &= ~mask; | |
427 | sa1111_writel(we1, mapbase + SA1111_WAKEEN1); | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
38c677cb DB |
432 | static struct irq_chip sa1111_high_chip = { |
433 | .name = "SA1111-h", | |
8231e741 LB |
434 | .irq_ack = sa1111_ack_irq, |
435 | .irq_mask = sa1111_mask_highirq, | |
436 | .irq_unmask = sa1111_unmask_highirq, | |
437 | .irq_retrigger = sa1111_retrigger_highirq, | |
438 | .irq_set_type = sa1111_type_highirq, | |
439 | .irq_set_wake = sa1111_wake_highirq, | |
1da177e4 LT |
440 | }; |
441 | ||
36d31213 | 442 | static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base) |
1da177e4 LT |
443 | { |
444 | void __iomem *irqbase = sachip->base + SA1111_INTC; | |
f03ecaa0 | 445 | unsigned i, irq; |
36d31213 | 446 | int ret; |
1da177e4 LT |
447 | |
448 | /* | |
449 | * We're guaranteed that this region hasn't been taken. | |
450 | */ | |
451 | request_mem_region(sachip->phys + SA1111_INTC, 512, "irq"); | |
452 | ||
36d31213 RK |
453 | ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1); |
454 | if (ret <= 0) { | |
455 | dev_err(sachip->dev, "unable to allocate %u irqs: %d\n", | |
456 | SA1111_IRQ_NR, ret); | |
457 | if (ret == 0) | |
458 | ret = -EINVAL; | |
459 | return ret; | |
460 | } | |
461 | ||
462 | sachip->irq_base = ret; | |
463 | ||
1da177e4 LT |
464 | /* disable all IRQs */ |
465 | sa1111_writel(0, irqbase + SA1111_INTEN0); | |
466 | sa1111_writel(0, irqbase + SA1111_INTEN1); | |
467 | sa1111_writel(0, irqbase + SA1111_WAKEEN0); | |
468 | sa1111_writel(0, irqbase + SA1111_WAKEEN1); | |
469 | ||
470 | /* | |
471 | * detect on rising edge. Note: Feb 2001 Errata for SA1111 | |
472 | * specifies that S0ReadyInt and S1ReadyInt should be '1'. | |
473 | */ | |
474 | sa1111_writel(0, irqbase + SA1111_INTPOL0); | |
475 | sa1111_writel(SA1111_IRQMASK_HI(IRQ_S0_READY_NINT) | | |
476 | SA1111_IRQMASK_HI(IRQ_S1_READY_NINT), | |
477 | irqbase + SA1111_INTPOL1); | |
478 | ||
479 | /* clear all IRQs */ | |
480 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR0); | |
481 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); | |
482 | ||
f03ecaa0 RK |
483 | for (i = IRQ_GPAIN0; i <= SSPROR; i++) { |
484 | irq = sachip->irq_base + i; | |
f38c02f3 TG |
485 | irq_set_chip_and_handler(irq, &sa1111_low_chip, |
486 | handle_edge_irq); | |
9323f261 | 487 | irq_set_chip_data(irq, sachip); |
e8d36d5d | 488 | irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
1da177e4 LT |
489 | } |
490 | ||
f03ecaa0 RK |
491 | for (i = AUDXMTDMADONEA; i <= IRQ_S1_BVD1_STSCHG; i++) { |
492 | irq = sachip->irq_base + i; | |
f38c02f3 TG |
493 | irq_set_chip_and_handler(irq, &sa1111_high_chip, |
494 | handle_edge_irq); | |
9323f261 | 495 | irq_set_chip_data(irq, sachip); |
e8d36d5d | 496 | irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
1da177e4 LT |
497 | } |
498 | ||
499 | /* | |
500 | * Register SA1111 interrupt | |
501 | */ | |
6845664a | 502 | irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); |
056c0acf RK |
503 | irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler, |
504 | sachip); | |
36d31213 RK |
505 | |
506 | dev_info(sachip->dev, "Providing IRQ%u-%u\n", | |
507 | sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1); | |
508 | ||
509 | return 0; | |
1da177e4 LT |
510 | } |
511 | ||
512 | /* | |
513 | * Bring the SA1111 out of reset. This requires a set procedure: | |
514 | * 1. nRESET asserted (by hardware) | |
515 | * 2. CLK turned on from SA1110 | |
516 | * 3. nRESET deasserted | |
517 | * 4. VCO turned on, PLL_BYPASS turned off | |
518 | * 5. Wait lock time, then assert RCLKEn | |
519 | * 7. PCR set to allow clocking of individual functions | |
520 | * | |
521 | * Until we've done this, the only registers we can access are: | |
522 | * SBI_SKCR | |
523 | * SBI_SMCR | |
524 | * SBI_SKID | |
525 | */ | |
526 | static void sa1111_wake(struct sa1111 *sachip) | |
527 | { | |
528 | unsigned long flags, r; | |
529 | ||
530 | spin_lock_irqsave(&sachip->lock, flags); | |
531 | ||
97d654f8 | 532 | clk_enable(sachip->clk); |
1da177e4 LT |
533 | |
534 | /* | |
535 | * Turn VCO on, and disable PLL Bypass. | |
536 | */ | |
537 | r = sa1111_readl(sachip->base + SA1111_SKCR); | |
538 | r &= ~SKCR_VCO_OFF; | |
539 | sa1111_writel(r, sachip->base + SA1111_SKCR); | |
540 | r |= SKCR_PLL_BYPASS | SKCR_OE_EN; | |
541 | sa1111_writel(r, sachip->base + SA1111_SKCR); | |
542 | ||
543 | /* | |
544 | * Wait lock time. SA1111 manual _doesn't_ | |
545 | * specify a figure for this! We choose 100us. | |
546 | */ | |
547 | udelay(100); | |
548 | ||
549 | /* | |
550 | * Enable RCLK. We also ensure that RDYEN is set. | |
551 | */ | |
552 | r |= SKCR_RCLKEN | SKCR_RDYEN; | |
553 | sa1111_writel(r, sachip->base + SA1111_SKCR); | |
554 | ||
555 | /* | |
556 | * Wait 14 RCLK cycles for the chip to finish coming out | |
557 | * of reset. (RCLK=24MHz). This is 590ns. | |
558 | */ | |
559 | udelay(1); | |
560 | ||
561 | /* | |
562 | * Ensure all clocks are initially off. | |
563 | */ | |
564 | sa1111_writel(0, sachip->base + SA1111_SKPCR); | |
565 | ||
566 | spin_unlock_irqrestore(&sachip->lock, flags); | |
567 | } | |
568 | ||
569 | #ifdef CONFIG_ARCH_SA1100 | |
570 | ||
571 | static u32 sa1111_dma_mask[] = { | |
572 | ~0, | |
573 | ~(1 << 20), | |
574 | ~(1 << 23), | |
575 | ~(1 << 24), | |
576 | ~(1 << 25), | |
577 | ~(1 << 20), | |
578 | ~(1 << 20), | |
579 | 0, | |
580 | }; | |
581 | ||
582 | /* | |
583 | * Configure the SA1111 shared memory controller. | |
584 | */ | |
585 | void | |
586 | sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac, | |
587 | unsigned int cas_latency) | |
588 | { | |
589 | unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC); | |
590 | ||
591 | if (cas_latency == 3) | |
592 | smcr |= SMCR_CLAT; | |
593 | ||
594 | sa1111_writel(smcr, sachip->base + SA1111_SMCR); | |
595 | ||
596 | /* | |
597 | * Now clear the bits in the DMA mask to work around the SA1111 | |
598 | * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion | |
599 | * Chip Specification Update, June 2000, Erratum #7). | |
600 | */ | |
601 | if (sachip->dev->dma_mask) | |
602 | *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2]; | |
603 | ||
604 | sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2]; | |
605 | } | |
0703ed2a | 606 | #endif |
1da177e4 | 607 | |
1da177e4 LT |
608 | static void sa1111_dev_release(struct device *_dev) |
609 | { | |
610 | struct sa1111_dev *dev = SA1111_DEV(_dev); | |
611 | ||
1da177e4 LT |
612 | kfree(dev); |
613 | } | |
614 | ||
615 | static int | |
616 | sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent, | |
617 | struct sa1111_dev_info *info) | |
618 | { | |
619 | struct sa1111_dev *dev; | |
f03ecaa0 | 620 | unsigned i; |
1da177e4 LT |
621 | int ret; |
622 | ||
d2a02b93 | 623 | dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL); |
1da177e4 LT |
624 | if (!dev) { |
625 | ret = -ENOMEM; | |
924e1d49 | 626 | goto err_alloc; |
1da177e4 | 627 | } |
1da177e4 | 628 | |
924e1d49 | 629 | device_initialize(&dev->dev); |
3f978704 | 630 | dev_set_name(&dev->dev, "%4.4lx", info->offset); |
1da177e4 LT |
631 | dev->devid = info->devid; |
632 | dev->dev.parent = sachip->dev; | |
633 | dev->dev.bus = &sa1111_bus_type; | |
634 | dev->dev.release = sa1111_dev_release; | |
1da177e4 LT |
635 | dev->res.start = sachip->phys + info->offset; |
636 | dev->res.end = dev->res.start + 511; | |
3f978704 | 637 | dev->res.name = dev_name(&dev->dev); |
1da177e4 LT |
638 | dev->res.flags = IORESOURCE_MEM; |
639 | dev->mapbase = sachip->base + info->offset; | |
640 | dev->skpcr_mask = info->skpcr_mask; | |
f03ecaa0 RK |
641 | |
642 | for (i = 0; i < ARRAY_SIZE(info->irq); i++) | |
643 | dev->irq[i] = sachip->irq_base + info->irq[i]; | |
1da177e4 | 644 | |
09a2ba2f | 645 | /* |
21d1c770 RK |
646 | * If the parent device has a DMA mask associated with it, and |
647 | * this child supports DMA, propagate it down to the children. | |
09a2ba2f | 648 | */ |
21d1c770 | 649 | if (info->dma && sachip->dev->dma_mask) { |
09a2ba2f RK |
650 | dev->dma_mask = *sachip->dev->dma_mask; |
651 | dev->dev.dma_mask = &dev->dma_mask; | |
652 | dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask; | |
653 | } | |
654 | ||
1da177e4 LT |
655 | ret = request_resource(parent, &dev->res); |
656 | if (ret) { | |
22eeaff3 | 657 | dev_err(sachip->dev, "failed to allocate resource for %s\n", |
1da177e4 | 658 | dev->res.name); |
924e1d49 | 659 | goto err_resource; |
1da177e4 LT |
660 | } |
661 | ||
924e1d49 RK |
662 | ret = device_add(&dev->dev); |
663 | if (ret) | |
664 | goto err_add; | |
665 | return 0; | |
1da177e4 | 666 | |
924e1d49 RK |
667 | err_add: |
668 | release_resource(&dev->res); | |
669 | err_resource: | |
670 | put_device(&dev->dev); | |
671 | err_alloc: | |
1da177e4 LT |
672 | return ret; |
673 | } | |
674 | ||
675 | /** | |
676 | * sa1111_probe - probe for a single SA1111 chip. | |
677 | * @phys_addr: physical address of device. | |
678 | * | |
679 | * Probe for a SA1111 chip. This must be called | |
680 | * before any other SA1111-specific code. | |
681 | * | |
682 | * Returns: | |
683 | * %-ENODEV device not found. | |
684 | * %-EBUSY physical address already marked in-use. | |
f03ecaa0 | 685 | * %-EINVAL no platform data passed |
1da177e4 LT |
686 | * %0 successful. |
687 | */ | |
351a102d | 688 | static int __sa1111_probe(struct device *me, struct resource *mem, int irq) |
1da177e4 | 689 | { |
f03ecaa0 | 690 | struct sa1111_platform_data *pd = me->platform_data; |
1da177e4 LT |
691 | struct sa1111 *sachip; |
692 | unsigned long id; | |
416112f8 | 693 | unsigned int has_devs; |
1da177e4 LT |
694 | int i, ret = -ENODEV; |
695 | ||
f03ecaa0 RK |
696 | if (!pd) |
697 | return -EINVAL; | |
698 | ||
d2a02b93 | 699 | sachip = kzalloc(sizeof(struct sa1111), GFP_KERNEL); |
1da177e4 LT |
700 | if (!sachip) |
701 | return -ENOMEM; | |
702 | ||
13f75582 | 703 | sachip->clk = clk_get(me, "SA1111_CLK"); |
442a9022 | 704 | if (IS_ERR(sachip->clk)) { |
97d654f8 RK |
705 | ret = PTR_ERR(sachip->clk); |
706 | goto err_free; | |
707 | } | |
708 | ||
72ae00c9 RK |
709 | ret = clk_prepare(sachip->clk); |
710 | if (ret) | |
711 | goto err_clkput; | |
712 | ||
1da177e4 LT |
713 | spin_lock_init(&sachip->lock); |
714 | ||
715 | sachip->dev = me; | |
716 | dev_set_drvdata(sachip->dev, sachip); | |
717 | ||
ae99ddbc | 718 | sachip->pdata = pd; |
1da177e4 LT |
719 | sachip->phys = mem->start; |
720 | sachip->irq = irq; | |
721 | ||
722 | /* | |
723 | * Map the whole region. This also maps the | |
724 | * registers for our children. | |
725 | */ | |
726 | sachip->base = ioremap(mem->start, PAGE_SIZE * 2); | |
727 | if (!sachip->base) { | |
728 | ret = -ENOMEM; | |
72ae00c9 | 729 | goto err_clk_unprep; |
1da177e4 LT |
730 | } |
731 | ||
732 | /* | |
733 | * Probe for the chip. Only touch the SBI registers. | |
734 | */ | |
735 | id = sa1111_readl(sachip->base + SA1111_SKID); | |
736 | if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { | |
737 | printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id); | |
738 | ret = -ENODEV; | |
97d654f8 | 739 | goto err_unmap; |
1da177e4 LT |
740 | } |
741 | ||
4ed89f22 RK |
742 | pr_info("SA1111 Microprocessor Companion Chip: silicon revision %lx, metal revision %lx\n", |
743 | (id & SKID_SIREV_MASK) >> 4, id & SKID_MTREV_MASK); | |
1da177e4 LT |
744 | |
745 | /* | |
746 | * We found it. Wake the chip up, and initialise. | |
747 | */ | |
748 | sa1111_wake(sachip); | |
749 | ||
36d31213 RK |
750 | /* |
751 | * The interrupt controller must be initialised before any | |
752 | * other device to ensure that the interrupts are available. | |
753 | */ | |
754 | if (sachip->irq != NO_IRQ) { | |
755 | ret = sa1111_setup_irq(sachip, pd->irq_base); | |
756 | if (ret) | |
757 | goto err_unmap; | |
758 | } | |
759 | ||
1da177e4 | 760 | #ifdef CONFIG_ARCH_SA1100 |
416112f8 DB |
761 | { |
762 | unsigned int val; | |
763 | ||
1da177e4 LT |
764 | /* |
765 | * The SDRAM configuration of the SA1110 and the SA1111 must | |
766 | * match. This is very important to ensure that SA1111 accesses | |
767 | * don't corrupt the SDRAM. Note that this ungates the SA1111's | |
768 | * MBGNT signal, so we must have called sa1110_mb_disable() | |
769 | * beforehand. | |
770 | */ | |
771 | sa1111_configure_smc(sachip, 1, | |
772 | FExtr(MDCNFG, MDCNFG_SA1110_DRAC0), | |
773 | FExtr(MDCNFG, MDCNFG_SA1110_TDL0)); | |
774 | ||
775 | /* | |
776 | * We only need to turn on DCLK whenever we want to use the | |
777 | * DMA. It can otherwise be held firmly in the off position. | |
778 | * (currently, we always enable it.) | |
779 | */ | |
780 | val = sa1111_readl(sachip->base + SA1111_SKPCR); | |
781 | sa1111_writel(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR); | |
782 | ||
783 | /* | |
784 | * Enable the SA1110 memory bus request and grant signals. | |
785 | */ | |
786 | sa1110_mb_enable(); | |
416112f8 | 787 | } |
1da177e4 LT |
788 | #endif |
789 | ||
1da177e4 LT |
790 | g_sa1111 = sachip; |
791 | ||
792 | has_devs = ~0; | |
07be45f5 RK |
793 | if (pd) |
794 | has_devs &= ~pd->disable_devs; | |
1da177e4 LT |
795 | |
796 | for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++) | |
e5c0fc41 | 797 | if (sa1111_devices[i].devid & has_devs) |
1da177e4 LT |
798 | sa1111_init_one_child(sachip, mem, &sa1111_devices[i]); |
799 | ||
800 | return 0; | |
801 | ||
97d654f8 | 802 | err_unmap: |
1da177e4 | 803 | iounmap(sachip->base); |
72ae00c9 RK |
804 | err_clk_unprep: |
805 | clk_unprepare(sachip->clk); | |
97d654f8 RK |
806 | err_clkput: |
807 | clk_put(sachip->clk); | |
808 | err_free: | |
1da177e4 LT |
809 | kfree(sachip); |
810 | return ret; | |
811 | } | |
812 | ||
522c37b9 RK |
813 | static int sa1111_remove_one(struct device *dev, void *data) |
814 | { | |
924e1d49 RK |
815 | struct sa1111_dev *sadev = SA1111_DEV(dev); |
816 | device_del(&sadev->dev); | |
817 | release_resource(&sadev->res); | |
818 | put_device(&sadev->dev); | |
522c37b9 RK |
819 | return 0; |
820 | } | |
821 | ||
1da177e4 LT |
822 | static void __sa1111_remove(struct sa1111 *sachip) |
823 | { | |
1da177e4 LT |
824 | void __iomem *irqbase = sachip->base + SA1111_INTC; |
825 | ||
522c37b9 | 826 | device_for_each_child(sachip->dev, NULL, sa1111_remove_one); |
1da177e4 LT |
827 | |
828 | /* disable all IRQs */ | |
829 | sa1111_writel(0, irqbase + SA1111_INTEN0); | |
830 | sa1111_writel(0, irqbase + SA1111_INTEN1); | |
831 | sa1111_writel(0, irqbase + SA1111_WAKEEN0); | |
832 | sa1111_writel(0, irqbase + SA1111_WAKEEN1); | |
833 | ||
97d654f8 | 834 | clk_disable(sachip->clk); |
72ae00c9 | 835 | clk_unprepare(sachip->clk); |
97d654f8 | 836 | |
1da177e4 | 837 | if (sachip->irq != NO_IRQ) { |
056c0acf | 838 | irq_set_chained_handler_and_data(sachip->irq, NULL, NULL); |
36d31213 | 839 | irq_free_descs(sachip->irq_base, SA1111_IRQ_NR); |
1da177e4 LT |
840 | |
841 | release_mem_region(sachip->phys + SA1111_INTC, 512); | |
842 | } | |
843 | ||
844 | iounmap(sachip->base); | |
97d654f8 | 845 | clk_put(sachip->clk); |
1da177e4 LT |
846 | kfree(sachip); |
847 | } | |
848 | ||
1da177e4 LT |
849 | struct sa1111_save_data { |
850 | unsigned int skcr; | |
851 | unsigned int skpcr; | |
852 | unsigned int skcdr; | |
853 | unsigned char skaud; | |
854 | unsigned char skpwm0; | |
855 | unsigned char skpwm1; | |
856 | ||
857 | /* | |
858 | * Interrupt controller | |
859 | */ | |
860 | unsigned int intpol0; | |
861 | unsigned int intpol1; | |
862 | unsigned int inten0; | |
863 | unsigned int inten1; | |
864 | unsigned int wakepol0; | |
865 | unsigned int wakepol1; | |
866 | unsigned int wakeen0; | |
867 | unsigned int wakeen1; | |
868 | }; | |
869 | ||
870 | #ifdef CONFIG_PM | |
871 | ||
3ae5eaec | 872 | static int sa1111_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 873 | { |
3ae5eaec | 874 | struct sa1111 *sachip = platform_get_drvdata(dev); |
1da177e4 LT |
875 | struct sa1111_save_data *save; |
876 | unsigned long flags; | |
877 | unsigned int val; | |
878 | void __iomem *base; | |
879 | ||
1da177e4 LT |
880 | save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL); |
881 | if (!save) | |
882 | return -ENOMEM; | |
93160c63 | 883 | sachip->saved_state = save; |
1da177e4 LT |
884 | |
885 | spin_lock_irqsave(&sachip->lock, flags); | |
886 | ||
887 | /* | |
888 | * Save state. | |
889 | */ | |
890 | base = sachip->base; | |
891 | save->skcr = sa1111_readl(base + SA1111_SKCR); | |
892 | save->skpcr = sa1111_readl(base + SA1111_SKPCR); | |
893 | save->skcdr = sa1111_readl(base + SA1111_SKCDR); | |
894 | save->skaud = sa1111_readl(base + SA1111_SKAUD); | |
895 | save->skpwm0 = sa1111_readl(base + SA1111_SKPWM0); | |
896 | save->skpwm1 = sa1111_readl(base + SA1111_SKPWM1); | |
897 | ||
a22db0f3 RK |
898 | sa1111_writel(0, sachip->base + SA1111_SKPWM0); |
899 | sa1111_writel(0, sachip->base + SA1111_SKPWM1); | |
900 | ||
1da177e4 LT |
901 | base = sachip->base + SA1111_INTC; |
902 | save->intpol0 = sa1111_readl(base + SA1111_INTPOL0); | |
903 | save->intpol1 = sa1111_readl(base + SA1111_INTPOL1); | |
904 | save->inten0 = sa1111_readl(base + SA1111_INTEN0); | |
905 | save->inten1 = sa1111_readl(base + SA1111_INTEN1); | |
906 | save->wakepol0 = sa1111_readl(base + SA1111_WAKEPOL0); | |
907 | save->wakepol1 = sa1111_readl(base + SA1111_WAKEPOL1); | |
908 | save->wakeen0 = sa1111_readl(base + SA1111_WAKEEN0); | |
909 | save->wakeen1 = sa1111_readl(base + SA1111_WAKEEN1); | |
910 | ||
911 | /* | |
912 | * Disable. | |
913 | */ | |
914 | val = sa1111_readl(sachip->base + SA1111_SKCR); | |
915 | sa1111_writel(val | SKCR_SLEEP, sachip->base + SA1111_SKCR); | |
1da177e4 | 916 | |
97d654f8 RK |
917 | clk_disable(sachip->clk); |
918 | ||
1da177e4 LT |
919 | spin_unlock_irqrestore(&sachip->lock, flags); |
920 | ||
29c140b6 RK |
921 | #ifdef CONFIG_ARCH_SA1100 |
922 | sa1110_mb_disable(); | |
923 | #endif | |
924 | ||
1da177e4 LT |
925 | return 0; |
926 | } | |
927 | ||
928 | /* | |
929 | * sa1111_resume - Restore the SA1111 device state. | |
930 | * @dev: device to restore | |
1da177e4 LT |
931 | * |
932 | * Restore the general state of the SA1111; clock control and | |
933 | * interrupt controller. Other parts of the SA1111 must be | |
934 | * restored by their respective drivers, and must be called | |
935 | * via LDM after this function. | |
936 | */ | |
3ae5eaec | 937 | static int sa1111_resume(struct platform_device *dev) |
1da177e4 | 938 | { |
3ae5eaec | 939 | struct sa1111 *sachip = platform_get_drvdata(dev); |
1da177e4 LT |
940 | struct sa1111_save_data *save; |
941 | unsigned long flags, id; | |
942 | void __iomem *base; | |
943 | ||
93160c63 | 944 | save = sachip->saved_state; |
1da177e4 LT |
945 | if (!save) |
946 | return 0; | |
947 | ||
1da177e4 LT |
948 | /* |
949 | * Ensure that the SA1111 is still here. | |
950 | * FIXME: shouldn't do this here. | |
951 | */ | |
952 | id = sa1111_readl(sachip->base + SA1111_SKID); | |
953 | if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { | |
954 | __sa1111_remove(sachip); | |
3ae5eaec | 955 | platform_set_drvdata(dev, NULL); |
1da177e4 LT |
956 | kfree(save); |
957 | return 0; | |
958 | } | |
959 | ||
960 | /* | |
961 | * First of all, wake up the chip. | |
962 | */ | |
963 | sa1111_wake(sachip); | |
3defb247 | 964 | |
29c140b6 RK |
965 | #ifdef CONFIG_ARCH_SA1100 |
966 | /* Enable the memory bus request/grant signals */ | |
967 | sa1110_mb_enable(); | |
968 | #endif | |
969 | ||
3defb247 MV |
970 | /* |
971 | * Only lock for write ops. Also, sa1111_wake must be called with | |
972 | * released spinlock! | |
973 | */ | |
974 | spin_lock_irqsave(&sachip->lock, flags); | |
975 | ||
1da177e4 LT |
976 | sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN0); |
977 | sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN1); | |
978 | ||
979 | base = sachip->base; | |
980 | sa1111_writel(save->skcr, base + SA1111_SKCR); | |
981 | sa1111_writel(save->skpcr, base + SA1111_SKPCR); | |
982 | sa1111_writel(save->skcdr, base + SA1111_SKCDR); | |
983 | sa1111_writel(save->skaud, base + SA1111_SKAUD); | |
984 | sa1111_writel(save->skpwm0, base + SA1111_SKPWM0); | |
985 | sa1111_writel(save->skpwm1, base + SA1111_SKPWM1); | |
986 | ||
987 | base = sachip->base + SA1111_INTC; | |
988 | sa1111_writel(save->intpol0, base + SA1111_INTPOL0); | |
989 | sa1111_writel(save->intpol1, base + SA1111_INTPOL1); | |
990 | sa1111_writel(save->inten0, base + SA1111_INTEN0); | |
991 | sa1111_writel(save->inten1, base + SA1111_INTEN1); | |
992 | sa1111_writel(save->wakepol0, base + SA1111_WAKEPOL0); | |
993 | sa1111_writel(save->wakepol1, base + SA1111_WAKEPOL1); | |
994 | sa1111_writel(save->wakeen0, base + SA1111_WAKEEN0); | |
995 | sa1111_writel(save->wakeen1, base + SA1111_WAKEEN1); | |
996 | ||
997 | spin_unlock_irqrestore(&sachip->lock, flags); | |
998 | ||
93160c63 | 999 | sachip->saved_state = NULL; |
1da177e4 LT |
1000 | kfree(save); |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | #else | |
1006 | #define sa1111_suspend NULL | |
1007 | #define sa1111_resume NULL | |
1008 | #endif | |
1009 | ||
351a102d | 1010 | static int sa1111_probe(struct platform_device *pdev) |
1da177e4 | 1011 | { |
1da177e4 LT |
1012 | struct resource *mem; |
1013 | int irq; | |
1014 | ||
1015 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1016 | if (!mem) | |
1017 | return -EINVAL; | |
1018 | irq = platform_get_irq(pdev, 0); | |
48944738 DV |
1019 | if (irq < 0) |
1020 | return -ENXIO; | |
1da177e4 | 1021 | |
3ae5eaec | 1022 | return __sa1111_probe(&pdev->dev, mem, irq); |
1da177e4 LT |
1023 | } |
1024 | ||
3ae5eaec | 1025 | static int sa1111_remove(struct platform_device *pdev) |
1da177e4 | 1026 | { |
3ae5eaec | 1027 | struct sa1111 *sachip = platform_get_drvdata(pdev); |
1da177e4 LT |
1028 | |
1029 | if (sachip) { | |
1da177e4 | 1030 | #ifdef CONFIG_PM |
93160c63 RW |
1031 | kfree(sachip->saved_state); |
1032 | sachip->saved_state = NULL; | |
1da177e4 | 1033 | #endif |
f2d2420b JL |
1034 | __sa1111_remove(sachip); |
1035 | platform_set_drvdata(pdev, NULL); | |
1da177e4 LT |
1036 | } |
1037 | ||
1038 | return 0; | |
1039 | } | |
1040 | ||
1041 | /* | |
1042 | * Not sure if this should be on the system bus or not yet. | |
1043 | * We really want some way to register a system device at | |
1044 | * the per-machine level, and then have this driver pick | |
1045 | * up the registered devices. | |
1046 | * | |
1047 | * We also need to handle the SDRAM configuration for | |
1048 | * PXA250/SA1110 machine classes. | |
1049 | */ | |
3ae5eaec | 1050 | static struct platform_driver sa1111_device_driver = { |
1da177e4 LT |
1051 | .probe = sa1111_probe, |
1052 | .remove = sa1111_remove, | |
1053 | .suspend = sa1111_suspend, | |
1054 | .resume = sa1111_resume, | |
3ae5eaec RK |
1055 | .driver = { |
1056 | .name = "sa1111", | |
1057 | }, | |
1da177e4 LT |
1058 | }; |
1059 | ||
1060 | /* | |
1061 | * Get the parent device driver (us) structure | |
1062 | * from a child function device | |
1063 | */ | |
1064 | static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev) | |
1065 | { | |
1066 | return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent); | |
1067 | } | |
1068 | ||
1069 | /* | |
1070 | * The bits in the opdiv field are non-linear. | |
1071 | */ | |
1072 | static unsigned char opdiv_table[] = { 1, 4, 2, 8 }; | |
1073 | ||
1074 | static unsigned int __sa1111_pll_clock(struct sa1111 *sachip) | |
1075 | { | |
1076 | unsigned int skcdr, fbdiv, ipdiv, opdiv; | |
1077 | ||
1078 | skcdr = sa1111_readl(sachip->base + SA1111_SKCDR); | |
1079 | ||
1080 | fbdiv = (skcdr & 0x007f) + 2; | |
1081 | ipdiv = ((skcdr & 0x0f80) >> 7) + 2; | |
1082 | opdiv = opdiv_table[(skcdr & 0x3000) >> 12]; | |
1083 | ||
1084 | return 3686400 * fbdiv / (ipdiv * opdiv); | |
1085 | } | |
1086 | ||
1087 | /** | |
1088 | * sa1111_pll_clock - return the current PLL clock frequency. | |
1089 | * @sadev: SA1111 function block | |
1090 | * | |
1091 | * BUG: we should look at SKCR. We also blindly believe that | |
1092 | * the chip is being fed with the 3.6864MHz clock. | |
1093 | * | |
1094 | * Returns the PLL clock in Hz. | |
1095 | */ | |
1096 | unsigned int sa1111_pll_clock(struct sa1111_dev *sadev) | |
1097 | { | |
1098 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1099 | ||
1100 | return __sa1111_pll_clock(sachip); | |
1101 | } | |
0a4bc5e8 | 1102 | EXPORT_SYMBOL(sa1111_pll_clock); |
1da177e4 LT |
1103 | |
1104 | /** | |
1105 | * sa1111_select_audio_mode - select I2S or AC link mode | |
1106 | * @sadev: SA1111 function block | |
1107 | * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S | |
1108 | * | |
1109 | * Frob the SKCR to select AC Link mode or I2S mode for | |
1110 | * the audio block. | |
1111 | */ | |
1112 | void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode) | |
1113 | { | |
1114 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1115 | unsigned long flags; | |
1116 | unsigned int val; | |
1117 | ||
1118 | spin_lock_irqsave(&sachip->lock, flags); | |
1119 | ||
1120 | val = sa1111_readl(sachip->base + SA1111_SKCR); | |
1121 | if (mode == SA1111_AUDIO_I2S) { | |
1122 | val &= ~SKCR_SELAC; | |
1123 | } else { | |
1124 | val |= SKCR_SELAC; | |
1125 | } | |
1126 | sa1111_writel(val, sachip->base + SA1111_SKCR); | |
1127 | ||
1128 | spin_unlock_irqrestore(&sachip->lock, flags); | |
1129 | } | |
0a4bc5e8 | 1130 | EXPORT_SYMBOL(sa1111_select_audio_mode); |
1da177e4 LT |
1131 | |
1132 | /** | |
1133 | * sa1111_set_audio_rate - set the audio sample rate | |
1134 | * @sadev: SA1111 SAC function block | |
1135 | * @rate: sample rate to select | |
1136 | */ | |
1137 | int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate) | |
1138 | { | |
1139 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1140 | unsigned int div; | |
1141 | ||
1142 | if (sadev->devid != SA1111_DEVID_SAC) | |
1143 | return -EINVAL; | |
1144 | ||
1145 | div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate; | |
1146 | if (div == 0) | |
1147 | div = 1; | |
1148 | if (div > 128) | |
1149 | div = 128; | |
1150 | ||
1151 | sa1111_writel(div - 1, sachip->base + SA1111_SKAUD); | |
1152 | ||
1153 | return 0; | |
1154 | } | |
0a4bc5e8 | 1155 | EXPORT_SYMBOL(sa1111_set_audio_rate); |
1da177e4 LT |
1156 | |
1157 | /** | |
1158 | * sa1111_get_audio_rate - get the audio sample rate | |
1159 | * @sadev: SA1111 SAC function block device | |
1160 | */ | |
1161 | int sa1111_get_audio_rate(struct sa1111_dev *sadev) | |
1162 | { | |
1163 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1164 | unsigned long div; | |
1165 | ||
1166 | if (sadev->devid != SA1111_DEVID_SAC) | |
1167 | return -EINVAL; | |
1168 | ||
1169 | div = sa1111_readl(sachip->base + SA1111_SKAUD) + 1; | |
1170 | ||
1171 | return __sa1111_pll_clock(sachip) / (256 * div); | |
1172 | } | |
0a4bc5e8 | 1173 | EXPORT_SYMBOL(sa1111_get_audio_rate); |
1da177e4 LT |
1174 | |
1175 | void sa1111_set_io_dir(struct sa1111_dev *sadev, | |
1176 | unsigned int bits, unsigned int dir, | |
1177 | unsigned int sleep_dir) | |
1178 | { | |
1179 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1180 | unsigned long flags; | |
1181 | unsigned int val; | |
1182 | void __iomem *gpio = sachip->base + SA1111_GPIO; | |
1183 | ||
1184 | #define MODIFY_BITS(port, mask, dir) \ | |
1185 | if (mask) { \ | |
1186 | val = sa1111_readl(port); \ | |
1187 | val &= ~(mask); \ | |
1188 | val |= (dir) & (mask); \ | |
1189 | sa1111_writel(val, port); \ | |
1190 | } | |
1191 | ||
1192 | spin_lock_irqsave(&sachip->lock, flags); | |
1193 | MODIFY_BITS(gpio + SA1111_GPIO_PADDR, bits & 15, dir); | |
1194 | MODIFY_BITS(gpio + SA1111_GPIO_PBDDR, (bits >> 8) & 255, dir >> 8); | |
1195 | MODIFY_BITS(gpio + SA1111_GPIO_PCDDR, (bits >> 16) & 255, dir >> 16); | |
1196 | ||
1197 | MODIFY_BITS(gpio + SA1111_GPIO_PASDR, bits & 15, sleep_dir); | |
1198 | MODIFY_BITS(gpio + SA1111_GPIO_PBSDR, (bits >> 8) & 255, sleep_dir >> 8); | |
1199 | MODIFY_BITS(gpio + SA1111_GPIO_PCSDR, (bits >> 16) & 255, sleep_dir >> 16); | |
1200 | spin_unlock_irqrestore(&sachip->lock, flags); | |
1201 | } | |
0a4bc5e8 | 1202 | EXPORT_SYMBOL(sa1111_set_io_dir); |
1da177e4 LT |
1203 | |
1204 | void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v) | |
1205 | { | |
1206 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1207 | unsigned long flags; | |
1208 | unsigned int val; | |
1209 | void __iomem *gpio = sachip->base + SA1111_GPIO; | |
1210 | ||
1211 | spin_lock_irqsave(&sachip->lock, flags); | |
1212 | MODIFY_BITS(gpio + SA1111_GPIO_PADWR, bits & 15, v); | |
1213 | MODIFY_BITS(gpio + SA1111_GPIO_PBDWR, (bits >> 8) & 255, v >> 8); | |
1214 | MODIFY_BITS(gpio + SA1111_GPIO_PCDWR, (bits >> 16) & 255, v >> 16); | |
1215 | spin_unlock_irqrestore(&sachip->lock, flags); | |
1216 | } | |
0a4bc5e8 | 1217 | EXPORT_SYMBOL(sa1111_set_io); |
1da177e4 LT |
1218 | |
1219 | void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v) | |
1220 | { | |
1221 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1222 | unsigned long flags; | |
1223 | unsigned int val; | |
1224 | void __iomem *gpio = sachip->base + SA1111_GPIO; | |
1225 | ||
1226 | spin_lock_irqsave(&sachip->lock, flags); | |
1227 | MODIFY_BITS(gpio + SA1111_GPIO_PASSR, bits & 15, v); | |
1228 | MODIFY_BITS(gpio + SA1111_GPIO_PBSSR, (bits >> 8) & 255, v >> 8); | |
1229 | MODIFY_BITS(gpio + SA1111_GPIO_PCSSR, (bits >> 16) & 255, v >> 16); | |
1230 | spin_unlock_irqrestore(&sachip->lock, flags); | |
1231 | } | |
0a4bc5e8 | 1232 | EXPORT_SYMBOL(sa1111_set_sleep_io); |
1da177e4 LT |
1233 | |
1234 | /* | |
1235 | * Individual device operations. | |
1236 | */ | |
1237 | ||
1238 | /** | |
1239 | * sa1111_enable_device - enable an on-chip SA1111 function block | |
1240 | * @sadev: SA1111 function block device to enable | |
1241 | */ | |
ae99ddbc | 1242 | int sa1111_enable_device(struct sa1111_dev *sadev) |
1da177e4 LT |
1243 | { |
1244 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1245 | unsigned long flags; | |
1246 | unsigned int val; | |
ae99ddbc | 1247 | int ret = 0; |
1da177e4 | 1248 | |
ae99ddbc RK |
1249 | if (sachip->pdata && sachip->pdata->enable) |
1250 | ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid); | |
1251 | ||
1252 | if (ret == 0) { | |
1253 | spin_lock_irqsave(&sachip->lock, flags); | |
1254 | val = sa1111_readl(sachip->base + SA1111_SKPCR); | |
1255 | sa1111_writel(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR); | |
1256 | spin_unlock_irqrestore(&sachip->lock, flags); | |
1257 | } | |
1258 | return ret; | |
1da177e4 | 1259 | } |
0a4bc5e8 | 1260 | EXPORT_SYMBOL(sa1111_enable_device); |
1da177e4 LT |
1261 | |
1262 | /** | |
1263 | * sa1111_disable_device - disable an on-chip SA1111 function block | |
1264 | * @sadev: SA1111 function block device to disable | |
1265 | */ | |
1266 | void sa1111_disable_device(struct sa1111_dev *sadev) | |
1267 | { | |
1268 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1269 | unsigned long flags; | |
1270 | unsigned int val; | |
1271 | ||
1272 | spin_lock_irqsave(&sachip->lock, flags); | |
1273 | val = sa1111_readl(sachip->base + SA1111_SKPCR); | |
1274 | sa1111_writel(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR); | |
1275 | spin_unlock_irqrestore(&sachip->lock, flags); | |
ae99ddbc RK |
1276 | |
1277 | if (sachip->pdata && sachip->pdata->disable) | |
1278 | sachip->pdata->disable(sachip->pdata->data, sadev->devid); | |
1da177e4 | 1279 | } |
0a4bc5e8 | 1280 | EXPORT_SYMBOL(sa1111_disable_device); |
1da177e4 LT |
1281 | |
1282 | /* | |
1283 | * SA1111 "Register Access Bus." | |
1284 | * | |
1285 | * We model this as a regular bus type, and hang devices directly | |
1286 | * off this. | |
1287 | */ | |
1288 | static int sa1111_match(struct device *_dev, struct device_driver *_drv) | |
1289 | { | |
1290 | struct sa1111_dev *dev = SA1111_DEV(_dev); | |
1291 | struct sa1111_driver *drv = SA1111_DRV(_drv); | |
1292 | ||
e5c0fc41 | 1293 | return dev->devid & drv->devid; |
1da177e4 LT |
1294 | } |
1295 | ||
1296 | static int sa1111_bus_suspend(struct device *dev, pm_message_t state) | |
1297 | { | |
1298 | struct sa1111_dev *sadev = SA1111_DEV(dev); | |
1299 | struct sa1111_driver *drv = SA1111_DRV(dev->driver); | |
1300 | int ret = 0; | |
1301 | ||
1302 | if (drv && drv->suspend) | |
1303 | ret = drv->suspend(sadev, state); | |
1304 | return ret; | |
1305 | } | |
1306 | ||
1307 | static int sa1111_bus_resume(struct device *dev) | |
1308 | { | |
1309 | struct sa1111_dev *sadev = SA1111_DEV(dev); | |
1310 | struct sa1111_driver *drv = SA1111_DRV(dev->driver); | |
1311 | int ret = 0; | |
1312 | ||
1313 | if (drv && drv->resume) | |
1314 | ret = drv->resume(sadev); | |
1315 | return ret; | |
1316 | } | |
1317 | ||
6bd72f05 RK |
1318 | static void sa1111_bus_shutdown(struct device *dev) |
1319 | { | |
1320 | struct sa1111_driver *drv = SA1111_DRV(dev->driver); | |
1321 | ||
1322 | if (drv && drv->shutdown) | |
1323 | drv->shutdown(SA1111_DEV(dev)); | |
1324 | } | |
1325 | ||
1da177e4 LT |
1326 | static int sa1111_bus_probe(struct device *dev) |
1327 | { | |
1328 | struct sa1111_dev *sadev = SA1111_DEV(dev); | |
1329 | struct sa1111_driver *drv = SA1111_DRV(dev->driver); | |
1330 | int ret = -ENODEV; | |
1331 | ||
1332 | if (drv->probe) | |
1333 | ret = drv->probe(sadev); | |
1334 | return ret; | |
1335 | } | |
1336 | ||
1337 | static int sa1111_bus_remove(struct device *dev) | |
1338 | { | |
1339 | struct sa1111_dev *sadev = SA1111_DEV(dev); | |
1340 | struct sa1111_driver *drv = SA1111_DRV(dev->driver); | |
1341 | int ret = 0; | |
1342 | ||
1343 | if (drv->remove) | |
1344 | ret = drv->remove(sadev); | |
1345 | return ret; | |
1346 | } | |
1347 | ||
1348 | struct bus_type sa1111_bus_type = { | |
1349 | .name = "sa1111-rab", | |
1350 | .match = sa1111_match, | |
2876ba43 RK |
1351 | .probe = sa1111_bus_probe, |
1352 | .remove = sa1111_bus_remove, | |
1da177e4 LT |
1353 | .suspend = sa1111_bus_suspend, |
1354 | .resume = sa1111_bus_resume, | |
6bd72f05 | 1355 | .shutdown = sa1111_bus_shutdown, |
1da177e4 | 1356 | }; |
0a4bc5e8 | 1357 | EXPORT_SYMBOL(sa1111_bus_type); |
1da177e4 LT |
1358 | |
1359 | int sa1111_driver_register(struct sa1111_driver *driver) | |
1360 | { | |
1da177e4 LT |
1361 | driver->drv.bus = &sa1111_bus_type; |
1362 | return driver_register(&driver->drv); | |
1363 | } | |
0a4bc5e8 | 1364 | EXPORT_SYMBOL(sa1111_driver_register); |
1da177e4 LT |
1365 | |
1366 | void sa1111_driver_unregister(struct sa1111_driver *driver) | |
1367 | { | |
1368 | driver_unregister(&driver->drv); | |
1369 | } | |
0a4bc5e8 | 1370 | EXPORT_SYMBOL(sa1111_driver_unregister); |
1da177e4 | 1371 | |
09a2ba2f RK |
1372 | #ifdef CONFIG_DMABOUNCE |
1373 | /* | |
1374 | * According to the "Intel StrongARM SA-1111 Microprocessor Companion | |
1375 | * Chip Specification Update" (June 2000), erratum #7, there is a | |
1376 | * significant bug in the SA1111 SDRAM shared memory controller. If | |
1377 | * an access to a region of memory above 1MB relative to the bank base, | |
1378 | * it is important that address bit 10 _NOT_ be asserted. Depending | |
1379 | * on the configuration of the RAM, bit 10 may correspond to one | |
1380 | * of several different (processor-relative) address bits. | |
1381 | * | |
1382 | * This routine only identifies whether or not a given DMA address | |
1383 | * is susceptible to the bug. | |
1384 | * | |
1385 | * This should only get called for sa1111_device types due to the | |
1386 | * way we configure our device dma_masks. | |
1387 | */ | |
1388 | static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) | |
1389 | { | |
1390 | /* | |
1391 | * Section 4.6 of the "Intel StrongARM SA-1111 Development Module | |
1392 | * User's Guide" mentions that jumpers R51 and R52 control the | |
1393 | * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or | |
1394 | * SDRAM bank 1 on Neponset). The default configuration selects | |
1395 | * Assabet, so any address in bank 1 is necessarily invalid. | |
1396 | */ | |
1397 | return (machine_is_assabet() || machine_is_pfs168()) && | |
1398 | (addr >= 0xc8000000 || (addr + size) >= 0xc8000000); | |
1399 | } | |
1400 | ||
1401 | static int sa1111_notifier_call(struct notifier_block *n, unsigned long action, | |
1402 | void *data) | |
1403 | { | |
1404 | struct sa1111_dev *dev = SA1111_DEV(data); | |
1405 | ||
1406 | switch (action) { | |
1407 | case BUS_NOTIFY_ADD_DEVICE: | |
1408 | if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL) { | |
1409 | int ret = dmabounce_register_dev(&dev->dev, 1024, 4096, | |
1410 | sa1111_needs_bounce); | |
1411 | if (ret) | |
1412 | dev_err(&dev->dev, "failed to register with dmabounce: %d\n", ret); | |
1413 | } | |
1414 | break; | |
1415 | ||
1416 | case BUS_NOTIFY_DEL_DEVICE: | |
1417 | if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL) | |
1418 | dmabounce_unregister_dev(&dev->dev); | |
1419 | break; | |
1420 | } | |
1421 | return NOTIFY_OK; | |
1422 | } | |
1423 | ||
1424 | static struct notifier_block sa1111_bus_notifier = { | |
1425 | .notifier_call = sa1111_notifier_call, | |
1426 | }; | |
1427 | #endif | |
1428 | ||
1da177e4 LT |
1429 | static int __init sa1111_init(void) |
1430 | { | |
1431 | int ret = bus_register(&sa1111_bus_type); | |
09a2ba2f RK |
1432 | #ifdef CONFIG_DMABOUNCE |
1433 | if (ret == 0) | |
1434 | bus_register_notifier(&sa1111_bus_type, &sa1111_bus_notifier); | |
1435 | #endif | |
1da177e4 | 1436 | if (ret == 0) |
3ae5eaec | 1437 | platform_driver_register(&sa1111_device_driver); |
1da177e4 LT |
1438 | return ret; |
1439 | } | |
1440 | ||
1441 | static void __exit sa1111_exit(void) | |
1442 | { | |
3ae5eaec | 1443 | platform_driver_unregister(&sa1111_device_driver); |
09a2ba2f RK |
1444 | #ifdef CONFIG_DMABOUNCE |
1445 | bus_unregister_notifier(&sa1111_bus_type, &sa1111_bus_notifier); | |
1446 | #endif | |
1da177e4 LT |
1447 | bus_unregister(&sa1111_bus_type); |
1448 | } | |
1449 | ||
72724382 | 1450 | subsys_initcall(sa1111_init); |
1da177e4 LT |
1451 | module_exit(sa1111_exit); |
1452 | ||
1453 | MODULE_DESCRIPTION("Intel Corporation SA1111 core driver"); | |
1454 | MODULE_LICENSE("GPL"); |