[linux-2.6-block.git] / arch / arm / boot / dts / zynq-7000.dtsi

/*
 *  Copyright (C) 2011 - 2014 Xilinx
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "xlnx,zynq-7000";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			clocks = <&clkc 3>;
			clock-latency = <1000>;
			cpu0-supply = <&regulator_vccpint>;
			operating-points = <
				/* kHz    uV */
				666667  1000000
				333334  1000000
			>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			clocks = <&clkc 3>;
		};
	};

	fpga_full: fpga-full {
		compatible = "fpga-region";
		fpga-mgr = <&devcfg>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
	};

	pmu@f8891000 {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 5 4>, <0 6 4>;
		interrupt-parent = <&intc>;
		reg = <0xf8891000 0x1000>,
		      <0xf8893000 0x1000>;
	};

	regulator_vccpint: fixedregulator {
		compatible = "regulator-fixed";
		regulator-name = "VCCPINT";
		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <1000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	amba: amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;

		adc: adc@f8007100 {
			compatible = "xlnx,zynq-xadc-1.00.a";
			reg = <0xf8007100 0x20>;
			interrupts = <0 7 4>;
			interrupt-parent = <&intc>;
			clocks = <&clkc 12>;
		};

		can0: can@e0008000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <&clkc 19>, <&clkc 36>;
			clock-names = "can_clk", "pclk";
			reg = <0xe0008000 0x1000>;
			interrupts = <0 28 4>;
			interrupt-parent = <&intc>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		can1: can@e0009000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <&clkc 20>, <&clkc 37>;
			clock-names = "can_clk", "pclk";
			reg = <0xe0009000 0x1000>;
			interrupts = <0 51 4>;
			interrupt-parent = <&intc>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		gpio0: gpio@e000a000 {
			compatible = "xlnx,zynq-gpio-1.0";
			#gpio-cells = <2>;
			clocks = <&clkc 42>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupts = <0 20 4>;
			reg = <0xe000a000 0x1000>;
		};

		i2c0: i2c@e0004000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <&clkc 38>;
			interrupt-parent = <&intc>;
			interrupts = <0 25 4>;
			reg = <0xe0004000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@e0005000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <&clkc 39>;
			interrupt-parent = <&intc>;
			interrupts = <0 48 4>;
			reg = <0xe0005000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		intc: interrupt-controller@f8f01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0xF8F01000 0x1000>,
			      <0xF8F00100 0x100>;
		};

		L2: cache-controller@f8f02000 {
			compatible = "arm,pl310-cache";
			reg = <0xF8F02000 0x1000>;
			interrupts = <0 2 4>;
			arm,data-latency = <3 2 2>;
			arm,tag-latency = <2 2 2>;
			cache-unified;
			cache-level = <2>;
		};

		mc: memory-controller@f8006000 {
			compatible = "xlnx,zynq-ddrc-a05";
			reg = <0xf8006000 0x1000>;
		};

		uart0: serial@e0000000 {
			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
			status = "disabled";
			clocks = <&clkc 23>, <&clkc 40>;
			clock-names = "uart_clk", "pclk";
			reg = <0xE0000000 0x1000>;
			interrupts = <0 27 4>;
		};

		uart1: serial@e0001000 {
			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
			status = "disabled";
			clocks = <&clkc 24>, <&clkc 41>;
			clock-names = "uart_clk", "pclk";
			reg = <0xE0001000 0x1000>;
			interrupts = <0 50 4>;
		};

		spi0: spi@e0006000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0006000 0x1000>;
			status = "disabled";
			interrupt-parent = <&intc>;
			interrupts = <0 26 4>;
			clocks = <&clkc 25>, <&clkc 34>;
			clock-names = "ref_clk", "pclk";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@e0007000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0007000 0x1000>;
			status = "disabled";
			interrupt-parent = <&intc>;
			interrupts = <0 49 4>;
			clocks = <&clkc 26>, <&clkc 35>;
			clock-names = "ref_clk", "pclk";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gem0: ethernet@e000b000 {
			compatible = "cdns,zynq-gem", "cdns,gem";
			reg = <0xe000b000 0x1000>;
			status = "disabled";
			interrupts = <0 22 4>;
			clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
			clock-names = "pclk", "hclk", "tx_clk";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gem1: ethernet@e000c000 {
			compatible = "cdns,zynq-gem", "cdns,gem";
			reg = <0xe000c000 0x1000>;
			status = "disabled";
			interrupts = <0 45 4>;
			clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
			clock-names = "pclk", "hclk", "tx_clk";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		sdhci0: sdhci@e0100000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&clkc 21>, <&clkc 32>;
			interrupt-parent = <&intc>;
			interrupts = <0 24 4>;
			reg = <0xe0100000 0x1000>;
		};

		sdhci1: sdhci@e0101000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&clkc 22>, <&clkc 33>;
			interrupt-parent = <&intc>;
			interrupts = <0 47 4>;
			reg = <0xe0101000 0x1000>;
		};

		slcr: slcr@f8000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
			reg = <0xF8000000 0x1000>;
			ranges;
			clkc: clkc@100 {
				#clock-cells = <1>;
				compatible = "xlnx,ps7-clkc";
				fclk-enable = <0>;
				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
						"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
						"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
						"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
						"dma", "usb0_aper", "usb1_aper", "gem0_aper",
						"gem1_aper", "sdio0_aper", "sdio1_aper",
						"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
						"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
						"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
						"dbg_trc", "dbg_apb";
				reg = <0x100 0x100>;
			};

			rstc: rstc@200 {
				compatible = "xlnx,zynq-reset";
				reg = <0x200 0x48>;
				#reset-cells = <1>;
				syscon = <&slcr>;
			};

			pinctrl0: pinctrl@700 {
				compatible = "xlnx,pinctrl-zynq";
				reg = <0x700 0x200>;
				syscon = <&slcr>;
			};
		};

		dmac_s: dmac@f8003000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xf8003000 0x1000>;
			interrupt-parent = <&intc>;
			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
				"dma4", "dma5", "dma6", "dma7";
			interrupts = <0 13 4>,
			             <0 14 4>, <0 15 4>,
			             <0 16 4>, <0 17 4>,
			             <0 40 4>, <0 41 4>,
			             <0 42 4>, <0 43 4>;
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <4>;
			clocks = <&clkc 27>;
			clock-names = "apb_pclk";
		};

		devcfg: devcfg@f8007000 {
			compatible = "xlnx,zynq-devcfg-1.0";
			reg = <0xf8007000 0x100>;
			interrupt-parent = <&intc>;
			interrupts = <0 8 4>;
			clocks = <&clkc 12>;
			clock-names = "ref_clk";
			syscon = <&slcr>;
		};

		global_timer: timer@f8f00200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0xf8f00200 0x20>;
			interrupts = <1 11 0x301>;
			interrupt-parent = <&intc>;
			clocks = <&clkc 4>;
		};

		ttc0: timer@f8001000 {
			interrupt-parent = <&intc>;
			interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
			compatible = "cdns,ttc";
			clocks = <&clkc 6>;
			reg = <0xF8001000 0x1000>;
		};

		ttc1: timer@f8002000 {
			interrupt-parent = <&intc>;
			interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
			compatible = "cdns,ttc";
			clocks = <&clkc 6>;
			reg = <0xF8002000 0x1000>;
		};

		scutimer: timer@f8f00600 {
			interrupt-parent = <&intc>;
			interrupts = <1 13 0x301>;
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xf8f00600 0x20>;
			clocks = <&clkc 4>;
		};

		usb0: usb@e0002000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			status = "disabled";
			clocks = <&clkc 28>;
			interrupt-parent = <&intc>;
			interrupts = <0 21 4>;
			reg = <0xe0002000 0x1000>;
			phy_type = "ulpi";
		};

		usb1: usb@e0003000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			status = "disabled";
			clocks = <&clkc 29>;
			interrupt-parent = <&intc>;
			interrupts = <0 44 4>;
			reg = <0xe0003000 0x1000>;
			phy_type = "ulpi";
		};

		watchdog0: watchdog@f8005000 {
			clocks = <&clkc 45>;
			compatible = "cdns,wdt-r1p2";
			interrupt-parent = <&intc>;
			interrupts = <0 9 1>;
			reg = <0xf8005000 0x1000>;
			timeout-sec = <10>;
		};
	};
};
Commit	Line	Data
b85a3ef4	1	/*
f7b1e9b5	2	* Copyright (C) 2011 - 2014 Xilinx
b85a3ef4 JL	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
b85a3ef4	14	/ {
7fe91fcc MS	15	#address-cells = <1>;
7fe91fcc MS	16	#size-cells = <1>;
e06f1a9e	17	compatible = "xlnx,zynq-7000";
b85a3ef4	18
41e4cdb9 SB	19	cpus {
	20	#address-cells = <1>;
	21	#size-cells = <0>;
	22
400b6a0c	23	cpu0: cpu@0 {
41e4cdb9 SB	24	compatible = "arm,cortex-a9";
	25	device_type = "cpu";
	26	reg = <0>;
	27	clocks = <&clkc 3>;
b2bf5d48	28	clock-latency = <1000>;
e1e22df1	29	cpu0-supply = <&regulator_vccpint>;
cd325295 SB	30	operating-points = <
	31	/* kHz uV */
	32	666667 1000000
	33	333334 1000000
cd325295	34	>;
41e4cdb9 SB	35	};
41e4cdb9 SB	36
400b6a0c	37	cpu1: cpu@1 {
41e4cdb9 SB	38	compatible = "arm,cortex-a9";
	39	device_type = "cpu";
	40	reg = <1>;
	41	clocks = <&clkc 3>;
	42	};
	43	};
	44
3c220bf4 MS	45	fpga_full: fpga-full {
	46	compatible = "fpga-region";
	47	fpga-mgr = <&devcfg>;
	48	#address-cells = <1>;
	49	#size-cells = <1>;
	50	ranges;
	51	};
	52
da457d57	53	pmu@f8891000 {
268a8200 MS	54	compatible = "arm,cortex-a9-pmu";
	55	interrupts = <0 5 4>, <0 6 4>;
	56	interrupt-parent = <&intc>;
995966cc MS	57	reg = <0xf8891000 0x1000>,
995966cc MS	58	<0xf8893000 0x1000>;
268a8200 MS	59	};
268a8200 MS	60
da457d57	61	regulator_vccpint: fixedregulator {
e1e22df1 SB	62	compatible = "regulator-fixed";
	63	regulator-name = "VCCPINT";
	64	regulator-min-microvolt = <1000000>;
	65	regulator-max-microvolt = <1000000>;
	66	regulator-boot-on;
	67	regulator-always-on;
	68	};
	69
6835fe48	70	amba: amba {
b85a3ef4 JL	71	compatible = "simple-bus";
	72	#address-cells = <1>;
	73	#size-cells = <1>;
e06f1a9e	74	interrupt-parent = <&intc>;
b85a3ef4 JL	75	ranges;
b85a3ef4 JL	76
70472c43	77	adc: adc@f8007100 {
21555604 SB	78	compatible = "xlnx,zynq-xadc-1.00.a";
	79	reg = <0xf8007100 0x20>;
	80	interrupts = <0 7 4>;
	81	interrupt-parent = <&intc>;
	82	clocks = <&clkc 12>;
fdf26183 MS	83	};
	84
	85	can0: can@e0008000 {
	86	compatible = "xlnx,zynq-can-1.0";
	87	status = "disabled";
	88	clocks = <&clkc 19>, <&clkc 36>;
	89	clock-names = "can_clk", "pclk";
	90	reg = <0xe0008000 0x1000>;
	91	interrupts = <0 28 4>;
	92	interrupt-parent = <&intc>;
	93	tx-fifo-depth = <0x40>;
	94	rx-fifo-depth = <0x40>;
	95	};
	96
	97	can1: can@e0009000 {
	98	compatible = "xlnx,zynq-can-1.0";
	99	status = "disabled";
	100	clocks = <&clkc 20>, <&clkc 37>;
	101	clock-names = "can_clk", "pclk";
	102	reg = <0xe0009000 0x1000>;
	103	interrupts = <0 51 4>;
	104	interrupt-parent = <&intc>;
	105	tx-fifo-depth = <0x40>;
	106	rx-fifo-depth = <0x40>;
	107	};
e0a5c552 SB	108
	109	gpio0: gpio@e000a000 {
	110	compatible = "xlnx,zynq-gpio-1.0";
	111	#gpio-cells = <2>;
	112	clocks = <&clkc 42>;
	113	gpio-controller;
e57f6e5e SB	114	interrupt-controller;
e57f6e5e SB	115	#interrupt-cells = <2>;
e0a5c552 SB	116	interrupt-parent = <&intc>;
	117	interrupts = <0 20 4>;
	118	reg = <0xe000a000 0x1000>;
21555604 SB	119	};
21555604 SB	120
f7b1e9b5	121	i2c0: i2c@e0004000 {
0f6faa3f SB	122	compatible = "cdns,i2c-r1p10";
	123	status = "disabled";
	124	clocks = <&clkc 38>;
	125	interrupt-parent = <&intc>;
	126	interrupts = <0 25 4>;
	127	reg = <0xe0004000 0x1000>;
	128	#address-cells = <1>;
	129	#size-cells = <0>;
	130	};
	131
f7b1e9b5	132	i2c1: i2c@e0005000 {
0f6faa3f SB	133	compatible = "cdns,i2c-r1p10";
	134	status = "disabled";
	135	clocks = <&clkc 39>;
	136	interrupt-parent = <&intc>;
	137	interrupts = <0 48 4>;
	138	reg = <0xe0005000 0x1000>;
	139	#address-cells = <1>;
	140	#size-cells = <0>;
	141	};
	142
b85a3ef4	143	intc: interrupt-controller@f8f01000 {
f447ed2d JC	144	compatible = "arm,cortex-a9-gic";
f447ed2d JC	145	#interrupt-cells = <3>;
b85a3ef4	146	interrupt-controller;
f447ed2d JC	147	reg = <0xF8F01000 0x1000>,
f447ed2d JC	148	<0xF8F00100 0x100>;
b85a3ef4 JL	149	};
b85a3ef4 JL	150
8abef06b	151	L2: cache-controller@f8f02000 {
0fcfdbca JC	152	compatible = "arm,pl310-cache";
0fcfdbca JC	153	reg = <0xF8F02000 0x1000>;
6de663fe	154	interrupts = <0 2 4>;
39c41df9 SB	155	arm,data-latency = <3 2 2>;
39c41df9 SB	156	arm,tag-latency = <2 2 2>;
0fcfdbca JC	157	cache-unified;
	158	cache-level = <2>;
	159	};
	160
6c7ba415	161	mc: memory-controller@f8006000 {
36ad5ae6 SB	162	compatible = "xlnx,zynq-ddrc-a05";
36ad5ae6 SB	163	reg = <0xf8006000 0x1000>;
2329efbb	164	};
36ad5ae6	165
f7b1e9b5	166	uart0: serial@e0000000 {
8fe9346b	167	compatible = "xlnx,xuartps", "cdns,uart-r1p8";
ec11ebcf	168	status = "disabled";
30e1e285	169	clocks = <&clkc 23>, <&clkc 40>;
8fe9346b	170	clock-names = "uart_clk", "pclk";
b85a3ef4	171	reg = <0xE0000000 0x1000>;
f447ed2d	172	interrupts = <0 27 4>;
b85a3ef4	173	};
78d6785d	174
f7b1e9b5	175	uart1: serial@e0001000 {
8fe9346b	176	compatible = "xlnx,xuartps", "cdns,uart-r1p8";
ec11ebcf	177	status = "disabled";
30e1e285	178	clocks = <&clkc 24>, <&clkc 41>;
8fe9346b	179	clock-names = "uart_clk", "pclk";
78d6785d JC	180	reg = <0xE0001000 0x1000>;
78d6785d JC	181	interrupts = <0 50 4>;
78d6785d	182	};
0f586fbf	183
f07ab7a0 AF	184	spi0: spi@e0006000 {
	185	compatible = "xlnx,zynq-spi-r1p6";
	186	reg = <0xe0006000 0x1000>;
	187	status = "disabled";
	188	interrupt-parent = <&intc>;
	189	interrupts = <0 26 4>;
	190	clocks = <&clkc 25>, <&clkc 34>;
	191	clock-names = "ref_clk", "pclk";
	192	#address-cells = <1>;
	193	#size-cells = <0>;
	194	};
	195
	196	spi1: spi@e0007000 {
	197	compatible = "xlnx,zynq-spi-r1p6";
	198	reg = <0xe0007000 0x1000>;
	199	status = "disabled";
	200	interrupt-parent = <&intc>;
	201	interrupts = <0 49 4>;
	202	clocks = <&clkc 26>, <&clkc 35>;
	203	clock-names = "ref_clk", "pclk";
	204	#address-cells = <1>;
	205	#size-cells = <0>;
	206	};
	207
982264c3	208	gem0: ethernet@e000b000 {
4481b18b	209	compatible = "cdns,zynq-gem", "cdns,gem";
b5241fb1	210	reg = <0xe000b000 0x1000>;
982264c3 ST	211	status = "disabled";
	212	interrupts = <0 22 4>;
	213	clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
	214	clock-names = "pclk", "hclk", "tx_clk";
edbd35e7 SB	215	#address-cells = <1>;
edbd35e7 SB	216	#size-cells = <0>;
982264c3 ST	217	};
	218
	219	gem1: ethernet@e000c000 {
4481b18b	220	compatible = "cdns,zynq-gem", "cdns,gem";
b5241fb1	221	reg = <0xe000c000 0x1000>;
982264c3 ST	222	status = "disabled";
	223	interrupts = <0 45 4>;
	224	clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
	225	clock-names = "pclk", "hclk", "tx_clk";
edbd35e7 SB	226	#address-cells = <1>;
edbd35e7 SB	227	#size-cells = <0>;
982264c3 ST	228	};
982264c3 ST	229
f7b1e9b5	230	sdhci0: sdhci@e0100000 {
3f7c7302 SB	231	compatible = "arasan,sdhci-8.9a";
	232	status = "disabled";
	233	clock-names = "clk_xin", "clk_ahb";
	234	clocks = <&clkc 21>, <&clkc 32>;
	235	interrupt-parent = <&intc>;
	236	interrupts = <0 24 4>;
	237	reg = <0xe0100000 0x1000>;
e65b1585	238	};
3f7c7302	239
f7b1e9b5	240	sdhci1: sdhci@e0101000 {
3f7c7302 SB	241	compatible = "arasan,sdhci-8.9a";
	242	status = "disabled";
	243	clock-names = "clk_xin", "clk_ahb";
	244	clocks = <&clkc 22>, <&clkc 33>;
	245	interrupt-parent = <&intc>;
	246	interrupts = <0 47 4>;
	247	reg = <0xe0101000 0x1000>;
e65b1585	248	};
3f7c7302	249
0f586fbf	250	slcr: slcr@f8000000 {
b0504e39 MS	251	#address-cells = <1>;
b0504e39 MS	252	#size-cells = <1>;
bc5ba9b9	253	compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
0f586fbf	254	reg = <0xF8000000 0x1000>;
b0504e39 MS	255	ranges;
	256	clkc: clkc@100 {
	257	#clock-cells = <1>;
	258	compatible = "xlnx,ps7-clkc";
b0504e39 MS	259	fclk-enable = <0>;
	260	clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
	261	"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
	262	"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
	263	"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
	264	"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
	265	"dma", "usb0_aper", "usb1_aper", "gem0_aper",
	266	"gem1_aper", "sdio0_aper", "sdio1_aper",
	267	"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
	268	"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
	269	"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
	270	"dbg_trc", "dbg_apb";
	271	reg = <0x100 0x100>;
0f586fbf	272	};
f52948ea	273
99650c25 MF	274	rstc: rstc@200 {
	275	compatible = "xlnx,zynq-reset";
	276	reg = <0x200 0x48>;
	277	#reset-cells = <1>;
	278	syscon = <&slcr>;
	279	};
	280
f52948ea SB	281	pinctrl0: pinctrl@700 {
	282	compatible = "xlnx,pinctrl-zynq";
	283	reg = <0x700 0x200>;
	284	syscon = <&slcr>;
	285	};
0f586fbf	286	};
91dc985c	287
fbb4add8 AF	288	dmac_s: dmac@f8003000 {
	289	compatible = "arm,pl330", "arm,primecell";
	290	reg = <0xf8003000 0x1000>;
	291	interrupt-parent = <&intc>;
41683583 MS	292	interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
41683583 MS	293	"dma4", "dma5", "dma6", "dma7";
fbb4add8 AF	294	interrupts = <0 13 4>,
	295	<0 14 4>, <0 15 4>,
	296	<0 16 4>, <0 17 4>,
	297	<0 40 4>, <0 41 4>,
	298	<0 42 4>, <0 43 4>;
	299	#dma-cells = <1>;
	300	#dma-channels = <8>;
	301	#dma-requests = <4>;
	302	clocks = <&clkc 27>;
	303	clock-names = "apb_pclk";
	304	};
	305
00f7dc63 MS	306	devcfg: devcfg@f8007000 {
	307	compatible = "xlnx,zynq-devcfg-1.0";
	308	reg = <0xf8007000 0x100>;
20598490 MF	309	interrupt-parent = <&intc>;
	310	interrupts = <0 8 4>;
	311	clocks = <&clkc 12>;
	312	clock-names = "ref_clk";
	313	syscon = <&slcr>;
e65b1585	314	};
00f7dc63	315
fa94bd57 SB	316	global_timer: timer@f8f00200 {
	317	compatible = "arm,cortex-a9-global-timer";
	318	reg = <0xf8f00200 0x20>;
	319	interrupts = <1 11 0x301>;
	320	interrupt-parent = <&intc>;
	321	clocks = <&clkc 4>;
	322	};
	323
f7b1e9b5	324	ttc0: timer@f8001000 {
e932900a	325	interrupt-parent = <&intc>;
f7b1e9b5	326	interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
e932900a	327	compatible = "cdns,ttc";
30e1e285	328	clocks = <&clkc 6>;
91dc985c	329	reg = <0xF8001000 0x1000>;
91dc985c JC	330	};
91dc985c JC	331
f7b1e9b5	332	ttc1: timer@f8002000 {
e932900a	333	interrupt-parent = <&intc>;
f7b1e9b5	334	interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
e932900a	335	compatible = "cdns,ttc";
30e1e285	336	clocks = <&clkc 6>;
91dc985c	337	reg = <0xF8002000 0x1000>;
91dc985c	338	};
f7b1e9b5 SB	339
f7b1e9b5 SB	340	scutimer: timer@f8f00600 {
2f34e0a5	341	interrupt-parent = <&intc>;
f7b1e9b5	342	interrupts = <1 13 0x301>;
2f34e0a5	343	compatible = "arm,cortex-a9-twd-timer";
f7b1e9b5	344	reg = <0xf8f00600 0x20>;
30e1e285	345	clocks = <&clkc 4>;
e65b1585	346	};
6714297b	347
1643b316 SB	348	usb0: usb@e0002000 {
	349	compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
	350	status = "disabled";
	351	clocks = <&clkc 28>;
	352	interrupt-parent = <&intc>;
	353	interrupts = <0 21 4>;
	354	reg = <0xe0002000 0x1000>;
	355	phy_type = "ulpi";
	356	};
	357
	358	usb1: usb@e0003000 {
	359	compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
	360	status = "disabled";
	361	clocks = <&clkc 29>;
	362	interrupt-parent = <&intc>;
	363	interrupts = <0 44 4>;
	364	reg = <0xe0003000 0x1000>;
	365	phy_type = "ulpi";
	366	};
	367
6714297b MS	368	watchdog0: watchdog@f8005000 {
6714297b MS	369	clocks = <&clkc 45>;
8f63a0ba	370	compatible = "cdns,wdt-r1p2";
6714297b MS	371	interrupt-parent = <&intc>;
	372	interrupts = <0 9 1>;
	373	reg = <0xf8005000 0x1000>;
6714297b MS	374	timeout-sec = <10>;
6714297b MS	375	};
b85a3ef4 JL	376	};
b85a3ef4 JL	377	};