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def4d6c0 TP |
1 | /* |
2 | * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | |
5 | * | |
6 | * Licensed under GPLv2 or later | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
10 | ||
11 | / { | |
12 | compatible = "wm,wm8850"; | |
13 | ||
7ec13d42 TP |
14 | cpus { |
15 | #address-cells = <1>; | |
16 | #size-cells = <0>; | |
17 | ||
18 | cpu@0 { | |
19 | device_type = "cpu"; | |
20 | compatible = "arm,cortex-a9"; | |
21 | reg = <0x0>; | |
22 | }; | |
23 | }; | |
24 | ||
def4d6c0 TP |
25 | aliases { |
26 | serial0 = &uart0; | |
27 | serial1 = &uart1; | |
28 | serial2 = &uart2; | |
29 | serial3 = &uart3; | |
30 | }; | |
31 | ||
32 | soc { | |
33 | #address-cells = <1>; | |
34 | #size-cells = <1>; | |
35 | compatible = "simple-bus"; | |
36 | ranges; | |
37 | interrupt-parent = <&intc0>; | |
38 | ||
39 | intc0: interrupt-controller@d8140000 { | |
40 | compatible = "via,vt8500-intc"; | |
41 | interrupt-controller; | |
42 | reg = <0xd8140000 0x10000>; | |
43 | #interrupt-cells = <1>; | |
44 | }; | |
45 | ||
46 | /* Secondary IC cascaded to intc0 */ | |
47 | intc1: interrupt-controller@d8150000 { | |
48 | compatible = "via,vt8500-intc"; | |
49 | interrupt-controller; | |
50 | #interrupt-cells = <1>; | |
51 | reg = <0xD8150000 0x10000>; | |
52 | interrupts = <56 57 58 59 60 61 62 63>; | |
53 | }; | |
54 | ||
649a59cf TP |
55 | pinctrl: pinctrl@d8110000 { |
56 | compatible = "wm,wm8850-pinctrl"; | |
def4d6c0 | 57 | reg = <0xd8110000 0x10000>; |
649a59cf TP |
58 | interrupt-controller; |
59 | #interrupt-cells = <2>; | |
60 | gpio-controller; | |
61 | #gpio-cells = <2>; | |
def4d6c0 TP |
62 | }; |
63 | ||
64 | pmc@d8130000 { | |
65 | compatible = "via,vt8500-pmc"; | |
66 | reg = <0xd8130000 0x1000>; | |
67 | ||
68 | clocks { | |
69 | #address-cells = <1>; | |
70 | #size-cells = <0>; | |
71 | ||
72 | ref25: ref25M { | |
73 | #clock-cells = <0>; | |
74 | compatible = "fixed-clock"; | |
75 | clock-frequency = <25000000>; | |
76 | }; | |
77 | ||
78 | ref24: ref24M { | |
79 | #clock-cells = <0>; | |
80 | compatible = "fixed-clock"; | |
81 | clock-frequency = <24000000>; | |
82 | }; | |
83 | ||
84 | plla: plla { | |
85 | #clock-cells = <0>; | |
86 | compatible = "wm,wm8750-pll-clock"; | |
87 | clocks = <&ref25>; | |
88 | reg = <0x200>; | |
89 | }; | |
90 | ||
91 | pllb: pllb { | |
92 | #clock-cells = <0>; | |
93 | compatible = "wm,wm8750-pll-clock"; | |
94 | clocks = <&ref25>; | |
95 | reg = <0x204>; | |
96 | }; | |
97 | ||
98 | clkuart0: uart0 { | |
99 | #clock-cells = <0>; | |
100 | compatible = "via,vt8500-device-clock"; | |
101 | clocks = <&ref24>; | |
102 | enable-reg = <0x254>; | |
103 | enable-bit = <24>; | |
104 | }; | |
105 | ||
106 | clkuart1: uart1 { | |
107 | #clock-cells = <0>; | |
108 | compatible = "via,vt8500-device-clock"; | |
109 | clocks = <&ref24>; | |
110 | enable-reg = <0x254>; | |
111 | enable-bit = <25>; | |
112 | }; | |
113 | ||
114 | clkuart2: uart2 { | |
115 | #clock-cells = <0>; | |
116 | compatible = "via,vt8500-device-clock"; | |
117 | clocks = <&ref24>; | |
118 | enable-reg = <0x254>; | |
119 | enable-bit = <26>; | |
120 | }; | |
121 | ||
122 | clkuart3: uart3 { | |
123 | #clock-cells = <0>; | |
124 | compatible = "via,vt8500-device-clock"; | |
125 | clocks = <&ref24>; | |
126 | enable-reg = <0x254>; | |
127 | enable-bit = <27>; | |
128 | }; | |
129 | ||
130 | clkpwm: pwm { | |
131 | #clock-cells = <0>; | |
132 | compatible = "via,vt8500-device-clock"; | |
133 | clocks = <&pllb>; | |
134 | divisor-reg = <0x350>; | |
135 | enable-reg = <0x250>; | |
136 | enable-bit = <17>; | |
137 | }; | |
138 | ||
139 | clksdhc: sdhc { | |
140 | #clock-cells = <0>; | |
141 | compatible = "via,vt8500-device-clock"; | |
142 | clocks = <&pllb>; | |
143 | divisor-reg = <0x330>; | |
144 | divisor-mask = <0x3f>; | |
145 | enable-reg = <0x250>; | |
146 | enable-bit = <0>; | |
147 | }; | |
148 | }; | |
149 | }; | |
150 | ||
7ab0a484 | 151 | fb: fb@d8051700 { |
def4d6c0 TP |
152 | compatible = "wm,wm8505-fb"; |
153 | reg = <0xd8051700 0x200>; | |
def4d6c0 TP |
154 | }; |
155 | ||
156 | ge_rops@d8050400 { | |
157 | compatible = "wm,prizm-ge-rops"; | |
158 | reg = <0xd8050400 0x100>; | |
159 | }; | |
160 | ||
161 | pwm: pwm@d8220000 { | |
162 | #pwm-cells = <3>; | |
163 | compatible = "via,vt8500-pwm"; | |
164 | reg = <0xd8220000 0x100>; | |
165 | clocks = <&clkpwm>; | |
166 | }; | |
167 | ||
168 | timer@d8130100 { | |
169 | compatible = "via,vt8500-timer"; | |
170 | reg = <0xd8130100 0x28>; | |
171 | interrupts = <36>; | |
172 | }; | |
173 | ||
174 | ehci@d8007900 { | |
175 | compatible = "via,vt8500-ehci"; | |
176 | reg = <0xd8007900 0x200>; | |
177 | interrupts = <26>; | |
178 | }; | |
179 | ||
180 | uhci@d8007b00 { | |
181 | compatible = "platform-uhci"; | |
182 | reg = <0xd8007b00 0x200>; | |
183 | interrupts = <26>; | |
184 | }; | |
185 | ||
186 | uhci@d8008d00 { | |
187 | compatible = "platform-uhci"; | |
188 | reg = <0xd8008d00 0x200>; | |
189 | interrupts = <26>; | |
190 | }; | |
191 | ||
55954f85 | 192 | uart0: serial@d8200000 { |
def4d6c0 TP |
193 | compatible = "via,vt8500-uart"; |
194 | reg = <0xd8200000 0x1040>; | |
195 | interrupts = <32>; | |
196 | clocks = <&clkuart0>; | |
55954f85 | 197 | status = "disabled"; |
def4d6c0 TP |
198 | }; |
199 | ||
55954f85 | 200 | uart1: serial@d82b0000 { |
def4d6c0 TP |
201 | compatible = "via,vt8500-uart"; |
202 | reg = <0xd82b0000 0x1040>; | |
203 | interrupts = <33>; | |
204 | clocks = <&clkuart1>; | |
55954f85 | 205 | status = "disabled"; |
def4d6c0 TP |
206 | }; |
207 | ||
55954f85 | 208 | uart2: serial@d8210000 { |
def4d6c0 TP |
209 | compatible = "via,vt8500-uart"; |
210 | reg = <0xd8210000 0x1040>; | |
211 | interrupts = <47>; | |
212 | clocks = <&clkuart2>; | |
55954f85 | 213 | status = "disabled"; |
def4d6c0 TP |
214 | }; |
215 | ||
55954f85 | 216 | uart3: serial@d82c0000 { |
def4d6c0 TP |
217 | compatible = "via,vt8500-uart"; |
218 | reg = <0xd82c0000 0x1040>; | |
219 | interrupts = <50>; | |
220 | clocks = <&clkuart3>; | |
55954f85 | 221 | status = "disabled"; |
def4d6c0 TP |
222 | }; |
223 | ||
224 | rtc@d8100000 { | |
225 | compatible = "via,vt8500-rtc"; | |
226 | reg = <0xd8100000 0x10000>; | |
227 | interrupts = <48>; | |
228 | }; | |
229 | ||
230 | sdhc@d800a000 { | |
231 | compatible = "wm,wm8505-sdhc"; | |
232 | reg = <0xd800a000 0x1000>; | |
233 | interrupts = <20 21>; | |
234 | clocks = <&clksdhc>; | |
235 | bus-width = <4>; | |
236 | sdon-inverted; | |
237 | }; | |
238 | }; | |
239 | }; |