[linux-2.6-block.git] / arch / arm / boot / dts / vf-colibri.dtsi

/*
 * Copyright 2014 Toradex AG
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/ {
	aliases {
		ethernet0 = &fec1;
		ethernet1 = &fec0;
	};

	bl: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_bl_on>;
		pwms = <&pwm0 0 5000000 0>;
		enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
		status = "disabled";
	};

	reg_module_3v3: regulator-module-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_module_3v3_avdd: regulator-module-3v3-avdd {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3_AVDD_AUDIO";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&adc0 {
	status = "okay";
	vref-supply = <&reg_module_3v3_avdd>;
};

&adc1 {
	status = "okay";
	vref-supply = <&reg_module_3v3_avdd>;
};

&can0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan0>;
	status = "disabled";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "disabled";
};

&clks {
	assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
			  <&clks VF610_CLK_ENET_TS_SEL>;
	assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
				 <&clks VF610_CLK_ENET_50M>;
};

&dspi1 {
	bus-num = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi1>;
};

&edma0 {
	status = "okay";
};

&edma1 {
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
	disable-wp;
};

&fec1 {
	phy-mode = "rmii";
	phy-supply = <&reg_module_3v3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
};

&i2c0 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
};

&nfc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	status = "okay";

	nand@0 {
		compatible = "fsl,vf610-nfc-nandcs";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		nand-bus-width = <8>;
		nand-ecc-mode = "hw";
		nand-ecc-strength = <32>;
		nand-ecc-step-size = <2048>;
		nand-on-flash-bbt;
	};
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm0>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
};

&usbdev0 {
	disable-over-current;
	status = "okay";
};

&usbh1 {
	disable-over-current;
	status = "okay";
};

&usbmisc0 {
	status = "okay";
};

&usbmisc1 {
	status = "okay";
};

&usbphy0 {
	status = "okay";
};

&usbphy1 {
	status = "okay";
};

&iomuxc {
	vf610-colibri {
		pinctrl_flexcan0: can0grp {
			fsl,pins = <
				VF610_PAD_PTB14__CAN0_RX	0x31F1
				VF610_PAD_PTB15__CAN0_TX	0x31F2
			>;
		};

		pinctrl_flexcan1: can1grp {
			fsl,pins = <
				VF610_PAD_PTB16__CAN1_RX	0x31F1
				VF610_PAD_PTB17__CAN1_TX	0x31F2
			>;
		};

		pinctrl_gpio_ext: gpio_ext {
			fsl,pins = <
				VF610_PAD_PTD10__GPIO_89	0x22ed /* EXT_IO_0 */
				VF610_PAD_PTD9__GPIO_88		0x22ed /* EXT_IO_1 */
				VF610_PAD_PTD26__GPIO_68	0x22ed /* EXT_IO_2 */
			>;
		};

		pinctrl_dcu0_1: dcu0grp_1 {
			fsl,pins = <
				VF610_PAD_PTE0__DCU0_HSYNC	0x1902
				VF610_PAD_PTE1__DCU0_VSYNC	0x1902
				VF610_PAD_PTE2__DCU0_PCLK	0x1902
				VF610_PAD_PTE4__DCU0_DE		0x1902
				VF610_PAD_PTE5__DCU0_R0		0x1902
				VF610_PAD_PTE6__DCU0_R1		0x1902
				VF610_PAD_PTE7__DCU0_R2		0x1902
				VF610_PAD_PTE8__DCU0_R3		0x1902
				VF610_PAD_PTE9__DCU0_R4		0x1902
				VF610_PAD_PTE10__DCU0_R5	0x1902
				VF610_PAD_PTE11__DCU0_R6	0x1902
				VF610_PAD_PTE12__DCU0_R7	0x1902
				VF610_PAD_PTE13__DCU0_G0	0x1902
				VF610_PAD_PTE14__DCU0_G1	0x1902
				VF610_PAD_PTE15__DCU0_G2	0x1902
				VF610_PAD_PTE16__DCU0_G3	0x1902
				VF610_PAD_PTE17__DCU0_G4	0x1902
				VF610_PAD_PTE18__DCU0_G5	0x1902
				VF610_PAD_PTE19__DCU0_G6	0x1902
				VF610_PAD_PTE20__DCU0_G7	0x1902
				VF610_PAD_PTE21__DCU0_B0	0x1902
				VF610_PAD_PTE22__DCU0_B1	0x1902
				VF610_PAD_PTE23__DCU0_B2	0x1902
				VF610_PAD_PTE24__DCU0_B3	0x1902
				VF610_PAD_PTE25__DCU0_B4	0x1902
				VF610_PAD_PTE26__DCU0_B5	0x1902
				VF610_PAD_PTE27__DCU0_B6	0x1902
				VF610_PAD_PTE28__DCU0_B7	0x1902
			>;
		};

		pinctrl_dspi1: dspi1grp {
			fsl,pins = <
				VF610_PAD_PTD5__DSPI1_CS0		0x33e2
				VF610_PAD_PTD6__DSPI1_SIN		0x33e1
				VF610_PAD_PTD7__DSPI1_SOUT		0x33e2
				VF610_PAD_PTD8__DSPI1_SCK		0x33e2
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
				VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
				VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
				VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
				VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
				VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
				VF610_PAD_PTB20__GPIO_42	0x219d
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				VF610_PAD_PTA6__RMII_CLKOUT		0x30d2
				VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
				VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
				VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
				VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
				VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
				VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
				VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
				VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
				VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
			>;
		};

		pinctrl_gpio_bl_on: gpio_bl_on {
			fsl,pins = <
				VF610_PAD_PTC0__GPIO_45		0x22ef
			>;
		};

		pinctrl_i2c0: i2c0grp {
			fsl,pins = <
				VF610_PAD_PTB14__I2C0_SCL		0x37ff
				VF610_PAD_PTB15__I2C0_SDA		0x37ff
			>;
		};

		pinctrl_nfc: nfcgrp {
			fsl,pins = <
				VF610_PAD_PTD23__NF_IO7		0x28df
				VF610_PAD_PTD22__NF_IO6		0x28df
				VF610_PAD_PTD21__NF_IO5		0x28df
				VF610_PAD_PTD20__NF_IO4		0x28df
				VF610_PAD_PTD19__NF_IO3		0x28df
				VF610_PAD_PTD18__NF_IO2		0x28df
				VF610_PAD_PTD17__NF_IO1		0x28df
				VF610_PAD_PTD16__NF_IO0		0x28df
				VF610_PAD_PTB24__NF_WE_B	0x28c2
				VF610_PAD_PTB25__NF_CE0_B	0x28c2
				VF610_PAD_PTB27__NF_RE_B	0x28c2
				VF610_PAD_PTC26__NF_RB_B	0x283d
				VF610_PAD_PTC27__NF_ALE		0x28c2
				VF610_PAD_PTC28__NF_CLE		0x28c2
			>;
		};

		pinctrl_pwm0: pwm0grp {
			fsl,pins = <
				VF610_PAD_PTB0__FTM0_CH0		0x1182
				VF610_PAD_PTB1__FTM0_CH1		0x1182
			>;
		};

		pinctrl_pwm1: pwm1grp {
			fsl,pins = <
				VF610_PAD_PTB8__FTM1_CH0		0x1182
				VF610_PAD_PTB9__FTM1_CH1		0x1182
			>;
		};

		pinctrl_uart0: uart0grp {
			fsl,pins = <
				VF610_PAD_PTB10__UART0_TX		0x21a2
				VF610_PAD_PTB11__UART0_RX		0x21a1
				VF610_PAD_PTB12__UART0_RTS		0x21a2
				VF610_PAD_PTB13__UART0_CTS		0x21a1
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				VF610_PAD_PTB4__UART1_TX		0x21a2
				VF610_PAD_PTB5__UART1_RX		0x21a1
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				VF610_PAD_PTD0__UART2_TX		0x21a2
				VF610_PAD_PTD1__UART2_RX		0x21a1
				VF610_PAD_PTD2__UART2_RTS		0x21a2
				VF610_PAD_PTD3__UART2_CTS		0x21a1
			>;
		};

		pinctrl_usbh1_reg: gpio_usb_vbus {
			fsl,pins = <
				VF610_PAD_PTD4__GPIO_83			0x22ed
			>;
		};
	};
};
Commit	Line	Data
e1bf86ac SA	1	/*
	2	* Copyright 2014 Toradex AG
	3	*
9f3440dd SA	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
13283626	13	* This file is distributed in the hope that it will be useful,
9f3440dd SA	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
13283626	18	* Or, alternatively,
9f3440dd SA	19	*
	20	* b) Permission is hereby granted, free of charge, to any person
	21	* obtaining a copy of this software and associated documentation
	22	* files (the "Software"), to deal in the Software without
13283626	23	* restriction, including without limitation the rights to use,
9f3440dd SA	24	* copy, modify, merge, publish, distribute, sublicense, and/or
	25	* sell copies of the Software, and to permit persons to whom the
	26	* Software is furnished to do so, subject to the following
	27	* conditions:
	28	*
	29	* The above copyright notice and this permission notice shall be
	30	* included in all copies or substantial portions of the Software.
	31	*
13283626	32	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
9f3440dd SA	33	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	34	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	35	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
13283626	36	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
9f3440dd SA	37	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	38	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	39	* OTHER DEALINGS IN THE SOFTWARE.
e1bf86ac SA	40	*/
	41
	42	/ {
9b1a1779 SA	43	aliases {
	44	ethernet0 = &fec1;
	45	ethernet1 = &fec0;
	46	};
	47
e1bf86ac SA	48	bl: backlight {
e1bf86ac SA	49	compatible = "pwm-backlight";
b2e42446 BD	50	pinctrl-names = "default";
b2e42446 BD	51	pinctrl-0 = <&pinctrl_gpio_bl_on>;
e1bf86ac	52	pwms = <&pwm0 0 5000000 0>;
b2e42446	53	enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
e1bf86ac SA	54	status = "disabled";
e1bf86ac SA	55	};
47b06e6e SA	56
	57	reg_module_3v3: regulator-module-3v3 {
	58	compatible = "regulator-fixed";
	59	regulator-name = "+V3.3";
	60	regulator-min-microvolt = <3300000>;
	61	regulator-max-microvolt = <3300000>;
	62	};
	63
	64	reg_module_3v3_avdd: regulator-module-3v3-avdd {
	65	compatible = "regulator-fixed";
	66	regulator-name = "+V3.3_AVDD_AUDIO";
	67	regulator-min-microvolt = <3300000>;
	68	regulator-max-microvolt = <3300000>;
	69	};
e1bf86ac SA	70	};
	71
	72	&adc0 {
	73	status = "okay";
47b06e6e	74	vref-supply = <&reg_module_3v3_avdd>;
e1bf86ac SA	75	};
	76
	77	&adc1 {
	78	status = "okay";
47b06e6e	79	vref-supply = <&reg_module_3v3_avdd>;
e1bf86ac SA	80	};
e1bf86ac SA	81
2afa06cb SA	82	&can0 {
	83	pinctrl-names = "default";
	84	pinctrl-0 = <&pinctrl_flexcan0>;
	85	status = "disabled";
	86	};
	87
	88	&can1 {
	89	pinctrl-names = "default";
	90	pinctrl-0 = <&pinctrl_flexcan1>;
	91	status = "disabled";
	92	};
	93
5c35b778 SA	94	&clks {
	95	assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
	96	<&clks VF610_CLK_ENET_TS_SEL>;
	97	assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
	98	<&clks VF610_CLK_ENET_50M>;
	99	};
	100
9fca0151 BD	101	&dspi1 {
	102	bus-num = <1>;
	103	pinctrl-names = "default";
	104	pinctrl-0 = <&pinctrl_dspi1>;
	105	};
	106
e1bf86ac SA	107	&edma0 {
	108	status = "okay";
	109	};
	110
14c41633 SM	111	&edma1 {
	112	status = "okay";
	113	};
	114
e1bf86ac SA	115	&esdhc1 {
	116	pinctrl-names = "default";
	117	pinctrl-0 = <&pinctrl_esdhc1>;
	118	bus-width = <4>;
76713954	119	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
4ee5ad0c	120	disable-wp;
e1bf86ac SA	121	};
	122
	123	&fec1 {
	124	phy-mode = "rmii";
47b06e6e	125	phy-supply = <&reg_module_3v3>;
e1bf86ac SA	126	pinctrl-names = "default";
	127	pinctrl-0 = <&pinctrl_fec1>;
	128	};
	129
1ddeb484 BD	130	&i2c0 {
	131	clock-frequency = <400000>;
	132	pinctrl-names = "default";
	133	pinctrl-0 = <&pinctrl_i2c0>;
	134	};
	135
65425265	136	&nfc {
65425265 SA	137	pinctrl-names = "default";
	138	pinctrl-0 = <&pinctrl_nfc>;
	139	status = "okay";
	140
	141	nand@0 {
	142	compatible = "fsl,vf610-nfc-nandcs";
	143	reg = <0>;
	144	#address-cells = <1>;
	145	#size-cells = <1>;
	146	nand-bus-width = <8>;
	147	nand-ecc-mode = "hw";
	148	nand-ecc-strength = <32>;
	149	nand-ecc-step-size = <2048>;
	150	nand-on-flash-bbt;
	151	};
	152	};
	153
e1bf86ac SA	154	&pwm0 {
	155	pinctrl-names = "default";
	156	pinctrl-0 = <&pinctrl_pwm0>;
	157	};
	158
	159	&pwm1 {
	160	pinctrl-names = "default";
	161	pinctrl-0 = <&pinctrl_pwm1>;
	162	};
	163
	164	&uart0 {
	165	pinctrl-names = "default";
	166	pinctrl-0 = <&pinctrl_uart0>;
	167	};
	168
	169	&uart1 {
	170	pinctrl-names = "default";
	171	pinctrl-0 = <&pinctrl_uart1>;
	172	};
	173
	174	&uart2 {
	175	pinctrl-names = "default";
	176	pinctrl-0 = <&pinctrl_uart2>;
	177	};
	178
	179	&usbdev0 {
	180	disable-over-current;
	181	status = "okay";
	182	};
	183
	184	&usbh1 {
	185	disable-over-current;
	186	status = "okay";
	187	};
	188
ac039cd9 SA	189	&usbmisc0 {
	190	status = "okay";
	191	};
	192
	193	&usbmisc1 {
	194	status = "okay";
	195	};
	196
	197	&usbphy0 {
	198	status = "okay";
	199	};
	200
	201	&usbphy1 {
	202	status = "okay";
	203	};
	204
e1bf86ac SA	205	&iomuxc {
e1bf86ac SA	206	vf610-colibri {
2afa06cb SA	207	pinctrl_flexcan0: can0grp {
	208	fsl,pins = <
	209	VF610_PAD_PTB14__CAN0_RX 0x31F1
	210	VF610_PAD_PTB15__CAN0_TX 0x31F2
	211	>;
	212	};
	213
	214	pinctrl_flexcan1: can1grp {
	215	fsl,pins = <
	216	VF610_PAD_PTB16__CAN1_RX 0x31F1
	217	VF610_PAD_PTB17__CAN1_TX 0x31F2
	218	>;
	219	};
	220
2b36bda3 SA	221	pinctrl_gpio_ext: gpio_ext {
	222	fsl,pins = <
	223	VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */
	224	VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */
	225	VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */
	226	>;
	227	};
	228
77f0862d SA	229	pinctrl_dcu0_1: dcu0grp_1 {
	230	fsl,pins = <
	231	VF610_PAD_PTE0__DCU0_HSYNC 0x1902
	232	VF610_PAD_PTE1__DCU0_VSYNC 0x1902
	233	VF610_PAD_PTE2__DCU0_PCLK 0x1902
	234	VF610_PAD_PTE4__DCU0_DE 0x1902
	235	VF610_PAD_PTE5__DCU0_R0 0x1902
	236	VF610_PAD_PTE6__DCU0_R1 0x1902
	237	VF610_PAD_PTE7__DCU0_R2 0x1902
	238	VF610_PAD_PTE8__DCU0_R3 0x1902
	239	VF610_PAD_PTE9__DCU0_R4 0x1902
	240	VF610_PAD_PTE10__DCU0_R5 0x1902
	241	VF610_PAD_PTE11__DCU0_R6 0x1902
	242	VF610_PAD_PTE12__DCU0_R7 0x1902
	243	VF610_PAD_PTE13__DCU0_G0 0x1902
	244	VF610_PAD_PTE14__DCU0_G1 0x1902
	245	VF610_PAD_PTE15__DCU0_G2 0x1902
	246	VF610_PAD_PTE16__DCU0_G3 0x1902
	247	VF610_PAD_PTE17__DCU0_G4 0x1902
	248	VF610_PAD_PTE18__DCU0_G5 0x1902
	249	VF610_PAD_PTE19__DCU0_G6 0x1902
	250	VF610_PAD_PTE20__DCU0_G7 0x1902
	251	VF610_PAD_PTE21__DCU0_B0 0x1902
	252	VF610_PAD_PTE22__DCU0_B1 0x1902
	253	VF610_PAD_PTE23__DCU0_B2 0x1902
	254	VF610_PAD_PTE24__DCU0_B3 0x1902
	255	VF610_PAD_PTE25__DCU0_B4 0x1902
	256	VF610_PAD_PTE26__DCU0_B5 0x1902
	257	VF610_PAD_PTE27__DCU0_B6 0x1902
	258	VF610_PAD_PTE28__DCU0_B7 0x1902
	259	>;
	260	};
	261
9fca0151 BD	262	pinctrl_dspi1: dspi1grp {
	263	fsl,pins = <
	264	VF610_PAD_PTD5__DSPI1_CS0 0x33e2
	265	VF610_PAD_PTD6__DSPI1_SIN 0x33e1
	266	VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
	267	VF610_PAD_PTD8__DSPI1_SCK 0x33e2
	268	>;
	269	};
	270
e1bf86ac SA	271	pinctrl_esdhc1: esdhc1grp {
	272	fsl,pins = <
	273	VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
	274	VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
	275	VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
	276	VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
	277	VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
	278	VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
	279	VF610_PAD_PTB20__GPIO_42 0x219d
	280	>;
	281	};
	282
	283	pinctrl_fec1: fec1grp {
	284	fsl,pins = <
eddb00fa	285	VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
e1bf86ac SA	286	VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
	287	VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
	288	VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
aa5fec2d	289	VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
e1bf86ac SA	290	VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
	291	VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
	292	VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
	293	VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
	294	VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
	295	>;
	296	};
	297
b2e42446 BD	298	pinctrl_gpio_bl_on: gpio_bl_on {
	299	fsl,pins = <
	300	VF610_PAD_PTC0__GPIO_45 0x22ef
	301	>;
	302	};
	303
1ddeb484 BD	304	pinctrl_i2c0: i2c0grp {
	305	fsl,pins = <
	306	VF610_PAD_PTB14__I2C0_SCL 0x37ff
	307	VF610_PAD_PTB15__I2C0_SDA 0x37ff
	308	>;
	309	};
	310
65425265 SA	311	pinctrl_nfc: nfcgrp {
	312	fsl,pins = <
	313	VF610_PAD_PTD23__NF_IO7 0x28df
	314	VF610_PAD_PTD22__NF_IO6 0x28df
	315	VF610_PAD_PTD21__NF_IO5 0x28df
	316	VF610_PAD_PTD20__NF_IO4 0x28df
	317	VF610_PAD_PTD19__NF_IO3 0x28df
	318	VF610_PAD_PTD18__NF_IO2 0x28df
	319	VF610_PAD_PTD17__NF_IO1 0x28df
	320	VF610_PAD_PTD16__NF_IO0 0x28df
	321	VF610_PAD_PTB24__NF_WE_B 0x28c2
	322	VF610_PAD_PTB25__NF_CE0_B 0x28c2
	323	VF610_PAD_PTB27__NF_RE_B 0x28c2
	324	VF610_PAD_PTC26__NF_RB_B 0x283d
	325	VF610_PAD_PTC27__NF_ALE 0x28c2
	326	VF610_PAD_PTC28__NF_CLE 0x28c2
	327	>;
	328	};
	329
e1bf86ac SA	330	pinctrl_pwm0: pwm0grp {
	331	fsl,pins = <
	332	VF610_PAD_PTB0__FTM0_CH0 0x1182
	333	VF610_PAD_PTB1__FTM0_CH1 0x1182
	334	>;
	335	};
	336
	337	pinctrl_pwm1: pwm1grp {
	338	fsl,pins = <
	339	VF610_PAD_PTB8__FTM1_CH0 0x1182
	340	VF610_PAD_PTB9__FTM1_CH1 0x1182
	341	>;
	342	};
	343
	344	pinctrl_uart0: uart0grp {
	345	fsl,pins = <
	346	VF610_PAD_PTB10__UART0_TX 0x21a2
	347	VF610_PAD_PTB11__UART0_RX 0x21a1
894b7383 BD	348	VF610_PAD_PTB12__UART0_RTS 0x21a2
894b7383 BD	349	VF610_PAD_PTB13__UART0_CTS 0x21a1
e1bf86ac SA	350	>;
	351	};
	352
	353	pinctrl_uart1: uart1grp {
	354	fsl,pins = <
	355	VF610_PAD_PTB4__UART1_TX 0x21a2
	356	VF610_PAD_PTB5__UART1_RX 0x21a1
	357	>;
	358	};
	359
	360	pinctrl_uart2: uart2grp {
	361	fsl,pins = <
	362	VF610_PAD_PTD0__UART2_TX 0x21a2
	363	VF610_PAD_PTD1__UART2_RX 0x21a1
	364	VF610_PAD_PTD2__UART2_RTS 0x21a2
	365	VF610_PAD_PTD3__UART2_CTS 0x21a1
	366	>;
	367	};
505251e5 SA	368
	369	pinctrl_usbh1_reg: gpio_usb_vbus {
	370	fsl,pins = <
	371	VF610_PAD_PTD4__GPIO_83 0x22ed
	372	>;
	373	};
e1bf86ac SA	374	};
e1bf86ac SA	375	};