[linux-2.6-block.git] / arch / arm / boot / dts / vexpress-v2p-ca9.dts

/*
 * ARM Ltd. Versatile Express
 *
 * CoreTile Express A9x4
 * Cortex-A9 MPCore (V2P-CA9)
 *
 * HBI-0191B
 */

/dts-v1/;

/ {
	model = "V2P-CA9";
	arm,hbi = <0x191>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			next-level-cache = <&L2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			next-level-cache = <&L2>;
		};
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x40000000>;
	};

	clcd@10020000 {
		compatible = "arm,pl111", "arm,primecell";
		reg = <0x10020000 0x1000>;
		interrupts = <0 44 4>;
		clocks = <&oscclk1>, <&oscclk2>;
		clock-names = "clcdclk", "apb_pclk";
	};

	memory-controller@100e0000 {
		compatible = "arm,pl341", "arm,primecell";
		reg = <0x100e0000 0x1000>;
		clocks = <&oscclk2>;
		clock-names = "apb_pclk";
	};

	memory-controller@100e1000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0x100e1000 0x1000>;
		interrupts = <0 45 4>,
			     <0 46 4>;
		clocks = <&oscclk2>;
		clock-names = "apb_pclk";
	};

	timer@100e4000 {
		compatible = "arm,sp804", "arm,primecell";
		reg = <0x100e4000 0x1000>;
		interrupts = <0 48 4>,
			     <0 49 4>;
		clocks = <&oscclk2>, <&oscclk2>;
		clock-names = "timclk", "apb_pclk";
		status = "disabled";
	};

	watchdog@100e5000 {
		compatible = "arm,sp805", "arm,primecell";
		reg = <0x100e5000 0x1000>;
		interrupts = <0 51 4>;
		clocks = <&oscclk2>, <&oscclk2>;
		clock-names = "wdogclk", "apb_pclk";
	};

	scu@1e000000 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x1e000000 0x58>;
	};

	timer@1e000600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x1e000600 0x20>;
		interrupts = <1 13 0xf04>;
	};

	watchdog@1e000620 {
		compatible = "arm,cortex-a9-twd-wdt";
		reg = <0x1e000620 0x20>;
		interrupts = <1 14 0xf04>;
	};

	gic: interrupt-controller@1e001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x1e001000 0x1000>,
		      <0x1e000100 0x100>;
	};

	L2: cache-controller@1e00a000 {
		compatible = "arm,pl310-cache";
		reg = <0x1e00a000 0x1000>;
		interrupts = <0 43 4>;
		cache-level = <2>;
		arm,data-latency = <1 1 1>;
		arm,tag-latency = <1 1 1>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 60 4>,
			     <0 61 4>,
			     <0 62 4>,
			     <0 63 4>;
	};

	dcc {
		compatible = "arm,vexpress,config-bus";
		arm,vexpress,config-bridge = <&v2m_sysreg>;

		osc@0 {
			/* ACLK clock to the AXI master port on the test chip */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 0>;
			freq-range = <30000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "extsaxiclk";
		};

		oscclk1: osc@1 {
			/* Reference clock for the CLCD */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 1>;
			freq-range = <10000000 80000000>;
			#clock-cells = <0>;
			clock-output-names = "clcdclk";
		};

		smbclk: oscclk2: osc@2 {
			/* Reference clock for the test chip internal PLLs */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 2>;
			freq-range = <33000000 100000000>;
			#clock-cells = <0>;
			clock-output-names = "tcrefclk";
		};

		volt@0 {
			/* Test Chip internal logic voltage */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 0>;
			regulator-name = "VD10";
			regulator-always-on;
			label = "VD10";
		};

		volt@1 {
			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 1>;
			regulator-name = "VD10_S2";
			regulator-always-on;
			label = "VD10_S2";
		};

		volt@2 {
			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 2>;
			regulator-name = "VD10_S3";
			regulator-always-on;
			label = "VD10_S3";
		};

		volt@3 {
			/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 3>;
			regulator-name = "VCC1V8";
			regulator-always-on;
			label = "VCC1V8";
		};

		volt@4 {
			/* DDR2 SDRAM VTT termination voltage */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 4>;
			regulator-name = "DDR2VTT";
			regulator-always-on;
			label = "DDR2VTT";
		};

		volt@5 {
			/* Local board supply for miscellaneous logic external to the Test Chip */
			arm,vexpress-sysreg,func = <2 5>;
			compatible = "arm,vexpress-volt";
			regulator-name = "VCC3V3";
			regulator-always-on;
			label = "VCC3V3";
		};

		amp@0 {
			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
			compatible = "arm,vexpress-amp";
			arm,vexpress-sysreg,func = <3 0>;
			label = "VD10_S2";
		};

		amp@1 {
			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
			compatible = "arm,vexpress-amp";
			arm,vexpress-sysreg,func = <3 1>;
			label = "VD10_S3";
		};

		power@0 {
			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
			compatible = "arm,vexpress-power";
			arm,vexpress-sysreg,func = <12 0>;
			label = "PVD10_S2";
		};

		power@1 {
			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
			compatible = "arm,vexpress-power";
			arm,vexpress-sysreg,func = <12 1>;
			label = "PVD10_S3";
		};
	};

	smb {
		compatible = "simple-bus";

		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0x40000000 0x04000000>,
			 <1 0 0x44000000 0x04000000>,
			 <2 0 0x48000000 0x04000000>,
			 <3 0 0x4c000000 0x04000000>,
			 <7 0 0x10000000 0x00020000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic 0  0 4>,
				<0 0  1 &gic 0  1 4>,
				<0 0  2 &gic 0  2 4>,
				<0 0  3 &gic 0  3 4>,
				<0 0  4 &gic 0  4 4>,
				<0 0  5 &gic 0  5 4>,
				<0 0  6 &gic 0  6 4>,
				<0 0  7 &gic 0  7 4>,
				<0 0  8 &gic 0  8 4>,
				<0 0  9 &gic 0  9 4>,
				<0 0 10 &gic 0 10 4>,
				<0 0 11 &gic 0 11 4>,
				<0 0 12 &gic 0 12 4>,
				<0 0 13 &gic 0 13 4>,
				<0 0 14 &gic 0 14 4>,
				<0 0 15 &gic 0 15 4>,
				<0 0 16 &gic 0 16 4>,
				<0 0 17 &gic 0 17 4>,
				<0 0 18 &gic 0 18 4>,
				<0 0 19 &gic 0 19 4>,
				<0 0 20 &gic 0 20 4>,
				<0 0 21 &gic 0 21 4>,
				<0 0 22 &gic 0 22 4>,
				<0 0 23 &gic 0 23 4>,
				<0 0 24 &gic 0 24 4>,
				<0 0 25 &gic 0 25 4>,
				<0 0 26 &gic 0 26 4>,
				<0 0 27 &gic 0 27 4>,
				<0 0 28 &gic 0 28 4>,
				<0 0 29 &gic 0 29 4>,
				<0 0 30 &gic 0 30 4>,
				<0 0 31 &gic 0 31 4>,
				<0 0 32 &gic 0 32 4>,
				<0 0 33 &gic 0 33 4>,
				<0 0 34 &gic 0 34 4>,
				<0 0 35 &gic 0 35 4>,
				<0 0 36 &gic 0 36 4>,
				<0 0 37 &gic 0 37 4>,
				<0 0 38 &gic 0 38 4>,
				<0 0 39 &gic 0 39 4>,
				<0 0 40 &gic 0 40 4>,
				<0 0 41 &gic 0 41 4>,
				<0 0 42 &gic 0 42 4>;

		/include/ "vexpress-v2m.dtsi"
	};
};
Commit	Line	Data
cca070a9 PM	1	/*
	2	* ARM Ltd. Versatile Express
	3	*
	4	* CoreTile Express A9x4
	5	* Cortex-A9 MPCore (V2P-CA9)
	6	*
	7	* HBI-0191B
	8	*/
	9
	10	/dts-v1/;
	11
	12	/ {
	13	model = "V2P-CA9";
	14	arm,hbi = <0x191>;
842839a3	15	arm,vexpress,site = <0xf>;
cca070a9 PM	16	compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
	17	interrupt-parent = <&gic>;
	18	#address-cells = <1>;
	19	#size-cells = <1>;
	20
	21	chosen { };
	22
	23	aliases {
	24	serial0 = &v2m_serial0;
	25	serial1 = &v2m_serial1;
	26	serial2 = &v2m_serial2;
	27	serial3 = &v2m_serial3;
	28	i2c0 = &v2m_i2c_dvi;
	29	i2c1 = &v2m_i2c_pcie;
	30	};
	31
	32	cpus {
	33	#address-cells = <1>;
	34	#size-cells = <0>;
	35
	36	cpu@0 {
	37	device_type = "cpu";
	38	compatible = "arm,cortex-a9";
	39	reg = <0>;
	40	next-level-cache = <&L2>;
	41	};
	42
	43	cpu@1 {
	44	device_type = "cpu";
	45	compatible = "arm,cortex-a9";
	46	reg = <1>;
	47	next-level-cache = <&L2>;
	48	};
	49
	50	cpu@2 {
	51	device_type = "cpu";
	52	compatible = "arm,cortex-a9";
	53	reg = <2>;
	54	next-level-cache = <&L2>;
	55	};
	56
	57	cpu@3 {
	58	device_type = "cpu";
	59	compatible = "arm,cortex-a9";
	60	reg = <3>;
	61	next-level-cache = <&L2>;
	62	};
	63	};
	64
	65	memory@60000000 {
	66	device_type = "memory";
	67	reg = <0x60000000 0x40000000>;
	68	};
	69
	70	clcd@10020000 {
	71	compatible = "arm,pl111", "arm,primecell";
	72	reg = <0x10020000 0x1000>;
	73	interrupts = <0 44 4>;
842839a3 PM	74	clocks = <&oscclk1>, <&oscclk2>;
842839a3 PM	75	clock-names = "clcdclk", "apb_pclk";
cca070a9 PM	76	};
	77
	78	memory-controller@100e0000 {
	79	compatible = "arm,pl341", "arm,primecell";
	80	reg = <0x100e0000 0x1000>;
842839a3 PM	81	clocks = <&oscclk2>;
842839a3 PM	82	clock-names = "apb_pclk";
cca070a9 PM	83	};
	84
	85	memory-controller@100e1000 {
	86	compatible = "arm,pl354", "arm,primecell";
	87	reg = <0x100e1000 0x1000>;
	88	interrupts = <0 45 4>,
	89	<0 46 4>;
842839a3 PM	90	clocks = <&oscclk2>;
842839a3 PM	91	clock-names = "apb_pclk";
cca070a9 PM	92	};
	93
	94	timer@100e4000 {
	95	compatible = "arm,sp804", "arm,primecell";
	96	reg = <0x100e4000 0x1000>;
	97	interrupts = <0 48 4>,
	98	<0 49 4>;
842839a3 PM	99	clocks = <&oscclk2>, <&oscclk2>;
842839a3 PM	100	clock-names = "timclk", "apb_pclk";
34c2e5fe	101	status = "disabled";
cca070a9 PM	102	};
	103
	104	watchdog@100e5000 {
	105	compatible = "arm,sp805", "arm,primecell";
	106	reg = <0x100e5000 0x1000>;
	107	interrupts = <0 51 4>;
842839a3 PM	108	clocks = <&oscclk2>, <&oscclk2>;
842839a3 PM	109	clock-names = "wdogclk", "apb_pclk";
cca070a9 PM	110	};
	111
	112	scu@1e000000 {
	113	compatible = "arm,cortex-a9-scu";
	114	reg = <0x1e000000 0x58>;
	115	};
	116
	117	timer@1e000600 {
	118	compatible = "arm,cortex-a9-twd-timer";
	119	reg = <0x1e000600 0x20>;
e29b65db PM	120	interrupts = <1 13 0xf04>;
	121	};
	122
	123	watchdog@1e000620 {
	124	compatible = "arm,cortex-a9-twd-wdt";
	125	reg = <0x1e000620 0x20>;
	126	interrupts = <1 14 0xf04>;
cca070a9 PM	127	};
	128
	129	gic: interrupt-controller@1e001000 {
	130	compatible = "arm,cortex-a9-gic";
	131	#interrupt-cells = <3>;
	132	#address-cells = <0>;
	133	interrupt-controller;
	134	reg = <0x1e001000 0x1000>,
	135	<0x1e000100 0x100>;
	136	};
	137
	138	L2: cache-controller@1e00a000 {
	139	compatible = "arm,pl310-cache";
	140	reg = <0x1e00a000 0x1000>;
	141	interrupts = <0 43 4>;
	142	cache-level = <2>;
	143	arm,data-latency = <1 1 1>;
	144	arm,tag-latency = <1 1 1>;
	145	};
	146
	147	pmu {
	148	compatible = "arm,cortex-a9-pmu";
	149	interrupts = <0 60 4>,
	150	<0 61 4>,
	151	<0 62 4>,
	152	<0 63 4>;
	153	};
	154
842839a3 PM	155	dcc {
	156	compatible = "arm,vexpress,config-bus";
	157	arm,vexpress,config-bridge = <&v2m_sysreg>;
	158
	159	osc@0 {
	160	/* ACLK clock to the AXI master port on the test chip */
	161	compatible = "arm,vexpress-osc";
	162	arm,vexpress-sysreg,func = <1 0>;
	163	freq-range = <30000000 50000000>;
	164	#clock-cells = <0>;
	165	clock-output-names = "extsaxiclk";
	166	};
	167
	168	oscclk1: osc@1 {
	169	/* Reference clock for the CLCD */
	170	compatible = "arm,vexpress-osc";
	171	arm,vexpress-sysreg,func = <1 1>;
	172	freq-range = <10000000 80000000>;
	173	#clock-cells = <0>;
	174	clock-output-names = "clcdclk";
	175	};
	176
	177	smbclk: oscclk2: osc@2 {
	178	/* Reference clock for the test chip internal PLLs */
	179	compatible = "arm,vexpress-osc";
	180	arm,vexpress-sysreg,func = <1 2>;
	181	freq-range = <33000000 100000000>;
	182	#clock-cells = <0>;
	183	clock-output-names = "tcrefclk";
	184	};
	185
	186	volt@0 {
	187	/* Test Chip internal logic voltage */
	188	compatible = "arm,vexpress-volt";
	189	arm,vexpress-sysreg,func = <2 0>;
	190	regulator-name = "VD10";
	191	regulator-always-on;
	192	label = "VD10";
	193	};
	194
	195	volt@1 {
	196	/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
	197	compatible = "arm,vexpress-volt";
	198	arm,vexpress-sysreg,func = <2 1>;
	199	regulator-name = "VD10_S2";
	200	regulator-always-on;
	201	label = "VD10_S2";
	202	};
	203
	204	volt@2 {
	205	/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
	206	compatible = "arm,vexpress-volt";
	207	arm,vexpress-sysreg,func = <2 2>;
	208	regulator-name = "VD10_S3";
	209	regulator-always-on;
	210	label = "VD10_S3";
	211	};
	212
	213	volt@3 {
	214	/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
	215	compatible = "arm,vexpress-volt";
	216	arm,vexpress-sysreg,func = <2 3>;
	217	regulator-name = "VCC1V8";
	218	regulator-always-on;
219	label = "VCC1V8";
220	};
221
222	volt@4 {
223	/* DDR2 SDRAM VTT termination voltage */
224	compatible = "arm,vexpress-volt";
225	arm,vexpress-sysreg,func = <2 4>;
226	regulator-name = "DDR2VTT";
227	regulator-always-on;
228	label = "DDR2VTT";
229	};
230
231	volt@5 {
232	/* Local board supply for miscellaneous logic external to the Test Chip */
233	arm,vexpress-sysreg,func = <2 5>;
234	compatible = "arm,vexpress-volt";
235	regulator-name = "VCC3V3";
236	regulator-always-on;
237	label = "VCC3V3";
238	};
239
240	amp@0 {
241	/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
242	compatible = "arm,vexpress-amp";
243	arm,vexpress-sysreg,func = <3 0>;
244	label = "VD10_S2";
245	};
246
247	amp@1 {
248	/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
249	compatible = "arm,vexpress-amp";
250	arm,vexpress-sysreg,func = <3 1>;
251	label = "VD10_S3";
252	};
253
254	power@0 {
255	/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
256	compatible = "arm,vexpress-power";
257	arm,vexpress-sysreg,func = <12 0>;
258	label = "PVD10_S2";
259	};
260
261	power@1 {
262	/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
263	compatible = "arm,vexpress-power";
264	arm,vexpress-sysreg,func = <12 1>;
265	label = "PVD10_S3";
266	};
267	};
268
433683a6 PM	269	smb {
	270	compatible = "simple-bus";
	271
	272	#address-cells = <2>;
	273	#size-cells = <1>;
cca070a9 PM	274	ranges = <0 0 0x40000000 0x04000000>,
	275	<1 0 0x44000000 0x04000000>,
	276	<2 0 0x48000000 0x04000000>,
	277	<3 0 0x4c000000 0x04000000>,
	278	<7 0 0x10000000 0x00020000>;
	279
433683a6	280	#interrupt-cells = <1>;
cca070a9 PM	281	interrupt-map-mask = <0 0 63>;
	282	interrupt-map = <0 0 0 &gic 0 0 4>,
	283	<0 0 1 &gic 0 1 4>,
	284	<0 0 2 &gic 0 2 4>,
	285	<0 0 3 &gic 0 3 4>,
	286	<0 0 4 &gic 0 4 4>,
	287	<0 0 5 &gic 0 5 4>,
	288	<0 0 6 &gic 0 6 4>,
	289	<0 0 7 &gic 0 7 4>,
	290	<0 0 8 &gic 0 8 4>,
	291	<0 0 9 &gic 0 9 4>,
	292	<0 0 10 &gic 0 10 4>,
	293	<0 0 11 &gic 0 11 4>,
	294	<0 0 12 &gic 0 12 4>,
	295	<0 0 13 &gic 0 13 4>,
	296	<0 0 14 &gic 0 14 4>,
	297	<0 0 15 &gic 0 15 4>,
	298	<0 0 16 &gic 0 16 4>,
	299	<0 0 17 &gic 0 17 4>,
	300	<0 0 18 &gic 0 18 4>,
	301	<0 0 19 &gic 0 19 4>,
	302	<0 0 20 &gic 0 20 4>,
	303	<0 0 21 &gic 0 21 4>,
	304	<0 0 22 &gic 0 22 4>,
	305	<0 0 23 &gic 0 23 4>,
	306	<0 0 24 &gic 0 24 4>,
	307	<0 0 25 &gic 0 25 4>,
	308	<0 0 26 &gic 0 26 4>,
	309	<0 0 27 &gic 0 27 4>,
	310	<0 0 28 &gic 0 28 4>,
	311	<0 0 29 &gic 0 29 4>,
	312	<0 0 30 &gic 0 30 4>,
	313	<0 0 31 &gic 0 31 4>,
	314	<0 0 32 &gic 0 32 4>,
	315	<0 0 33 &gic 0 33 4>,
	316	<0 0 34 &gic 0 34 4>,
	317	<0 0 35 &gic 0 35 4>,
	318	<0 0 36 &gic 0 36 4>,
	319	<0 0 37 &gic 0 37 4>,
	320	<0 0 38 &gic 0 38 4>,
	321	<0 0 39 &gic 0 39 4>,
	322	<0 0 40 &gic 0 40 4>,
	323	<0 0 41 &gic 0 41 4>,
	324	<0 0 42 &gic 0 42 4>;
433683a6 PM	325
433683a6 PM	326	/include/ "vexpress-v2m.dtsi"
cca070a9 PM	327	};
cca070a9 PM	328	};