[linux-2.6-block.git] / arch / arm / boot / dts / vexpress-v2p-ca15_a7.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * CoreTile Express A15x2 A7x3
 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
 *
 * HBI-0249A
 */

/dts-v1/;
#include "vexpress-v2m-rs1.dtsi"

/ {
	model = "V2P-CA15_CA7";
	arm,hbi = <0x249>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			cci-control-port = <&cci_control1>;
			cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
			capacity-dmips-mhz = <1024>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			cci-control-port = <&cci_control1>;
			cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
			capacity-dmips-mhz = <1024>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x100>;
			cci-control-port = <&cci_control2>;
			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
			capacity-dmips-mhz = <516>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x101>;
			cci-control-port = <&cci_control2>;
			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
			capacity-dmips-mhz = <516>;
		};

		cpu4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x102>;
			cci-control-port = <&cci_control2>;
			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
			capacity-dmips-mhz = <516>;
		};

		idle-states {
			CLUSTER_SLEEP_BIG: cluster-sleep-big {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <700>;
				min-residency-us = <2000>;
			};

			CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <500>;
				min-residency-us = <2500>;
			};
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0 0x40000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* Chipselect 2 is physically at 0x18000000 */
		vram: vram@18000000 {
			/* 8 MB of designated video RAM */
			compatible = "shared-dma-pool";
			reg = <0 0x18000000 0 0x00800000>;
			no-map;
		};
	};

	wdt@2a490000 {
		compatible = "arm,sp805", "arm,primecell";
		reg = <0 0x2a490000 0 0x1000>;
		interrupts = <0 98 4>;
		clocks = <&oscclk6a>, <&oscclk6a>;
		clock-names = "wdogclk", "apb_pclk";
	};

	hdlcd@2b000000 {
		compatible = "arm,hdlcd";
		reg = <0 0x2b000000 0 0x1000>;
		interrupts = <0 85 4>;
		clocks = <&hdlcd_clk>;
		clock-names = "pxlclk";
	};

	memory-controller@2b0a0000 {
		compatible = "arm,pl341", "arm,primecell";
		reg = <0 0x2b0a0000 0 0x1000>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x2c001000 0 0x1000>,
		      <0 0x2c002000 0 0x2000>,
		      <0 0x2c004000 0 0x2000>,
		      <0 0x2c006000 0 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	cci@2c090000 {
		compatible = "arm,cci-400";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0 0x2c090000 0 0x1000>;
		ranges = <0x0 0x0 0x2c090000 0x10000>;

		cci_control1: slave-if@4000 {
			compatible = "arm,cci-400-ctrl-if";
			interface-type = "ace";
			reg = <0x4000 0x1000>;
		};

		cci_control2: slave-if@5000 {
			compatible = "arm,cci-400-ctrl-if";
			interface-type = "ace";
			reg = <0x5000 0x1000>;
		};

		pmu@9000 {
			 compatible = "arm,cci-400-pmu,r0";
			 reg = <0x9000 0x5000>;
			 interrupts = <0 105 4>,
				      <0 101 4>,
				      <0 102 4>,
				      <0 103 4>,
				      <0 104 4>;
		};
	};

	memory-controller@7ffd0000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0 0x7ffd0000 0 0x1000>;
		interrupts = <0 86 4>,
			     <0 87 4>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
	};

	dma@7ff00000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0 0x7ff00000 0 0x1000>;
		interrupts = <0 92 4>,
			     <0 88 4>,
			     <0 89 4>,
			     <0 90 4>,
			     <0 91 4>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
	};

        scc@7fff0000 {
		compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
		reg = <0 0x7fff0000 0 0x1000>;
		interrupts = <0 95 4>;
        };

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
	};

	pmu-a15 {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <0 68 4>,
			     <0 69 4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>;
	};

	pmu-a7 {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <0 128 4>,
			     <0 129 4>,
			     <0 130 4>;
		interrupt-affinity = <&cpu2>,
				     <&cpu3>,
				     <&cpu4>;
	};

	oscclk6a: oscclk6a {
		/* Reference 24MHz clock */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "oscclk6a";
	};

	dcc {
		compatible = "arm,vexpress,config-bus";
		arm,vexpress,config-bridge = <&v2m_sysreg>;

		oscclk0 {
			/* A15 PLL 0 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 0>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk0";
		};

		oscclk1 {
			/* A15 PLL 1 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 1>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk1";
		};

		oscclk2 {
			/* A7 PLL 0 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 2>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk2";
		};

		oscclk3 {
			/* A7 PLL 1 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 3>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk3";
		};

		oscclk4 {
			/* External AXI master clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 4>;
			freq-range = <20000000 40000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk4";
		};

		hdlcd_clk: oscclk5 {
			/* HDLCD PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 5>;
			freq-range = <23750000 165000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk5";
		};

		smbclk: oscclk6 {
			/* Static memory controller clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 6>;
			freq-range = <20000000 40000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk6";
		};

		oscclk7 {
			/* SYS PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 7>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk7";
		};

		oscclk8 {
			/* DDR2 PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 8>;
			freq-range = <20000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk8";
		};

		volt-a15 {
			/* A15 CPU core voltage */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 0>;
			regulator-name = "A15 Vcore";
			regulator-min-microvolt = <800000>;
			regulator-max-microvolt = <1050000>;
			regulator-always-on;
			label = "A15 Vcore";
		};

		volt-a7 {
			/* A7 CPU core voltage */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 1>;
			regulator-name = "A7 Vcore";
			regulator-min-microvolt = <800000>;
			regulator-max-microvolt = <1050000>;
			regulator-always-on;
			label = "A7 Vcore";
		};

		amp-a15 {
			/* Total current for the two A15 cores */
			compatible = "arm,vexpress-amp";
			arm,vexpress-sysreg,func = <3 0>;
			label = "A15 Icore";
		};

		amp-a7 {
			/* Total current for the three A7 cores */
			compatible = "arm,vexpress-amp";
			arm,vexpress-sysreg,func = <3 1>;
			label = "A7 Icore";
		};

		temp-dcc {
			/* DCC internal temperature */
			compatible = "arm,vexpress-temp";
			arm,vexpress-sysreg,func = <4 0>;
			label = "DCC";
		};

		power-a15 {
			/* Total power for the two A15 cores */
			compatible = "arm,vexpress-power";
			arm,vexpress-sysreg,func = <12 0>;
			label = "A15 Pcore";
		};

		power-a7 {
			/* Total power for the three A7 cores */
			compatible = "arm,vexpress-power";
			arm,vexpress-sysreg,func = <12 1>;
			label = "A7 Pcore";
		};

		energy-a15 {
			/* Total energy for the two A15 cores */
			compatible = "arm,vexpress-energy";
			arm,vexpress-sysreg,func = <13 0>, <13 1>;
			label = "A15 Jcore";
		};

		energy-a7 {
			/* Total energy for the three A7 cores */
			compatible = "arm,vexpress-energy";
			arm,vexpress-sysreg,func = <13 2>, <13 3>;
			label = "A7 Jcore";
		};
	};

	etb@20010000 {
		compatible = "arm,coresight-etb10", "arm,primecell";
		reg = <0 0x20010000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			etb_in_port: endpoint {
				slave-mode;
				remote-endpoint = <&replicator_out_port0>;
			};
		};
	};

	tpiu@20030000 {
		compatible = "arm,coresight-tpiu", "arm,primecell";
		reg = <0 0x20030000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			tpiu_in_port: endpoint {
				slave-mode;
				remote-endpoint = <&replicator_out_port1>;
			};
		};
	};

	replicator {
		/* non-configurable replicators don't show up on the
		 * AMBA bus.  As such no need to add "arm,primecell".
		 */
		compatible = "arm,coresight-replicator";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* replicator output ports */
			port@0 {
				reg = <0>;
				replicator_out_port0: endpoint {
					remote-endpoint = <&etb_in_port>;
				};
			};

			port@1 {
				reg = <1>;
				replicator_out_port1: endpoint {
					remote-endpoint = <&tpiu_in_port>;
				};
			};

			/* replicator input port */
			port@2 {
				reg = <0>;
				replicator_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&funnel_out_port0>;
				};
			};
		};
	};

	funnel@20040000 {
		compatible = "arm,coresight-funnel", "arm,primecell";
		reg = <0 0x20040000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* funnel output port */
			port@0 {
				reg = <0>;
				funnel_out_port0: endpoint {
					remote-endpoint =
						<&replicator_in_port0>;
				};
			};

			/* funnel input ports */
			port@1 {
				reg = <0>;
				funnel_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&ptm0_out_port>;
				};
			};

			port@2 {
				reg = <1>;
				funnel_in_port1: endpoint {
					slave-mode;
					remote-endpoint = <&ptm1_out_port>;
				};
			};

			port@3 {
				reg = <2>;
				funnel_in_port2: endpoint {
					slave-mode;
					remote-endpoint = <&etm0_out_port>;
				};
			};

			/* Input port #3 is for ITM, not supported here */

			port@4 {
				reg = <4>;
				funnel_in_port4: endpoint {
					slave-mode;
					remote-endpoint = <&etm1_out_port>;
				};
			};

			port@5 {
				reg = <5>;
				funnel_in_port5: endpoint {
					slave-mode;
					remote-endpoint = <&etm2_out_port>;
				};
			};
		};
	};

	ptm@2201c000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2201c000 0 0x1000>;

		cpu = <&cpu0>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			ptm0_out_port: endpoint {
				remote-endpoint = <&funnel_in_port0>;
			};
		};
	};

	ptm@2201d000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2201d000 0 0x1000>;

		cpu = <&cpu1>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			ptm1_out_port: endpoint {
				remote-endpoint = <&funnel_in_port1>;
			};
		};
	};

	etm@2203c000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2203c000 0 0x1000>;

		cpu = <&cpu2>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			etm0_out_port: endpoint {
				remote-endpoint = <&funnel_in_port2>;
			};
		};
	};

	etm@2203d000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2203d000 0 0x1000>;

		cpu = <&cpu3>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			etm1_out_port: endpoint {
				remote-endpoint = <&funnel_in_port4>;
			};
		};
	};

	etm@2203e000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2203e000 0 0x1000>;

		cpu = <&cpu4>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			etm2_out_port: endpoint {
				remote-endpoint = <&funnel_in_port5>;
			};
		};
	};

	smb: smb@8000000 {
		compatible = "simple-bus";

		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0 0x08000000 0x04000000>,
			 <1 0 0 0x14000000 0x04000000>,
			 <2 0 0 0x18000000 0x04000000>,
			 <3 0 0 0x1c000000 0x04000000>,
			 <4 0 0 0x0c000000 0x04000000>,
			 <5 0 0 0x10000000 0x04000000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic 0  0 4>,
				<0 0  1 &gic 0  1 4>,
				<0 0  2 &gic 0  2 4>,
				<0 0  3 &gic 0  3 4>,
				<0 0  4 &gic 0  4 4>,
				<0 0  5 &gic 0  5 4>,
				<0 0  6 &gic 0  6 4>,
				<0 0  7 &gic 0  7 4>,
				<0 0  8 &gic 0  8 4>,
				<0 0  9 &gic 0  9 4>,
				<0 0 10 &gic 0 10 4>,
				<0 0 11 &gic 0 11 4>,
				<0 0 12 &gic 0 12 4>,
				<0 0 13 &gic 0 13 4>,
				<0 0 14 &gic 0 14 4>,
				<0 0 15 &gic 0 15 4>,
				<0 0 16 &gic 0 16 4>,
				<0 0 17 &gic 0 17 4>,
				<0 0 18 &gic 0 18 4>,
				<0 0 19 &gic 0 19 4>,
				<0 0 20 &gic 0 20 4>,
				<0 0 21 &gic 0 21 4>,
				<0 0 22 &gic 0 22 4>,
				<0 0 23 &gic 0 23 4>,
				<0 0 24 &gic 0 24 4>,
				<0 0 25 &gic 0 25 4>,
				<0 0 26 &gic 0 26 4>,
				<0 0 27 &gic 0 27 4>,
				<0 0 28 &gic 0 28 4>,
				<0 0 29 &gic 0 29 4>,
				<0 0 30 &gic 0 30 4>,
				<0 0 31 &gic 0 31 4>,
				<0 0 32 &gic 0 32 4>,
				<0 0 33 &gic 0 33 4>,
				<0 0 34 &gic 0 34 4>,
				<0 0 35 &gic 0 35 4>,
				<0 0 36 &gic 0 36 4>,
				<0 0 37 &gic 0 37 4>,
				<0 0 38 &gic 0 38 4>,
				<0 0 39 &gic 0 39 4>,
				<0 0 40 &gic 0 40 4>,
				<0 0 41 &gic 0 41 4>,
				<0 0 42 &gic 0 42 4>;
	};

	site2: hsb@40000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x40000000 0x3fef0000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 3>;
		interrupt-map = <0 0 &gic 0 36 4>,
				<0 1 &gic 0 37 4>,
				<0 2 &gic 0 38 4>,
				<0 3 &gic 0 39 4>;
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
375faa93 PM	2	/*
	3	* ARM Ltd. Versatile Express
	4	*
	5	* CoreTile Express A15x2 A7x3
	6	* Cortex-A15_A7 MPCore (V2P-CA15_A7)
	7	*
	8	* HBI-0249A
	9	*/
	10
	11	/dts-v1/;
bd7aff03	12	#include "vexpress-v2m-rs1.dtsi"
375faa93 PM	13
	14	/ {
	15	model = "V2P-CA15_CA7";
	16	arm,hbi = <0x249>;
842839a3	17	arm,vexpress,site = <0xf>;
375faa93 PM	18	compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
	19	interrupt-parent = <&gic>;
	20	#address-cells = <2>;
	21	#size-cells = <2>;
	22
	23	chosen { };
	24
	25	aliases {
	26	serial0 = &v2m_serial0;
	27	serial1 = &v2m_serial1;
	28	serial2 = &v2m_serial2;
	29	serial3 = &v2m_serial3;
	30	i2c0 = &v2m_i2c_dvi;
	31	i2c1 = &v2m_i2c_pcie;
	32	};
	33
	34	cpus {
	35	#address-cells = <1>;
	36	#size-cells = <0>;
	37
	38	cpu0: cpu@0 {
	39	device_type = "cpu";
	40	compatible = "arm,cortex-a15";
	41	reg = <0>;
a2bdc32a	42	cci-control-port = <&cci_control1>;
d2e5c871	43	cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
b01c3994	44	capacity-dmips-mhz = <1024>;
375faa93 PM	45	};
	46
	47	cpu1: cpu@1 {
	48	device_type = "cpu";
	49	compatible = "arm,cortex-a15";
	50	reg = <1>;
a2bdc32a	51	cci-control-port = <&cci_control1>;
d2e5c871	52	cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
b01c3994	53	capacity-dmips-mhz = <1024>;
375faa93 PM	54	};
375faa93 PM	55
375faa93 PM	56	cpu2: cpu@2 {
	57	device_type = "cpu";
	58	compatible = "arm,cortex-a7";
	59	reg = <0x100>;
a2bdc32a	60	cci-control-port = <&cci_control2>;
d2e5c871	61	cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
b01c3994	62	capacity-dmips-mhz = <516>;
375faa93 PM	63	};
	64
	65	cpu3: cpu@3 {
	66	device_type = "cpu";
	67	compatible = "arm,cortex-a7";
	68	reg = <0x101>;
a2bdc32a	69	cci-control-port = <&cci_control2>;
d2e5c871	70	cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
b01c3994	71	capacity-dmips-mhz = <516>;
375faa93 PM	72	};
	73
	74	cpu4: cpu@4 {
	75	device_type = "cpu";
	76	compatible = "arm,cortex-a7";
	77	reg = <0x102>;
a2bdc32a	78	cci-control-port = <&cci_control2>;
d2e5c871	79	cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
b01c3994	80	capacity-dmips-mhz = <516>;
d2e5c871 LP	81	};
	82
	83	idle-states {
	84	CLUSTER_SLEEP_BIG: cluster-sleep-big {
	85	compatible = "arm,idle-state";
	86	local-timer-stop;
	87	entry-latency-us = <1000>;
	88	exit-latency-us = <700>;
	89	min-residency-us = <2000>;
	90	};
	91
	92	CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
	93	compatible = "arm,idle-state";
	94	local-timer-stop;
	95	entry-latency-us = <1000>;
	96	exit-latency-us = <500>;
	97	min-residency-us = <2500>;
	98	};
375faa93	99	};
375faa93 PM	100	};
	101
	102	memory@80000000 {
	103	device_type = "memory";
	104	reg = <0 0x80000000 0 0x40000000>;
	105	};
	106
f1fe12c8 LW	107	reserved-memory {
	108	#address-cells = <2>;
	109	#size-cells = <2>;
	110	ranges;
	111
	112	/* Chipselect 2 is physically at 0x18000000 */
	113	vram: vram@18000000 {
	114	/* 8 MB of designated video RAM */
	115	compatible = "shared-dma-pool";
	116	reg = <0 0x18000000 0 0x00800000>;
	117	no-map;
	118	};
	119	};
	120
375faa93 PM	121	wdt@2a490000 {
	122	compatible = "arm,sp805", "arm,primecell";
	123	reg = <0 0x2a490000 0 0x1000>;
aab7da70	124	interrupts = <0 98 4>;
842839a3 PM	125	clocks = <&oscclk6a>, <&oscclk6a>;
842839a3 PM	126	clock-names = "wdogclk", "apb_pclk";
375faa93 PM	127	};
	128
	129	hdlcd@2b000000 {
	130	compatible = "arm,hdlcd";
	131	reg = <0 0x2b000000 0 0x1000>;
	132	interrupts = <0 85 4>;
2cff6dba	133	clocks = <&hdlcd_clk>;
842839a3	134	clock-names = "pxlclk";
375faa93 PM	135	};
	136
	137	memory-controller@2b0a0000 {
	138	compatible = "arm,pl341", "arm,primecell";
	139	reg = <0 0x2b0a0000 0 0x1000>;
842839a3 PM	140	clocks = <&oscclk6a>;
842839a3 PM	141	clock-names = "apb_pclk";
375faa93 PM	142	};
	143
	144	gic: interrupt-controller@2c001000 {
	145	compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
	146	#interrupt-cells = <3>;
	147	#address-cells = <0>;
	148	interrupt-controller;
	149	reg = <0 0x2c001000 0 0x1000>,
368400e2	150	<0 0x2c002000 0 0x2000>,
375faa93 PM	151	<0 0x2c004000 0 0x2000>,
	152	<0 0x2c006000 0 0x2000>;
	153	interrupts = <1 9 0xf04>;
	154	};
	155
a2bdc32a JMT	156	cci@2c090000 {
	157	compatible = "arm,cci-400";
	158	#address-cells = <1>;
	159	#size-cells = <1>;
	160	reg = <0 0x2c090000 0 0x1000>;
	161	ranges = <0x0 0x0 0x2c090000 0x10000>;
	162
	163	cci_control1: slave-if@4000 {
	164	compatible = "arm,cci-400-ctrl-if";
	165	interface-type = "ace";
	166	reg = <0x4000 0x1000>;
	167	};
	168
	169	cci_control2: slave-if@5000 {
	170	compatible = "arm,cci-400-ctrl-if";
	171	interface-type = "ace";
	172	reg = <0x5000 0x1000>;
	173	};
3adf7aaa SH	174
	175	pmu@9000 {
	176	compatible = "arm,cci-400-pmu,r0";
	177	reg = <0x9000 0x5000>;
	178	interrupts = <0 105 4>,
	179	<0 101 4>,
	180	<0 102 4>,
	181	<0 103 4>,
	182	<0 104 4>;
	183	};
a2bdc32a JMT	184	};
a2bdc32a JMT	185
375faa93 PM	186	memory-controller@7ffd0000 {
	187	compatible = "arm,pl354", "arm,primecell";
	188	reg = <0 0x7ffd0000 0 0x1000>;
	189	interrupts = <0 86 4>,
	190	<0 87 4>;
842839a3 PM	191	clocks = <&oscclk6a>;
842839a3 PM	192	clock-names = "apb_pclk";
375faa93 PM	193	};
	194
	195	dma@7ff00000 {
	196	compatible = "arm,pl330", "arm,primecell";
	197	reg = <0 0x7ff00000 0 0x1000>;
	198	interrupts = <0 92 4>,
	199	<0 88 4>,
	200	<0 89 4>,
	201	<0 90 4>,
	202	<0 91 4>;
842839a3 PM	203	clocks = <&oscclk6a>;
842839a3 PM	204	clock-names = "apb_pclk";
375faa93 PM	205	};
375faa93 PM	206
ceca0e1c PM	207	scc@7fff0000 {
	208	compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
	209	reg = <0 0x7fff0000 0 0x1000>;
	210	interrupts = <0 95 4>;
	211	};
	212
375faa93 PM	213	timer {
	214	compatible = "arm,armv7-timer";
	215	interrupts = <1 13 0xf08>,
	216	<1 14 0xf08>,
	217	<1 11 0xf08>,
	218	<1 10 0xf08>;
	219	};
	220
b67b00ee	221	pmu-a15 {
7e16063b	222	compatible = "arm,cortex-a15-pmu";
375faa93 PM	223	interrupts = <0 68 4>,
375faa93 PM	224	<0 69 4>;
4d44f2a0 MR	225	interrupt-affinity = <&cpu0>,
	226	<&cpu1>;
	227	};
	228
b67b00ee	229	pmu-a7 {
4d44f2a0 MR	230	compatible = "arm,cortex-a7-pmu";
	231	interrupts = <0 128 4>,
	232	<0 129 4>,
	233	<0 130 4>;
	234	interrupt-affinity = <&cpu2>,
	235	<&cpu3>,
	236	<&cpu4>;
375faa93 PM	237	};
375faa93 PM	238
842839a3 PM	239	oscclk6a: oscclk6a {
	240	/* Reference 24MHz clock */
	241	compatible = "fixed-clock";
	242	#clock-cells = <0>;
	243	clock-frequency = <24000000>;
	244	clock-output-names = "oscclk6a";
	245	};
	246
	247	dcc {
	248	compatible = "arm,vexpress,config-bus";
	249	arm,vexpress,config-bridge = <&v2m_sysreg>;
	250
2cff6dba	251	oscclk0 {
842839a3 PM	252	/* A15 PLL 0 reference clock */
	253	compatible = "arm,vexpress-osc";
	254	arm,vexpress-sysreg,func = <1 0>;
	255	freq-range = <17000000 50000000>;
	256	#clock-cells = <0>;
	257	clock-output-names = "oscclk0";
	258	};
	259
2cff6dba	260	oscclk1 {
842839a3 PM	261	/* A15 PLL 1 reference clock */
	262	compatible = "arm,vexpress-osc";
	263	arm,vexpress-sysreg,func = <1 1>;
	264	freq-range = <17000000 50000000>;
	265	#clock-cells = <0>;
	266	clock-output-names = "oscclk1";
	267	};
	268
2cff6dba	269	oscclk2 {
842839a3 PM	270	/* A7 PLL 0 reference clock */
	271	compatible = "arm,vexpress-osc";
	272	arm,vexpress-sysreg,func = <1 2>;
	273	freq-range = <17000000 50000000>;
	274	#clock-cells = <0>;
	275	clock-output-names = "oscclk2";
	276	};
	277
2cff6dba	278	oscclk3 {
842839a3 PM	279	/* A7 PLL 1 reference clock */
	280	compatible = "arm,vexpress-osc";
	281	arm,vexpress-sysreg,func = <1 3>;
	282	freq-range = <17000000 50000000>;
	283	#clock-cells = <0>;
	284	clock-output-names = "oscclk3";
	285	};
	286
2cff6dba	287	oscclk4 {
842839a3 PM	288	/* External AXI master clock */
	289	compatible = "arm,vexpress-osc";
	290	arm,vexpress-sysreg,func = <1 4>;
	291	freq-range = <20000000 40000000>;
	292	#clock-cells = <0>;
	293	clock-output-names = "oscclk4";
	294	};
	295
2cff6dba	296	hdlcd_clk: oscclk5 {
842839a3 PM	297	/* HDLCD PLL reference clock */
	298	compatible = "arm,vexpress-osc";
	299	arm,vexpress-sysreg,func = <1 5>;
	300	freq-range = <23750000 165000000>;
	301	#clock-cells = <0>;
	302	clock-output-names = "oscclk5";
	303	};
	304
2cff6dba	305	smbclk: oscclk6 {
842839a3 PM	306	/* Static memory controller clock */
	307	compatible = "arm,vexpress-osc";
	308	arm,vexpress-sysreg,func = <1 6>;
	309	freq-range = <20000000 40000000>;
	310	#clock-cells = <0>;
	311	clock-output-names = "oscclk6";
	312	};
	313
2cff6dba	314	oscclk7 {
842839a3 PM	315	/* SYS PLL reference clock */
	316	compatible = "arm,vexpress-osc";
	317	arm,vexpress-sysreg,func = <1 7>;
	318	freq-range = <17000000 50000000>;
	319	#clock-cells = <0>;
	320	clock-output-names = "oscclk7";
	321	};
	322
2cff6dba	323	oscclk8 {
842839a3 PM	324	/* DDR2 PLL reference clock */
	325	compatible = "arm,vexpress-osc";
	326	arm,vexpress-sysreg,func = <1 8>;
	327	freq-range = <20000000 50000000>;
	328	#clock-cells = <0>;
	329	clock-output-names = "oscclk8";
	330	};
	331
2cff6dba	332	volt-a15 {
842839a3 PM	333	/* A15 CPU core voltage */
	334	compatible = "arm,vexpress-volt";
	335	arm,vexpress-sysreg,func = <2 0>;
	336	regulator-name = "A15 Vcore";
	337	regulator-min-microvolt = <800000>;
	338	regulator-max-microvolt = <1050000>;
	339	regulator-always-on;
	340	label = "A15 Vcore";
	341	};
	342
2cff6dba	343	volt-a7 {
842839a3 PM	344	/* A7 CPU core voltage */
	345	compatible = "arm,vexpress-volt";
	346	arm,vexpress-sysreg,func = <2 1>;
	347	regulator-name = "A7 Vcore";
	348	regulator-min-microvolt = <800000>;
	349	regulator-max-microvolt = <1050000>;
	350	regulator-always-on;
	351	label = "A7 Vcore";
	352	};
	353
2cff6dba	354	amp-a15 {
842839a3 PM	355	/* Total current for the two A15 cores */
	356	compatible = "arm,vexpress-amp";
	357	arm,vexpress-sysreg,func = <3 0>;
	358	label = "A15 Icore";
	359	};
	360
2cff6dba	361	amp-a7 {
842839a3 PM	362	/* Total current for the three A7 cores */
	363	compatible = "arm,vexpress-amp";
	364	arm,vexpress-sysreg,func = <3 1>;
	365	label = "A7 Icore";
	366	};
	367
2cff6dba	368	temp-dcc {
842839a3 PM	369	/* DCC internal temperature */
	370	compatible = "arm,vexpress-temp";
	371	arm,vexpress-sysreg,func = <4 0>;
	372	label = "DCC";
	373	};
	374
2cff6dba	375	power-a15 {
842839a3 PM	376	/* Total power for the two A15 cores */
	377	compatible = "arm,vexpress-power";
	378	arm,vexpress-sysreg,func = <12 0>;
	379	label = "A15 Pcore";
	380	};
3b9334ac	381
2cff6dba	382	power-a7 {
842839a3 PM	383	/* Total power for the three A7 cores */
	384	compatible = "arm,vexpress-power";
	385	arm,vexpress-sysreg,func = <12 1>;
	386	label = "A7 Pcore";
	387	};
	388
2cff6dba	389	energy-a15 {
842839a3 PM	390	/* Total energy for the two A15 cores */
842839a3 PM	391	compatible = "arm,vexpress-energy";
3b9334ac	392	arm,vexpress-sysreg,func = <13 0>, <13 1>;
842839a3 PM	393	label = "A15 Jcore";
	394	};
	395
2cff6dba	396	energy-a7 {
842839a3 PM	397	/* Total energy for the three A7 cores */
842839a3 PM	398	compatible = "arm,vexpress-energy";
3b9334ac	399	arm,vexpress-sysreg,func = <13 2>, <13 3>;
842839a3 PM	400	label = "A7 Jcore";
	401	};
	402	};
	403
e6a7efad	404	etb@20010000 {
0bec8d82 MP	405	compatible = "arm,coresight-etb10", "arm,primecell";
	406	reg = <0 0x20010000 0 0x1000>;
	407
0bec8d82 MP	408	clocks = <&oscclk6a>;
	409	clock-names = "apb_pclk";
	410	port {
2cff6dba	411	etb_in_port: endpoint {
0bec8d82 MP	412	slave-mode;
	413	remote-endpoint = <&replicator_out_port0>;
	414	};
	415	};
	416	};
	417
e6a7efad	418	tpiu@20030000 {
0bec8d82 MP	419	compatible = "arm,coresight-tpiu", "arm,primecell";
	420	reg = <0 0x20030000 0 0x1000>;
	421
	422	clocks = <&oscclk6a>;
	423	clock-names = "apb_pclk";
	424	port {
2cff6dba	425	tpiu_in_port: endpoint {
0bec8d82 MP	426	slave-mode;
	427	remote-endpoint = <&replicator_out_port1>;
	428	};
	429	};
	430	};
	431
	432	replicator {
	433	/* non-configurable replicators don't show up on the
	434	* AMBA bus. As such no need to add "arm,primecell".
	435	*/
	436	compatible = "arm,coresight-replicator";
	437
	438	ports {
	439	#address-cells = <1>;
	440	#size-cells = <0>;
	441
	442	/* replicator output ports */
	443	port@0 {
	444	reg = <0>;
	445	replicator_out_port0: endpoint {
	446	remote-endpoint = <&etb_in_port>;
	447	};
	448	};
	449
	450	port@1 {
	451	reg = <1>;
	452	replicator_out_port1: endpoint {
	453	remote-endpoint = <&tpiu_in_port>;
	454	};
	455	};
	456
	457	/* replicator input port */
	458	port@2 {
	459	reg = <0>;
	460	replicator_in_port0: endpoint {
	461	slave-mode;
	462	remote-endpoint = <&funnel_out_port0>;
	463	};
	464	};
	465	};
	466	};
	467
e6a7efad	468	funnel@20040000 {
0bec8d82 MP	469	compatible = "arm,coresight-funnel", "arm,primecell";
	470	reg = <0 0x20040000 0 0x1000>;
	471
	472	clocks = <&oscclk6a>;
	473	clock-names = "apb_pclk";
	474	ports {
	475	#address-cells = <1>;
	476	#size-cells = <0>;
	477
	478	/* funnel output port */
	479	port@0 {
	480	reg = <0>;
	481	funnel_out_port0: endpoint {
	482	remote-endpoint =
	483	<&replicator_in_port0>;
	484	};
	485	};
	486
	487	/* funnel input ports */
	488	port@1 {
	489	reg = <0>;
	490	funnel_in_port0: endpoint {
	491	slave-mode;
	492	remote-endpoint = <&ptm0_out_port>;
	493	};
	494	};
	495
	496	port@2 {
	497	reg = <1>;
	498	funnel_in_port1: endpoint {
	499	slave-mode;
	500	remote-endpoint = <&ptm1_out_port>;
	501	};
	502	};
	503
	504	port@3 {
	505	reg = <2>;
	506	funnel_in_port2: endpoint {
	507	slave-mode;
	508	remote-endpoint = <&etm0_out_port>;
	509	};
	510	};
	511
	512	/* Input port #3 is for ITM, not supported here */
	513
	514	port@4 {
	515	reg = <4>;
	516	funnel_in_port4: endpoint {
	517	slave-mode;
	518	remote-endpoint = <&etm1_out_port>;
	519	};
	520	};
	521
	522	port@5 {
	523	reg = <5>;
	524	funnel_in_port5: endpoint {
	525	slave-mode;
	526	remote-endpoint = <&etm2_out_port>;
	527	};
	528	};
	529	};
	530	};
	531
e6a7efad	532	ptm@2201c000 {
0bec8d82 MP	533	compatible = "arm,coresight-etm3x", "arm,primecell";
	534	reg = <0 0x2201c000 0 0x1000>;
	535
	536	cpu = <&cpu0>;
	537	clocks = <&oscclk6a>;
	538	clock-names = "apb_pclk";
	539	port {
	540	ptm0_out_port: endpoint {
	541	remote-endpoint = <&funnel_in_port0>;
	542	};
	543	};
	544	};
	545
e6a7efad	546	ptm@2201d000 {
0bec8d82 MP	547	compatible = "arm,coresight-etm3x", "arm,primecell";
	548	reg = <0 0x2201d000 0 0x1000>;
	549
	550	cpu = <&cpu1>;
	551	clocks = <&oscclk6a>;
	552	clock-names = "apb_pclk";
	553	port {
	554	ptm1_out_port: endpoint {
	555	remote-endpoint = <&funnel_in_port1>;
	556	};
	557	};
	558	};
	559
e6a7efad	560	etm@2203c000 {
0bec8d82 MP	561	compatible = "arm,coresight-etm3x", "arm,primecell";
	562	reg = <0 0x2203c000 0 0x1000>;
	563
	564	cpu = <&cpu2>;
	565	clocks = <&oscclk6a>;
	566	clock-names = "apb_pclk";
	567	port {
	568	etm0_out_port: endpoint {
	569	remote-endpoint = <&funnel_in_port2>;
	570	};
	571	};
	572	};
	573
e6a7efad	574	etm@2203d000 {
0bec8d82 MP	575	compatible = "arm,coresight-etm3x", "arm,primecell";
	576	reg = <0 0x2203d000 0 0x1000>;
	577
	578	cpu = <&cpu3>;
	579	clocks = <&oscclk6a>;
	580	clock-names = "apb_pclk";
	581	port {
	582	etm1_out_port: endpoint {
	583	remote-endpoint = <&funnel_in_port4>;
	584	};
	585	};
	586	};
	587
e6a7efad	588	etm@2203e000 {
0bec8d82 MP	589	compatible = "arm,coresight-etm3x", "arm,primecell";
	590	reg = <0 0x2203e000 0 0x1000>;
	591
	592	cpu = <&cpu4>;
	593	clocks = <&oscclk6a>;
	594	clock-names = "apb_pclk";
	595	port {
	596	etm2_out_port: endpoint {
	597	remote-endpoint = <&funnel_in_port5>;
	598	};
	599	};
	600	};
	601
bd7aff03	602	smb: smb@8000000 {
433683a6 PM	603	compatible = "simple-bus";
	604
	605	#address-cells = <2>;
	606	#size-cells = <1>;
375faa93 PM	607	ranges = <0 0 0 0x08000000 0x04000000>,
	608	<1 0 0 0x14000000 0x04000000>,
	609	<2 0 0 0x18000000 0x04000000>,
	610	<3 0 0 0x1c000000 0x04000000>,
	611	<4 0 0 0x0c000000 0x04000000>,
	612	<5 0 0 0x10000000 0x04000000>;
	613
433683a6	614	#interrupt-cells = <1>;
375faa93 PM	615	interrupt-map-mask = <0 0 63>;
	616	interrupt-map = <0 0 0 &gic 0 0 4>,
	617	<0 0 1 &gic 0 1 4>,
	618	<0 0 2 &gic 0 2 4>,
	619	<0 0 3 &gic 0 3 4>,
	620	<0 0 4 &gic 0 4 4>,
	621	<0 0 5 &gic 0 5 4>,
	622	<0 0 6 &gic 0 6 4>,
	623	<0 0 7 &gic 0 7 4>,
	624	<0 0 8 &gic 0 8 4>,
	625	<0 0 9 &gic 0 9 4>,
	626	<0 0 10 &gic 0 10 4>,
	627	<0 0 11 &gic 0 11 4>,
	628	<0 0 12 &gic 0 12 4>,
	629	<0 0 13 &gic 0 13 4>,
	630	<0 0 14 &gic 0 14 4>,
	631	<0 0 15 &gic 0 15 4>,
	632	<0 0 16 &gic 0 16 4>,
	633	<0 0 17 &gic 0 17 4>,
	634	<0 0 18 &gic 0 18 4>,
	635	<0 0 19 &gic 0 19 4>,
	636	<0 0 20 &gic 0 20 4>,
	637	<0 0 21 &gic 0 21 4>,
	638	<0 0 22 &gic 0 22 4>,
	639	<0 0 23 &gic 0 23 4>,
	640	<0 0 24 &gic 0 24 4>,
	641	<0 0 25 &gic 0 25 4>,
	642	<0 0 26 &gic 0 26 4>,
	643	<0 0 27 &gic 0 27 4>,
	644	<0 0 28 &gic 0 28 4>,
	645	<0 0 29 &gic 0 29 4>,
	646	<0 0 30 &gic 0 30 4>,
	647	<0 0 31 &gic 0 31 4>,
	648	<0 0 32 &gic 0 32 4>,
	649	<0 0 33 &gic 0 33 4>,
	650	<0 0 34 &gic 0 34 4>,
	651	<0 0 35 &gic 0 35 4>,
	652	<0 0 36 &gic 0 36 4>,
	653	<0 0 37 &gic 0 37 4>,
	654	<0 0 38 &gic 0 38 4>,
	655	<0 0 39 &gic 0 39 4>,
	656	<0 0 40 &gic 0 40 4>,
	657	<0 0 41 &gic 0 41 4>,
	658	<0 0 42 &gic 0 42 4>;
	659	};
2b4e38fd BS	660
	661	site2: hsb@40000000 {
	662	compatible = "simple-bus";
	663	#address-cells = <1>;
	664	#size-cells = <1>;
	665	ranges = <0 0 0x40000000 0x3fef0000>;
	666	#interrupt-cells = <1>;
	667	interrupt-map-mask = <0 3>;
	668	interrupt-map = <0 0 &gic 0 36 4>,
	669	<0 1 &gic 0 37 4>,
	670	<0 2 &gic 0 38 4>,
	671	<0 3 &gic 0 39 4>;
	672	};
375faa93	673	};