Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
375faa93 PM |
2 | /* |
3 | * ARM Ltd. Versatile Express | |
4 | * | |
5 | * CoreTile Express A15x2 A7x3 | |
6 | * Cortex-A15_A7 MPCore (V2P-CA15_A7) | |
7 | * | |
8 | * HBI-0249A | |
9 | */ | |
10 | ||
11 | /dts-v1/; | |
12 | ||
13 | / { | |
14 | model = "V2P-CA15_CA7"; | |
15 | arm,hbi = <0x249>; | |
842839a3 | 16 | arm,vexpress,site = <0xf>; |
375faa93 PM |
17 | compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; |
18 | interrupt-parent = <&gic>; | |
19 | #address-cells = <2>; | |
20 | #size-cells = <2>; | |
21 | ||
22 | chosen { }; | |
23 | ||
24 | aliases { | |
25 | serial0 = &v2m_serial0; | |
26 | serial1 = &v2m_serial1; | |
27 | serial2 = &v2m_serial2; | |
28 | serial3 = &v2m_serial3; | |
29 | i2c0 = &v2m_i2c_dvi; | |
30 | i2c1 = &v2m_i2c_pcie; | |
31 | }; | |
32 | ||
33 | cpus { | |
34 | #address-cells = <1>; | |
35 | #size-cells = <0>; | |
36 | ||
37 | cpu0: cpu@0 { | |
38 | device_type = "cpu"; | |
39 | compatible = "arm,cortex-a15"; | |
40 | reg = <0>; | |
a2bdc32a | 41 | cci-control-port = <&cci_control1>; |
d2e5c871 | 42 | cpu-idle-states = <&CLUSTER_SLEEP_BIG>; |
b01c3994 | 43 | capacity-dmips-mhz = <1024>; |
375faa93 PM |
44 | }; |
45 | ||
46 | cpu1: cpu@1 { | |
47 | device_type = "cpu"; | |
48 | compatible = "arm,cortex-a15"; | |
49 | reg = <1>; | |
a2bdc32a | 50 | cci-control-port = <&cci_control1>; |
d2e5c871 | 51 | cpu-idle-states = <&CLUSTER_SLEEP_BIG>; |
b01c3994 | 52 | capacity-dmips-mhz = <1024>; |
375faa93 PM |
53 | }; |
54 | ||
375faa93 PM |
55 | cpu2: cpu@2 { |
56 | device_type = "cpu"; | |
57 | compatible = "arm,cortex-a7"; | |
58 | reg = <0x100>; | |
a2bdc32a | 59 | cci-control-port = <&cci_control2>; |
d2e5c871 | 60 | cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; |
b01c3994 | 61 | capacity-dmips-mhz = <516>; |
375faa93 PM |
62 | }; |
63 | ||
64 | cpu3: cpu@3 { | |
65 | device_type = "cpu"; | |
66 | compatible = "arm,cortex-a7"; | |
67 | reg = <0x101>; | |
a2bdc32a | 68 | cci-control-port = <&cci_control2>; |
d2e5c871 | 69 | cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; |
b01c3994 | 70 | capacity-dmips-mhz = <516>; |
375faa93 PM |
71 | }; |
72 | ||
73 | cpu4: cpu@4 { | |
74 | device_type = "cpu"; | |
75 | compatible = "arm,cortex-a7"; | |
76 | reg = <0x102>; | |
a2bdc32a | 77 | cci-control-port = <&cci_control2>; |
d2e5c871 | 78 | cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; |
b01c3994 | 79 | capacity-dmips-mhz = <516>; |
d2e5c871 LP |
80 | }; |
81 | ||
82 | idle-states { | |
83 | CLUSTER_SLEEP_BIG: cluster-sleep-big { | |
84 | compatible = "arm,idle-state"; | |
85 | local-timer-stop; | |
86 | entry-latency-us = <1000>; | |
87 | exit-latency-us = <700>; | |
88 | min-residency-us = <2000>; | |
89 | }; | |
90 | ||
91 | CLUSTER_SLEEP_LITTLE: cluster-sleep-little { | |
92 | compatible = "arm,idle-state"; | |
93 | local-timer-stop; | |
94 | entry-latency-us = <1000>; | |
95 | exit-latency-us = <500>; | |
96 | min-residency-us = <2500>; | |
97 | }; | |
375faa93 | 98 | }; |
375faa93 PM |
99 | }; |
100 | ||
101 | memory@80000000 { | |
102 | device_type = "memory"; | |
103 | reg = <0 0x80000000 0 0x40000000>; | |
104 | }; | |
105 | ||
106 | wdt@2a490000 { | |
107 | compatible = "arm,sp805", "arm,primecell"; | |
108 | reg = <0 0x2a490000 0 0x1000>; | |
aab7da70 | 109 | interrupts = <0 98 4>; |
842839a3 PM |
110 | clocks = <&oscclk6a>, <&oscclk6a>; |
111 | clock-names = "wdogclk", "apb_pclk"; | |
375faa93 PM |
112 | }; |
113 | ||
114 | hdlcd@2b000000 { | |
115 | compatible = "arm,hdlcd"; | |
116 | reg = <0 0x2b000000 0 0x1000>; | |
117 | interrupts = <0 85 4>; | |
2cff6dba | 118 | clocks = <&hdlcd_clk>; |
842839a3 | 119 | clock-names = "pxlclk"; |
375faa93 PM |
120 | }; |
121 | ||
122 | memory-controller@2b0a0000 { | |
123 | compatible = "arm,pl341", "arm,primecell"; | |
124 | reg = <0 0x2b0a0000 0 0x1000>; | |
842839a3 PM |
125 | clocks = <&oscclk6a>; |
126 | clock-names = "apb_pclk"; | |
375faa93 PM |
127 | }; |
128 | ||
129 | gic: interrupt-controller@2c001000 { | |
130 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | |
131 | #interrupt-cells = <3>; | |
132 | #address-cells = <0>; | |
133 | interrupt-controller; | |
134 | reg = <0 0x2c001000 0 0x1000>, | |
368400e2 | 135 | <0 0x2c002000 0 0x2000>, |
375faa93 PM |
136 | <0 0x2c004000 0 0x2000>, |
137 | <0 0x2c006000 0 0x2000>; | |
138 | interrupts = <1 9 0xf04>; | |
139 | }; | |
140 | ||
a2bdc32a JMT |
141 | cci@2c090000 { |
142 | compatible = "arm,cci-400"; | |
143 | #address-cells = <1>; | |
144 | #size-cells = <1>; | |
145 | reg = <0 0x2c090000 0 0x1000>; | |
146 | ranges = <0x0 0x0 0x2c090000 0x10000>; | |
147 | ||
148 | cci_control1: slave-if@4000 { | |
149 | compatible = "arm,cci-400-ctrl-if"; | |
150 | interface-type = "ace"; | |
151 | reg = <0x4000 0x1000>; | |
152 | }; | |
153 | ||
154 | cci_control2: slave-if@5000 { | |
155 | compatible = "arm,cci-400-ctrl-if"; | |
156 | interface-type = "ace"; | |
157 | reg = <0x5000 0x1000>; | |
158 | }; | |
3adf7aaa SH |
159 | |
160 | pmu@9000 { | |
161 | compatible = "arm,cci-400-pmu,r0"; | |
162 | reg = <0x9000 0x5000>; | |
163 | interrupts = <0 105 4>, | |
164 | <0 101 4>, | |
165 | <0 102 4>, | |
166 | <0 103 4>, | |
167 | <0 104 4>; | |
168 | }; | |
a2bdc32a JMT |
169 | }; |
170 | ||
375faa93 PM |
171 | memory-controller@7ffd0000 { |
172 | compatible = "arm,pl354", "arm,primecell"; | |
173 | reg = <0 0x7ffd0000 0 0x1000>; | |
174 | interrupts = <0 86 4>, | |
175 | <0 87 4>; | |
842839a3 PM |
176 | clocks = <&oscclk6a>; |
177 | clock-names = "apb_pclk"; | |
375faa93 PM |
178 | }; |
179 | ||
180 | dma@7ff00000 { | |
181 | compatible = "arm,pl330", "arm,primecell"; | |
182 | reg = <0 0x7ff00000 0 0x1000>; | |
183 | interrupts = <0 92 4>, | |
184 | <0 88 4>, | |
185 | <0 89 4>, | |
186 | <0 90 4>, | |
187 | <0 91 4>; | |
842839a3 PM |
188 | clocks = <&oscclk6a>; |
189 | clock-names = "apb_pclk"; | |
375faa93 PM |
190 | }; |
191 | ||
ceca0e1c PM |
192 | scc@7fff0000 { |
193 | compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; | |
194 | reg = <0 0x7fff0000 0 0x1000>; | |
195 | interrupts = <0 95 4>; | |
196 | }; | |
197 | ||
375faa93 PM |
198 | timer { |
199 | compatible = "arm,armv7-timer"; | |
200 | interrupts = <1 13 0xf08>, | |
201 | <1 14 0xf08>, | |
202 | <1 11 0xf08>, | |
203 | <1 10 0xf08>; | |
204 | }; | |
205 | ||
4d44f2a0 | 206 | pmu_a15 { |
7e16063b | 207 | compatible = "arm,cortex-a15-pmu"; |
375faa93 PM |
208 | interrupts = <0 68 4>, |
209 | <0 69 4>; | |
4d44f2a0 MR |
210 | interrupt-affinity = <&cpu0>, |
211 | <&cpu1>; | |
212 | }; | |
213 | ||
214 | pmu_a7 { | |
215 | compatible = "arm,cortex-a7-pmu"; | |
216 | interrupts = <0 128 4>, | |
217 | <0 129 4>, | |
218 | <0 130 4>; | |
219 | interrupt-affinity = <&cpu2>, | |
220 | <&cpu3>, | |
221 | <&cpu4>; | |
375faa93 PM |
222 | }; |
223 | ||
842839a3 PM |
224 | oscclk6a: oscclk6a { |
225 | /* Reference 24MHz clock */ | |
226 | compatible = "fixed-clock"; | |
227 | #clock-cells = <0>; | |
228 | clock-frequency = <24000000>; | |
229 | clock-output-names = "oscclk6a"; | |
230 | }; | |
231 | ||
232 | dcc { | |
233 | compatible = "arm,vexpress,config-bus"; | |
234 | arm,vexpress,config-bridge = <&v2m_sysreg>; | |
235 | ||
2cff6dba | 236 | oscclk0 { |
842839a3 PM |
237 | /* A15 PLL 0 reference clock */ |
238 | compatible = "arm,vexpress-osc"; | |
239 | arm,vexpress-sysreg,func = <1 0>; | |
240 | freq-range = <17000000 50000000>; | |
241 | #clock-cells = <0>; | |
242 | clock-output-names = "oscclk0"; | |
243 | }; | |
244 | ||
2cff6dba | 245 | oscclk1 { |
842839a3 PM |
246 | /* A15 PLL 1 reference clock */ |
247 | compatible = "arm,vexpress-osc"; | |
248 | arm,vexpress-sysreg,func = <1 1>; | |
249 | freq-range = <17000000 50000000>; | |
250 | #clock-cells = <0>; | |
251 | clock-output-names = "oscclk1"; | |
252 | }; | |
253 | ||
2cff6dba | 254 | oscclk2 { |
842839a3 PM |
255 | /* A7 PLL 0 reference clock */ |
256 | compatible = "arm,vexpress-osc"; | |
257 | arm,vexpress-sysreg,func = <1 2>; | |
258 | freq-range = <17000000 50000000>; | |
259 | #clock-cells = <0>; | |
260 | clock-output-names = "oscclk2"; | |
261 | }; | |
262 | ||
2cff6dba | 263 | oscclk3 { |
842839a3 PM |
264 | /* A7 PLL 1 reference clock */ |
265 | compatible = "arm,vexpress-osc"; | |
266 | arm,vexpress-sysreg,func = <1 3>; | |
267 | freq-range = <17000000 50000000>; | |
268 | #clock-cells = <0>; | |
269 | clock-output-names = "oscclk3"; | |
270 | }; | |
271 | ||
2cff6dba | 272 | oscclk4 { |
842839a3 PM |
273 | /* External AXI master clock */ |
274 | compatible = "arm,vexpress-osc"; | |
275 | arm,vexpress-sysreg,func = <1 4>; | |
276 | freq-range = <20000000 40000000>; | |
277 | #clock-cells = <0>; | |
278 | clock-output-names = "oscclk4"; | |
279 | }; | |
280 | ||
2cff6dba | 281 | hdlcd_clk: oscclk5 { |
842839a3 PM |
282 | /* HDLCD PLL reference clock */ |
283 | compatible = "arm,vexpress-osc"; | |
284 | arm,vexpress-sysreg,func = <1 5>; | |
285 | freq-range = <23750000 165000000>; | |
286 | #clock-cells = <0>; | |
287 | clock-output-names = "oscclk5"; | |
288 | }; | |
289 | ||
2cff6dba | 290 | smbclk: oscclk6 { |
842839a3 PM |
291 | /* Static memory controller clock */ |
292 | compatible = "arm,vexpress-osc"; | |
293 | arm,vexpress-sysreg,func = <1 6>; | |
294 | freq-range = <20000000 40000000>; | |
295 | #clock-cells = <0>; | |
296 | clock-output-names = "oscclk6"; | |
297 | }; | |
298 | ||
2cff6dba | 299 | oscclk7 { |
842839a3 PM |
300 | /* SYS PLL reference clock */ |
301 | compatible = "arm,vexpress-osc"; | |
302 | arm,vexpress-sysreg,func = <1 7>; | |
303 | freq-range = <17000000 50000000>; | |
304 | #clock-cells = <0>; | |
305 | clock-output-names = "oscclk7"; | |
306 | }; | |
307 | ||
2cff6dba | 308 | oscclk8 { |
842839a3 PM |
309 | /* DDR2 PLL reference clock */ |
310 | compatible = "arm,vexpress-osc"; | |
311 | arm,vexpress-sysreg,func = <1 8>; | |
312 | freq-range = <20000000 50000000>; | |
313 | #clock-cells = <0>; | |
314 | clock-output-names = "oscclk8"; | |
315 | }; | |
316 | ||
2cff6dba | 317 | volt-a15 { |
842839a3 PM |
318 | /* A15 CPU core voltage */ |
319 | compatible = "arm,vexpress-volt"; | |
320 | arm,vexpress-sysreg,func = <2 0>; | |
321 | regulator-name = "A15 Vcore"; | |
322 | regulator-min-microvolt = <800000>; | |
323 | regulator-max-microvolt = <1050000>; | |
324 | regulator-always-on; | |
325 | label = "A15 Vcore"; | |
326 | }; | |
327 | ||
2cff6dba | 328 | volt-a7 { |
842839a3 PM |
329 | /* A7 CPU core voltage */ |
330 | compatible = "arm,vexpress-volt"; | |
331 | arm,vexpress-sysreg,func = <2 1>; | |
332 | regulator-name = "A7 Vcore"; | |
333 | regulator-min-microvolt = <800000>; | |
334 | regulator-max-microvolt = <1050000>; | |
335 | regulator-always-on; | |
336 | label = "A7 Vcore"; | |
337 | }; | |
338 | ||
2cff6dba | 339 | amp-a15 { |
842839a3 PM |
340 | /* Total current for the two A15 cores */ |
341 | compatible = "arm,vexpress-amp"; | |
342 | arm,vexpress-sysreg,func = <3 0>; | |
343 | label = "A15 Icore"; | |
344 | }; | |
345 | ||
2cff6dba | 346 | amp-a7 { |
842839a3 PM |
347 | /* Total current for the three A7 cores */ |
348 | compatible = "arm,vexpress-amp"; | |
349 | arm,vexpress-sysreg,func = <3 1>; | |
350 | label = "A7 Icore"; | |
351 | }; | |
352 | ||
2cff6dba | 353 | temp-dcc { |
842839a3 PM |
354 | /* DCC internal temperature */ |
355 | compatible = "arm,vexpress-temp"; | |
356 | arm,vexpress-sysreg,func = <4 0>; | |
357 | label = "DCC"; | |
358 | }; | |
359 | ||
2cff6dba | 360 | power-a15 { |
842839a3 PM |
361 | /* Total power for the two A15 cores */ |
362 | compatible = "arm,vexpress-power"; | |
363 | arm,vexpress-sysreg,func = <12 0>; | |
364 | label = "A15 Pcore"; | |
365 | }; | |
3b9334ac | 366 | |
2cff6dba | 367 | power-a7 { |
842839a3 PM |
368 | /* Total power for the three A7 cores */ |
369 | compatible = "arm,vexpress-power"; | |
370 | arm,vexpress-sysreg,func = <12 1>; | |
371 | label = "A7 Pcore"; | |
372 | }; | |
373 | ||
2cff6dba | 374 | energy-a15 { |
842839a3 PM |
375 | /* Total energy for the two A15 cores */ |
376 | compatible = "arm,vexpress-energy"; | |
3b9334ac | 377 | arm,vexpress-sysreg,func = <13 0>, <13 1>; |
842839a3 PM |
378 | label = "A15 Jcore"; |
379 | }; | |
380 | ||
2cff6dba | 381 | energy-a7 { |
842839a3 PM |
382 | /* Total energy for the three A7 cores */ |
383 | compatible = "arm,vexpress-energy"; | |
3b9334ac | 384 | arm,vexpress-sysreg,func = <13 2>, <13 3>; |
842839a3 PM |
385 | label = "A7 Jcore"; |
386 | }; | |
387 | }; | |
388 | ||
e6a7efad | 389 | etb@20010000 { |
0bec8d82 MP |
390 | compatible = "arm,coresight-etb10", "arm,primecell"; |
391 | reg = <0 0x20010000 0 0x1000>; | |
392 | ||
0bec8d82 MP |
393 | clocks = <&oscclk6a>; |
394 | clock-names = "apb_pclk"; | |
395 | port { | |
2cff6dba | 396 | etb_in_port: endpoint { |
0bec8d82 MP |
397 | slave-mode; |
398 | remote-endpoint = <&replicator_out_port0>; | |
399 | }; | |
400 | }; | |
401 | }; | |
402 | ||
e6a7efad | 403 | tpiu@20030000 { |
0bec8d82 MP |
404 | compatible = "arm,coresight-tpiu", "arm,primecell"; |
405 | reg = <0 0x20030000 0 0x1000>; | |
406 | ||
407 | clocks = <&oscclk6a>; | |
408 | clock-names = "apb_pclk"; | |
409 | port { | |
2cff6dba | 410 | tpiu_in_port: endpoint { |
0bec8d82 MP |
411 | slave-mode; |
412 | remote-endpoint = <&replicator_out_port1>; | |
413 | }; | |
414 | }; | |
415 | }; | |
416 | ||
417 | replicator { | |
418 | /* non-configurable replicators don't show up on the | |
419 | * AMBA bus. As such no need to add "arm,primecell". | |
420 | */ | |
421 | compatible = "arm,coresight-replicator"; | |
422 | ||
423 | ports { | |
424 | #address-cells = <1>; | |
425 | #size-cells = <0>; | |
426 | ||
427 | /* replicator output ports */ | |
428 | port@0 { | |
429 | reg = <0>; | |
430 | replicator_out_port0: endpoint { | |
431 | remote-endpoint = <&etb_in_port>; | |
432 | }; | |
433 | }; | |
434 | ||
435 | port@1 { | |
436 | reg = <1>; | |
437 | replicator_out_port1: endpoint { | |
438 | remote-endpoint = <&tpiu_in_port>; | |
439 | }; | |
440 | }; | |
441 | ||
442 | /* replicator input port */ | |
443 | port@2 { | |
444 | reg = <0>; | |
445 | replicator_in_port0: endpoint { | |
446 | slave-mode; | |
447 | remote-endpoint = <&funnel_out_port0>; | |
448 | }; | |
449 | }; | |
450 | }; | |
451 | }; | |
452 | ||
e6a7efad | 453 | funnel@20040000 { |
0bec8d82 MP |
454 | compatible = "arm,coresight-funnel", "arm,primecell"; |
455 | reg = <0 0x20040000 0 0x1000>; | |
456 | ||
457 | clocks = <&oscclk6a>; | |
458 | clock-names = "apb_pclk"; | |
459 | ports { | |
460 | #address-cells = <1>; | |
461 | #size-cells = <0>; | |
462 | ||
463 | /* funnel output port */ | |
464 | port@0 { | |
465 | reg = <0>; | |
466 | funnel_out_port0: endpoint { | |
467 | remote-endpoint = | |
468 | <&replicator_in_port0>; | |
469 | }; | |
470 | }; | |
471 | ||
472 | /* funnel input ports */ | |
473 | port@1 { | |
474 | reg = <0>; | |
475 | funnel_in_port0: endpoint { | |
476 | slave-mode; | |
477 | remote-endpoint = <&ptm0_out_port>; | |
478 | }; | |
479 | }; | |
480 | ||
481 | port@2 { | |
482 | reg = <1>; | |
483 | funnel_in_port1: endpoint { | |
484 | slave-mode; | |
485 | remote-endpoint = <&ptm1_out_port>; | |
486 | }; | |
487 | }; | |
488 | ||
489 | port@3 { | |
490 | reg = <2>; | |
491 | funnel_in_port2: endpoint { | |
492 | slave-mode; | |
493 | remote-endpoint = <&etm0_out_port>; | |
494 | }; | |
495 | }; | |
496 | ||
497 | /* Input port #3 is for ITM, not supported here */ | |
498 | ||
499 | port@4 { | |
500 | reg = <4>; | |
501 | funnel_in_port4: endpoint { | |
502 | slave-mode; | |
503 | remote-endpoint = <&etm1_out_port>; | |
504 | }; | |
505 | }; | |
506 | ||
507 | port@5 { | |
508 | reg = <5>; | |
509 | funnel_in_port5: endpoint { | |
510 | slave-mode; | |
511 | remote-endpoint = <&etm2_out_port>; | |
512 | }; | |
513 | }; | |
514 | }; | |
515 | }; | |
516 | ||
e6a7efad | 517 | ptm@2201c000 { |
0bec8d82 MP |
518 | compatible = "arm,coresight-etm3x", "arm,primecell"; |
519 | reg = <0 0x2201c000 0 0x1000>; | |
520 | ||
521 | cpu = <&cpu0>; | |
522 | clocks = <&oscclk6a>; | |
523 | clock-names = "apb_pclk"; | |
524 | port { | |
525 | ptm0_out_port: endpoint { | |
526 | remote-endpoint = <&funnel_in_port0>; | |
527 | }; | |
528 | }; | |
529 | }; | |
530 | ||
e6a7efad | 531 | ptm@2201d000 { |
0bec8d82 MP |
532 | compatible = "arm,coresight-etm3x", "arm,primecell"; |
533 | reg = <0 0x2201d000 0 0x1000>; | |
534 | ||
535 | cpu = <&cpu1>; | |
536 | clocks = <&oscclk6a>; | |
537 | clock-names = "apb_pclk"; | |
538 | port { | |
539 | ptm1_out_port: endpoint { | |
540 | remote-endpoint = <&funnel_in_port1>; | |
541 | }; | |
542 | }; | |
543 | }; | |
544 | ||
e6a7efad | 545 | etm@2203c000 { |
0bec8d82 MP |
546 | compatible = "arm,coresight-etm3x", "arm,primecell"; |
547 | reg = <0 0x2203c000 0 0x1000>; | |
548 | ||
549 | cpu = <&cpu2>; | |
550 | clocks = <&oscclk6a>; | |
551 | clock-names = "apb_pclk"; | |
552 | port { | |
553 | etm0_out_port: endpoint { | |
554 | remote-endpoint = <&funnel_in_port2>; | |
555 | }; | |
556 | }; | |
557 | }; | |
558 | ||
e6a7efad | 559 | etm@2203d000 { |
0bec8d82 MP |
560 | compatible = "arm,coresight-etm3x", "arm,primecell"; |
561 | reg = <0 0x2203d000 0 0x1000>; | |
562 | ||
563 | cpu = <&cpu3>; | |
564 | clocks = <&oscclk6a>; | |
565 | clock-names = "apb_pclk"; | |
566 | port { | |
567 | etm1_out_port: endpoint { | |
568 | remote-endpoint = <&funnel_in_port4>; | |
569 | }; | |
570 | }; | |
571 | }; | |
572 | ||
e6a7efad | 573 | etm@2203e000 { |
0bec8d82 MP |
574 | compatible = "arm,coresight-etm3x", "arm,primecell"; |
575 | reg = <0 0x2203e000 0 0x1000>; | |
576 | ||
577 | cpu = <&cpu4>; | |
578 | clocks = <&oscclk6a>; | |
579 | clock-names = "apb_pclk"; | |
580 | port { | |
581 | etm2_out_port: endpoint { | |
582 | remote-endpoint = <&funnel_in_port5>; | |
583 | }; | |
584 | }; | |
585 | }; | |
586 | ||
e6a7efad | 587 | smb@8000000 { |
433683a6 PM |
588 | compatible = "simple-bus"; |
589 | ||
590 | #address-cells = <2>; | |
591 | #size-cells = <1>; | |
375faa93 PM |
592 | ranges = <0 0 0 0x08000000 0x04000000>, |
593 | <1 0 0 0x14000000 0x04000000>, | |
594 | <2 0 0 0x18000000 0x04000000>, | |
595 | <3 0 0 0x1c000000 0x04000000>, | |
596 | <4 0 0 0x0c000000 0x04000000>, | |
597 | <5 0 0 0x10000000 0x04000000>; | |
598 | ||
433683a6 | 599 | #interrupt-cells = <1>; |
375faa93 PM |
600 | interrupt-map-mask = <0 0 63>; |
601 | interrupt-map = <0 0 0 &gic 0 0 4>, | |
602 | <0 0 1 &gic 0 1 4>, | |
603 | <0 0 2 &gic 0 2 4>, | |
604 | <0 0 3 &gic 0 3 4>, | |
605 | <0 0 4 &gic 0 4 4>, | |
606 | <0 0 5 &gic 0 5 4>, | |
607 | <0 0 6 &gic 0 6 4>, | |
608 | <0 0 7 &gic 0 7 4>, | |
609 | <0 0 8 &gic 0 8 4>, | |
610 | <0 0 9 &gic 0 9 4>, | |
611 | <0 0 10 &gic 0 10 4>, | |
612 | <0 0 11 &gic 0 11 4>, | |
613 | <0 0 12 &gic 0 12 4>, | |
614 | <0 0 13 &gic 0 13 4>, | |
615 | <0 0 14 &gic 0 14 4>, | |
616 | <0 0 15 &gic 0 15 4>, | |
617 | <0 0 16 &gic 0 16 4>, | |
618 | <0 0 17 &gic 0 17 4>, | |
619 | <0 0 18 &gic 0 18 4>, | |
620 | <0 0 19 &gic 0 19 4>, | |
621 | <0 0 20 &gic 0 20 4>, | |
622 | <0 0 21 &gic 0 21 4>, | |
623 | <0 0 22 &gic 0 22 4>, | |
624 | <0 0 23 &gic 0 23 4>, | |
625 | <0 0 24 &gic 0 24 4>, | |
626 | <0 0 25 &gic 0 25 4>, | |
627 | <0 0 26 &gic 0 26 4>, | |
628 | <0 0 27 &gic 0 27 4>, | |
629 | <0 0 28 &gic 0 28 4>, | |
630 | <0 0 29 &gic 0 29 4>, | |
631 | <0 0 30 &gic 0 30 4>, | |
632 | <0 0 31 &gic 0 31 4>, | |
633 | <0 0 32 &gic 0 32 4>, | |
634 | <0 0 33 &gic 0 33 4>, | |
635 | <0 0 34 &gic 0 34 4>, | |
636 | <0 0 35 &gic 0 35 4>, | |
637 | <0 0 36 &gic 0 36 4>, | |
638 | <0 0 37 &gic 0 37 4>, | |
639 | <0 0 38 &gic 0 38 4>, | |
640 | <0 0 39 &gic 0 39 4>, | |
641 | <0 0 40 &gic 0 40 4>, | |
642 | <0 0 41 &gic 0 41 4>, | |
643 | <0 0 42 &gic 0 42 4>; | |
433683a6 PM |
644 | |
645 | /include/ "vexpress-v2m-rs1.dtsi" | |
375faa93 | 646 | }; |
2b4e38fd BS |
647 | |
648 | site2: hsb@40000000 { | |
649 | compatible = "simple-bus"; | |
650 | #address-cells = <1>; | |
651 | #size-cells = <1>; | |
652 | ranges = <0 0 0x40000000 0x3fef0000>; | |
653 | #interrupt-cells = <1>; | |
654 | interrupt-map-mask = <0 3>; | |
655 | interrupt-map = <0 0 &gic 0 36 4>, | |
656 | <0 1 &gic 0 37 4>, | |
657 | <0 2 &gic 0 38 4>, | |
658 | <0 3 &gic 0 39 4>; | |
659 | }; | |
375faa93 | 660 | }; |