[linux-2.6-block.git] / arch / arm / boot / dts / vexpress-v2p-ca15_a7.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * CoreTile Express A15x2 A7x3
 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
 *
 * HBI-0249A
 */

/dts-v1/;
#include "vexpress-v2m-rs1.dtsi"

/ {
	model = "V2P-CA15_CA7";
	arm,hbi = <0x249>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			cci-control-port = <&cci_control1>;
			cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
			capacity-dmips-mhz = <1024>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			cci-control-port = <&cci_control1>;
			cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
			capacity-dmips-mhz = <1024>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x100>;
			cci-control-port = <&cci_control2>;
			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
			capacity-dmips-mhz = <516>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x101>;
			cci-control-port = <&cci_control2>;
			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
			capacity-dmips-mhz = <516>;
		};

		cpu4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x102>;
			cci-control-port = <&cci_control2>;
			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
			capacity-dmips-mhz = <516>;
		};

		idle-states {
			CLUSTER_SLEEP_BIG: cluster-sleep-big {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <700>;
				min-residency-us = <2000>;
			};

			CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <500>;
				min-residency-us = <2500>;
			};
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0 0x40000000>;
	};

	wdt@2a490000 {
		compatible = "arm,sp805", "arm,primecell";
		reg = <0 0x2a490000 0 0x1000>;
		interrupts = <0 98 4>;
		clocks = <&oscclk6a>, <&oscclk6a>;
		clock-names = "wdogclk", "apb_pclk";
	};

	hdlcd@2b000000 {
		compatible = "arm,hdlcd";
		reg = <0 0x2b000000 0 0x1000>;
		interrupts = <0 85 4>;
		clocks = <&hdlcd_clk>;
		clock-names = "pxlclk";
	};

	memory-controller@2b0a0000 {
		compatible = "arm,pl341", "arm,primecell";
		reg = <0 0x2b0a0000 0 0x1000>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x2c001000 0 0x1000>,
		      <0 0x2c002000 0 0x2000>,
		      <0 0x2c004000 0 0x2000>,
		      <0 0x2c006000 0 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	cci@2c090000 {
		compatible = "arm,cci-400";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0 0x2c090000 0 0x1000>;
		ranges = <0x0 0x0 0x2c090000 0x10000>;

		cci_control1: slave-if@4000 {
			compatible = "arm,cci-400-ctrl-if";
			interface-type = "ace";
			reg = <0x4000 0x1000>;
		};

		cci_control2: slave-if@5000 {
			compatible = "arm,cci-400-ctrl-if";
			interface-type = "ace";
			reg = <0x5000 0x1000>;
		};

		pmu@9000 {
			 compatible = "arm,cci-400-pmu,r0";
			 reg = <0x9000 0x5000>;
			 interrupts = <0 105 4>,
				      <0 101 4>,
				      <0 102 4>,
				      <0 103 4>,
				      <0 104 4>;
		};
	};

	memory-controller@7ffd0000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0 0x7ffd0000 0 0x1000>;
		interrupts = <0 86 4>,
			     <0 87 4>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
	};

	dma@7ff00000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0 0x7ff00000 0 0x1000>;
		interrupts = <0 92 4>,
			     <0 88 4>,
			     <0 89 4>,
			     <0 90 4>,
			     <0 91 4>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
	};

        scc@7fff0000 {
		compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
		reg = <0 0x7fff0000 0 0x1000>;
		interrupts = <0 95 4>;
        };

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
	};

	pmu-a15 {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <0 68 4>,
			     <0 69 4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>;
	};

	pmu-a7 {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <0 128 4>,
			     <0 129 4>,
			     <0 130 4>;
		interrupt-affinity = <&cpu2>,
				     <&cpu3>,
				     <&cpu4>;
	};

	oscclk6a: oscclk6a {
		/* Reference 24MHz clock */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "oscclk6a";
	};

	dcc {
		compatible = "arm,vexpress,config-bus";
		arm,vexpress,config-bridge = <&v2m_sysreg>;

		oscclk0 {
			/* A15 PLL 0 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 0>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk0";
		};

		oscclk1 {
			/* A15 PLL 1 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 1>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk1";
		};

		oscclk2 {
			/* A7 PLL 0 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 2>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk2";
		};

		oscclk3 {
			/* A7 PLL 1 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 3>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk3";
		};

		oscclk4 {
			/* External AXI master clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 4>;
			freq-range = <20000000 40000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk4";
		};

		hdlcd_clk: oscclk5 {
			/* HDLCD PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 5>;
			freq-range = <23750000 165000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk5";
		};

		smbclk: oscclk6 {
			/* Static memory controller clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 6>;
			freq-range = <20000000 40000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk6";
		};

		oscclk7 {
			/* SYS PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 7>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk7";
		};

		oscclk8 {
			/* DDR2 PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 8>;
			freq-range = <20000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk8";
		};

		volt-a15 {
			/* A15 CPU core voltage */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 0>;
			regulator-name = "A15 Vcore";
			regulator-min-microvolt = <800000>;
			regulator-max-microvolt = <1050000>;
			regulator-always-on;
			label = "A15 Vcore";
		};

		volt-a7 {
			/* A7 CPU core voltage */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 1>;
			regulator-name = "A7 Vcore";
			regulator-min-microvolt = <800000>;
			regulator-max-microvolt = <1050000>;
			regulator-always-on;
			label = "A7 Vcore";
		};

		amp-a15 {
			/* Total current for the two A15 cores */
			compatible = "arm,vexpress-amp";
			arm,vexpress-sysreg,func = <3 0>;
			label = "A15 Icore";
		};

		amp-a7 {
			/* Total current for the three A7 cores */
			compatible = "arm,vexpress-amp";
			arm,vexpress-sysreg,func = <3 1>;
			label = "A7 Icore";
		};

		temp-dcc {
			/* DCC internal temperature */
			compatible = "arm,vexpress-temp";
			arm,vexpress-sysreg,func = <4 0>;
			label = "DCC";
		};

		power-a15 {
			/* Total power for the two A15 cores */
			compatible = "arm,vexpress-power";
			arm,vexpress-sysreg,func = <12 0>;
			label = "A15 Pcore";
		};

		power-a7 {
			/* Total power for the three A7 cores */
			compatible = "arm,vexpress-power";
			arm,vexpress-sysreg,func = <12 1>;
			label = "A7 Pcore";
		};

		energy-a15 {
			/* Total energy for the two A15 cores */
			compatible = "arm,vexpress-energy";
			arm,vexpress-sysreg,func = <13 0>, <13 1>;
			label = "A15 Jcore";
		};

		energy-a7 {
			/* Total energy for the three A7 cores */
			compatible = "arm,vexpress-energy";
			arm,vexpress-sysreg,func = <13 2>, <13 3>;
			label = "A7 Jcore";
		};
	};

	etb@20010000 {
		compatible = "arm,coresight-etb10", "arm,primecell";
		reg = <0 0x20010000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			etb_in_port: endpoint {
				slave-mode;
				remote-endpoint = <&replicator_out_port0>;
			};
		};
	};

	tpiu@20030000 {
		compatible = "arm,coresight-tpiu", "arm,primecell";
		reg = <0 0x20030000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			tpiu_in_port: endpoint {
				slave-mode;
				remote-endpoint = <&replicator_out_port1>;
			};
		};
	};

	replicator {
		/* non-configurable replicators don't show up on the
		 * AMBA bus.  As such no need to add "arm,primecell".
		 */
		compatible = "arm,coresight-replicator";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* replicator output ports */
			port@0 {
				reg = <0>;
				replicator_out_port0: endpoint {
					remote-endpoint = <&etb_in_port>;
				};
			};

			port@1 {
				reg = <1>;
				replicator_out_port1: endpoint {
					remote-endpoint = <&tpiu_in_port>;
				};
			};

			/* replicator input port */
			port@2 {
				reg = <0>;
				replicator_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&funnel_out_port0>;
				};
			};
		};
	};

	funnel@20040000 {
		compatible = "arm,coresight-funnel", "arm,primecell";
		reg = <0 0x20040000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* funnel output port */
			port@0 {
				reg = <0>;
				funnel_out_port0: endpoint {
					remote-endpoint =
						<&replicator_in_port0>;
				};
			};

			/* funnel input ports */
			port@1 {
				reg = <0>;
				funnel_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&ptm0_out_port>;
				};
			};

			port@2 {
				reg = <1>;
				funnel_in_port1: endpoint {
					slave-mode;
					remote-endpoint = <&ptm1_out_port>;
				};
			};

			port@3 {
				reg = <2>;
				funnel_in_port2: endpoint {
					slave-mode;
					remote-endpoint = <&etm0_out_port>;
				};
			};

			/* Input port #3 is for ITM, not supported here */

			port@4 {
				reg = <4>;
				funnel_in_port4: endpoint {
					slave-mode;
					remote-endpoint = <&etm1_out_port>;
				};
			};

			port@5 {
				reg = <5>;
				funnel_in_port5: endpoint {
					slave-mode;
					remote-endpoint = <&etm2_out_port>;
				};
			};
		};
	};

	ptm@2201c000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2201c000 0 0x1000>;

		cpu = <&cpu0>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			ptm0_out_port: endpoint {
				remote-endpoint = <&funnel_in_port0>;
			};
		};
	};

	ptm@2201d000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2201d000 0 0x1000>;

		cpu = <&cpu1>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			ptm1_out_port: endpoint {
				remote-endpoint = <&funnel_in_port1>;
			};
		};
	};

	etm@2203c000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2203c000 0 0x1000>;

		cpu = <&cpu2>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			etm0_out_port: endpoint {
				remote-endpoint = <&funnel_in_port2>;
			};
		};
	};

	etm@2203d000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2203d000 0 0x1000>;

		cpu = <&cpu3>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			etm1_out_port: endpoint {
				remote-endpoint = <&funnel_in_port4>;
			};
		};
	};

	etm@2203e000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2203e000 0 0x1000>;

		cpu = <&cpu4>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {
			etm2_out_port: endpoint {
				remote-endpoint = <&funnel_in_port5>;
			};
		};
	};

	smb: smb@8000000 {
		compatible = "simple-bus";

		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0 0x08000000 0x04000000>,
			 <1 0 0 0x14000000 0x04000000>,
			 <2 0 0 0x18000000 0x04000000>,
			 <3 0 0 0x1c000000 0x04000000>,
			 <4 0 0 0x0c000000 0x04000000>,
			 <5 0 0 0x10000000 0x04000000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic 0  0 4>,
				<0 0  1 &gic 0  1 4>,
				<0 0  2 &gic 0  2 4>,
				<0 0  3 &gic 0  3 4>,
				<0 0  4 &gic 0  4 4>,
				<0 0  5 &gic 0  5 4>,
				<0 0  6 &gic 0  6 4>,
				<0 0  7 &gic 0  7 4>,
				<0 0  8 &gic 0  8 4>,
				<0 0  9 &gic 0  9 4>,
				<0 0 10 &gic 0 10 4>,
				<0 0 11 &gic 0 11 4>,
				<0 0 12 &gic 0 12 4>,
				<0 0 13 &gic 0 13 4>,
				<0 0 14 &gic 0 14 4>,
				<0 0 15 &gic 0 15 4>,
				<0 0 16 &gic 0 16 4>,
				<0 0 17 &gic 0 17 4>,
				<0 0 18 &gic 0 18 4>,
				<0 0 19 &gic 0 19 4>,
				<0 0 20 &gic 0 20 4>,
				<0 0 21 &gic 0 21 4>,
				<0 0 22 &gic 0 22 4>,
				<0 0 23 &gic 0 23 4>,
				<0 0 24 &gic 0 24 4>,
				<0 0 25 &gic 0 25 4>,
				<0 0 26 &gic 0 26 4>,
				<0 0 27 &gic 0 27 4>,
				<0 0 28 &gic 0 28 4>,
				<0 0 29 &gic 0 29 4>,
				<0 0 30 &gic 0 30 4>,
				<0 0 31 &gic 0 31 4>,
				<0 0 32 &gic 0 32 4>,
				<0 0 33 &gic 0 33 4>,
				<0 0 34 &gic 0 34 4>,
				<0 0 35 &gic 0 35 4>,
				<0 0 36 &gic 0 36 4>,
				<0 0 37 &gic 0 37 4>,
				<0 0 38 &gic 0 38 4>,
				<0 0 39 &gic 0 39 4>,
				<0 0 40 &gic 0 40 4>,
				<0 0 41 &gic 0 41 4>,
				<0 0 42 &gic 0 42 4>;
	};

	site2: hsb@40000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x40000000 0x3fef0000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 3>;
		interrupt-map = <0 0 &gic 0 36 4>,
				<0 1 &gic 0 37 4>,
				<0 2 &gic 0 38 4>,
				<0 3 &gic 0 39 4>;
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
375faa93 PM	2	/*
	3	* ARM Ltd. Versatile Express
	4	*
	5	* CoreTile Express A15x2 A7x3
	6	* Cortex-A15_A7 MPCore (V2P-CA15_A7)
	7	*
	8	* HBI-0249A
	9	*/
	10
	11	/dts-v1/;
bd7aff03	12	#include "vexpress-v2m-rs1.dtsi"
375faa93 PM	13
	14	/ {
	15	model = "V2P-CA15_CA7";
	16	arm,hbi = <0x249>;
842839a3	17	arm,vexpress,site = <0xf>;
375faa93 PM	18	compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
	19	interrupt-parent = <&gic>;
	20	#address-cells = <2>;
	21	#size-cells = <2>;
	22
	23	chosen { };
	24
	25	aliases {
	26	serial0 = &v2m_serial0;
	27	serial1 = &v2m_serial1;
	28	serial2 = &v2m_serial2;
	29	serial3 = &v2m_serial3;
	30	i2c0 = &v2m_i2c_dvi;
	31	i2c1 = &v2m_i2c_pcie;
	32	};
	33
	34	cpus {
	35	#address-cells = <1>;
	36	#size-cells = <0>;
	37
	38	cpu0: cpu@0 {
	39	device_type = "cpu";
	40	compatible = "arm,cortex-a15";
	41	reg = <0>;
a2bdc32a	42	cci-control-port = <&cci_control1>;
d2e5c871	43	cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
b01c3994	44	capacity-dmips-mhz = <1024>;
375faa93 PM	45	};
	46
	47	cpu1: cpu@1 {
	48	device_type = "cpu";
	49	compatible = "arm,cortex-a15";
	50	reg = <1>;
a2bdc32a	51	cci-control-port = <&cci_control1>;
d2e5c871	52	cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
b01c3994	53	capacity-dmips-mhz = <1024>;
375faa93 PM	54	};
375faa93 PM	55
375faa93 PM	56	cpu2: cpu@2 {
	57	device_type = "cpu";
	58	compatible = "arm,cortex-a7";
	59	reg = <0x100>;
a2bdc32a	60	cci-control-port = <&cci_control2>;
d2e5c871	61	cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
b01c3994	62	capacity-dmips-mhz = <516>;
375faa93 PM	63	};
	64
	65	cpu3: cpu@3 {
	66	device_type = "cpu";
	67	compatible = "arm,cortex-a7";
	68	reg = <0x101>;
a2bdc32a	69	cci-control-port = <&cci_control2>;
d2e5c871	70	cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
b01c3994	71	capacity-dmips-mhz = <516>;
375faa93 PM	72	};
	73
	74	cpu4: cpu@4 {
	75	device_type = "cpu";
	76	compatible = "arm,cortex-a7";
	77	reg = <0x102>;
a2bdc32a	78	cci-control-port = <&cci_control2>;
d2e5c871	79	cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
b01c3994	80	capacity-dmips-mhz = <516>;
d2e5c871 LP	81	};
	82
	83	idle-states {
	84	CLUSTER_SLEEP_BIG: cluster-sleep-big {
	85	compatible = "arm,idle-state";
	86	local-timer-stop;
	87	entry-latency-us = <1000>;
	88	exit-latency-us = <700>;
	89	min-residency-us = <2000>;
	90	};
	91
	92	CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
	93	compatible = "arm,idle-state";
	94	local-timer-stop;
	95	entry-latency-us = <1000>;
	96	exit-latency-us = <500>;
	97	min-residency-us = <2500>;
	98	};
375faa93	99	};
375faa93 PM	100	};
	101
	102	memory@80000000 {
	103	device_type = "memory";
	104	reg = <0 0x80000000 0 0x40000000>;
	105	};
	106
	107	wdt@2a490000 {
	108	compatible = "arm,sp805", "arm,primecell";
	109	reg = <0 0x2a490000 0 0x1000>;
aab7da70	110	interrupts = <0 98 4>;
842839a3 PM	111	clocks = <&oscclk6a>, <&oscclk6a>;
842839a3 PM	112	clock-names = "wdogclk", "apb_pclk";
375faa93 PM	113	};
	114
	115	hdlcd@2b000000 {
	116	compatible = "arm,hdlcd";
	117	reg = <0 0x2b000000 0 0x1000>;
	118	interrupts = <0 85 4>;
2cff6dba	119	clocks = <&hdlcd_clk>;
842839a3	120	clock-names = "pxlclk";
375faa93 PM	121	};
	122
	123	memory-controller@2b0a0000 {
	124	compatible = "arm,pl341", "arm,primecell";
	125	reg = <0 0x2b0a0000 0 0x1000>;
842839a3 PM	126	clocks = <&oscclk6a>;
842839a3 PM	127	clock-names = "apb_pclk";
375faa93 PM	128	};
	129
	130	gic: interrupt-controller@2c001000 {
	131	compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
	132	#interrupt-cells = <3>;
	133	#address-cells = <0>;
	134	interrupt-controller;
	135	reg = <0 0x2c001000 0 0x1000>,
368400e2	136	<0 0x2c002000 0 0x2000>,
375faa93 PM	137	<0 0x2c004000 0 0x2000>,
	138	<0 0x2c006000 0 0x2000>;
	139	interrupts = <1 9 0xf04>;
	140	};
	141
a2bdc32a JMT	142	cci@2c090000 {
	143	compatible = "arm,cci-400";
	144	#address-cells = <1>;
	145	#size-cells = <1>;
	146	reg = <0 0x2c090000 0 0x1000>;
	147	ranges = <0x0 0x0 0x2c090000 0x10000>;
	148
	149	cci_control1: slave-if@4000 {
	150	compatible = "arm,cci-400-ctrl-if";
	151	interface-type = "ace";
	152	reg = <0x4000 0x1000>;
	153	};
	154
	155	cci_control2: slave-if@5000 {
	156	compatible = "arm,cci-400-ctrl-if";
	157	interface-type = "ace";
	158	reg = <0x5000 0x1000>;
	159	};
3adf7aaa SH	160
	161	pmu@9000 {
	162	compatible = "arm,cci-400-pmu,r0";
	163	reg = <0x9000 0x5000>;
	164	interrupts = <0 105 4>,
	165	<0 101 4>,
	166	<0 102 4>,
	167	<0 103 4>,
	168	<0 104 4>;
	169	};
a2bdc32a JMT	170	};
a2bdc32a JMT	171
375faa93 PM	172	memory-controller@7ffd0000 {
	173	compatible = "arm,pl354", "arm,primecell";
	174	reg = <0 0x7ffd0000 0 0x1000>;
	175	interrupts = <0 86 4>,
	176	<0 87 4>;
842839a3 PM	177	clocks = <&oscclk6a>;
842839a3 PM	178	clock-names = "apb_pclk";
375faa93 PM	179	};
	180
	181	dma@7ff00000 {
	182	compatible = "arm,pl330", "arm,primecell";
	183	reg = <0 0x7ff00000 0 0x1000>;
	184	interrupts = <0 92 4>,
	185	<0 88 4>,
	186	<0 89 4>,
	187	<0 90 4>,
	188	<0 91 4>;
842839a3 PM	189	clocks = <&oscclk6a>;
842839a3 PM	190	clock-names = "apb_pclk";
375faa93 PM	191	};
375faa93 PM	192
ceca0e1c PM	193	scc@7fff0000 {
	194	compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
	195	reg = <0 0x7fff0000 0 0x1000>;
	196	interrupts = <0 95 4>;
	197	};
	198
375faa93 PM	199	timer {
	200	compatible = "arm,armv7-timer";
	201	interrupts = <1 13 0xf08>,
	202	<1 14 0xf08>,
	203	<1 11 0xf08>,
	204	<1 10 0xf08>;
	205	};
	206
b67b00ee	207	pmu-a15 {
7e16063b	208	compatible = "arm,cortex-a15-pmu";
375faa93 PM	209	interrupts = <0 68 4>,
375faa93 PM	210	<0 69 4>;
4d44f2a0 MR	211	interrupt-affinity = <&cpu0>,
	212	<&cpu1>;
	213	};
	214
b67b00ee	215	pmu-a7 {
4d44f2a0 MR	216	compatible = "arm,cortex-a7-pmu";
	217	interrupts = <0 128 4>,
	218	<0 129 4>,
	219	<0 130 4>;
	220	interrupt-affinity = <&cpu2>,
	221	<&cpu3>,
	222	<&cpu4>;
375faa93 PM	223	};
375faa93 PM	224
842839a3 PM	225	oscclk6a: oscclk6a {
	226	/* Reference 24MHz clock */
	227	compatible = "fixed-clock";
	228	#clock-cells = <0>;
	229	clock-frequency = <24000000>;
	230	clock-output-names = "oscclk6a";
	231	};
	232
	233	dcc {
	234	compatible = "arm,vexpress,config-bus";
	235	arm,vexpress,config-bridge = <&v2m_sysreg>;
	236
2cff6dba	237	oscclk0 {
842839a3 PM	238	/* A15 PLL 0 reference clock */
	239	compatible = "arm,vexpress-osc";
	240	arm,vexpress-sysreg,func = <1 0>;
	241	freq-range = <17000000 50000000>;
	242	#clock-cells = <0>;
	243	clock-output-names = "oscclk0";
	244	};
	245
2cff6dba	246	oscclk1 {
842839a3 PM	247	/* A15 PLL 1 reference clock */
	248	compatible = "arm,vexpress-osc";
	249	arm,vexpress-sysreg,func = <1 1>;
	250	freq-range = <17000000 50000000>;
	251	#clock-cells = <0>;
	252	clock-output-names = "oscclk1";
	253	};
	254
2cff6dba	255	oscclk2 {
842839a3 PM	256	/* A7 PLL 0 reference clock */
	257	compatible = "arm,vexpress-osc";
	258	arm,vexpress-sysreg,func = <1 2>;
	259	freq-range = <17000000 50000000>;
	260	#clock-cells = <0>;
	261	clock-output-names = "oscclk2";
	262	};
	263
2cff6dba	264	oscclk3 {
842839a3 PM	265	/* A7 PLL 1 reference clock */
	266	compatible = "arm,vexpress-osc";
	267	arm,vexpress-sysreg,func = <1 3>;
	268	freq-range = <17000000 50000000>;
	269	#clock-cells = <0>;
	270	clock-output-names = "oscclk3";
	271	};
	272
2cff6dba	273	oscclk4 {
842839a3 PM	274	/* External AXI master clock */
	275	compatible = "arm,vexpress-osc";
	276	arm,vexpress-sysreg,func = <1 4>;
	277	freq-range = <20000000 40000000>;
	278	#clock-cells = <0>;
	279	clock-output-names = "oscclk4";
	280	};
	281
2cff6dba	282	hdlcd_clk: oscclk5 {
842839a3 PM	283	/* HDLCD PLL reference clock */
	284	compatible = "arm,vexpress-osc";
	285	arm,vexpress-sysreg,func = <1 5>;
	286	freq-range = <23750000 165000000>;
	287	#clock-cells = <0>;
	288	clock-output-names = "oscclk5";
	289	};
	290
2cff6dba	291	smbclk: oscclk6 {
842839a3 PM	292	/* Static memory controller clock */
	293	compatible = "arm,vexpress-osc";
	294	arm,vexpress-sysreg,func = <1 6>;
	295	freq-range = <20000000 40000000>;
	296	#clock-cells = <0>;
	297	clock-output-names = "oscclk6";
	298	};
	299
2cff6dba	300	oscclk7 {
842839a3 PM	301	/* SYS PLL reference clock */
	302	compatible = "arm,vexpress-osc";
	303	arm,vexpress-sysreg,func = <1 7>;
	304	freq-range = <17000000 50000000>;
	305	#clock-cells = <0>;
	306	clock-output-names = "oscclk7";
	307	};
	308
2cff6dba	309	oscclk8 {
842839a3 PM	310	/* DDR2 PLL reference clock */
	311	compatible = "arm,vexpress-osc";
	312	arm,vexpress-sysreg,func = <1 8>;
	313	freq-range = <20000000 50000000>;
	314	#clock-cells = <0>;
	315	clock-output-names = "oscclk8";
	316	};
	317
2cff6dba	318	volt-a15 {
842839a3 PM	319	/* A15 CPU core voltage */
	320	compatible = "arm,vexpress-volt";
	321	arm,vexpress-sysreg,func = <2 0>;
	322	regulator-name = "A15 Vcore";
	323	regulator-min-microvolt = <800000>;
	324	regulator-max-microvolt = <1050000>;
	325	regulator-always-on;
	326	label = "A15 Vcore";
	327	};
	328
2cff6dba	329	volt-a7 {
842839a3 PM	330	/* A7 CPU core voltage */
	331	compatible = "arm,vexpress-volt";
	332	arm,vexpress-sysreg,func = <2 1>;
	333	regulator-name = "A7 Vcore";
	334	regulator-min-microvolt = <800000>;
	335	regulator-max-microvolt = <1050000>;
	336	regulator-always-on;
	337	label = "A7 Vcore";
	338	};
	339
2cff6dba	340	amp-a15 {
842839a3 PM	341	/* Total current for the two A15 cores */
	342	compatible = "arm,vexpress-amp";
	343	arm,vexpress-sysreg,func = <3 0>;
	344	label = "A15 Icore";
	345	};
	346
2cff6dba	347	amp-a7 {
842839a3 PM	348	/* Total current for the three A7 cores */
	349	compatible = "arm,vexpress-amp";
	350	arm,vexpress-sysreg,func = <3 1>;
	351	label = "A7 Icore";
	352	};
	353
2cff6dba	354	temp-dcc {
842839a3 PM	355	/* DCC internal temperature */
	356	compatible = "arm,vexpress-temp";
	357	arm,vexpress-sysreg,func = <4 0>;
	358	label = "DCC";
	359	};
	360
2cff6dba	361	power-a15 {
842839a3 PM	362	/* Total power for the two A15 cores */
	363	compatible = "arm,vexpress-power";
	364	arm,vexpress-sysreg,func = <12 0>;
	365	label = "A15 Pcore";
	366	};
3b9334ac	367
2cff6dba	368	power-a7 {
842839a3 PM	369	/* Total power for the three A7 cores */
	370	compatible = "arm,vexpress-power";
	371	arm,vexpress-sysreg,func = <12 1>;
	372	label = "A7 Pcore";
	373	};
	374
2cff6dba	375	energy-a15 {
842839a3 PM	376	/* Total energy for the two A15 cores */
842839a3 PM	377	compatible = "arm,vexpress-energy";
3b9334ac	378	arm,vexpress-sysreg,func = <13 0>, <13 1>;
842839a3 PM	379	label = "A15 Jcore";
	380	};
	381
2cff6dba	382	energy-a7 {
842839a3 PM	383	/* Total energy for the three A7 cores */
842839a3 PM	384	compatible = "arm,vexpress-energy";
3b9334ac	385	arm,vexpress-sysreg,func = <13 2>, <13 3>;
842839a3 PM	386	label = "A7 Jcore";
	387	};
	388	};
	389
e6a7efad	390	etb@20010000 {
0bec8d82 MP	391	compatible = "arm,coresight-etb10", "arm,primecell";
	392	reg = <0 0x20010000 0 0x1000>;
	393
0bec8d82 MP	394	clocks = <&oscclk6a>;
	395	clock-names = "apb_pclk";
	396	port {
2cff6dba	397	etb_in_port: endpoint {
0bec8d82 MP	398	slave-mode;
	399	remote-endpoint = <&replicator_out_port0>;
	400	};
	401	};
	402	};
	403
e6a7efad	404	tpiu@20030000 {
0bec8d82 MP	405	compatible = "arm,coresight-tpiu", "arm,primecell";
	406	reg = <0 0x20030000 0 0x1000>;
	407
	408	clocks = <&oscclk6a>;
	409	clock-names = "apb_pclk";
	410	port {
2cff6dba	411	tpiu_in_port: endpoint {
0bec8d82 MP	412	slave-mode;
	413	remote-endpoint = <&replicator_out_port1>;
	414	};
	415	};
	416	};
	417
	418	replicator {
	419	/* non-configurable replicators don't show up on the
	420	* AMBA bus. As such no need to add "arm,primecell".
	421	*/
	422	compatible = "arm,coresight-replicator";
	423
	424	ports {
	425	#address-cells = <1>;
	426	#size-cells = <0>;
	427
	428	/* replicator output ports */
	429	port@0 {
	430	reg = <0>;
	431	replicator_out_port0: endpoint {
	432	remote-endpoint = <&etb_in_port>;
	433	};
	434	};
	435
	436	port@1 {
	437	reg = <1>;
	438	replicator_out_port1: endpoint {
	439	remote-endpoint = <&tpiu_in_port>;
	440	};
	441	};
	442
	443	/* replicator input port */
	444	port@2 {
	445	reg = <0>;
	446	replicator_in_port0: endpoint {
	447	slave-mode;
	448	remote-endpoint = <&funnel_out_port0>;
	449	};
	450	};
	451	};
	452	};
	453
e6a7efad	454	funnel@20040000 {
0bec8d82 MP	455	compatible = "arm,coresight-funnel", "arm,primecell";
	456	reg = <0 0x20040000 0 0x1000>;
	457
	458	clocks = <&oscclk6a>;
	459	clock-names = "apb_pclk";
	460	ports {
	461	#address-cells = <1>;
	462	#size-cells = <0>;
	463
	464	/* funnel output port */
	465	port@0 {
	466	reg = <0>;
	467	funnel_out_port0: endpoint {
	468	remote-endpoint =
	469	<&replicator_in_port0>;
	470	};
	471	};
	472
	473	/* funnel input ports */
	474	port@1 {
	475	reg = <0>;
	476	funnel_in_port0: endpoint {
	477	slave-mode;
	478	remote-endpoint = <&ptm0_out_port>;
	479	};
	480	};
	481
	482	port@2 {
	483	reg = <1>;
	484	funnel_in_port1: endpoint {
	485	slave-mode;
	486	remote-endpoint = <&ptm1_out_port>;
	487	};
	488	};
	489
	490	port@3 {
	491	reg = <2>;
	492	funnel_in_port2: endpoint {
	493	slave-mode;
	494	remote-endpoint = <&etm0_out_port>;
	495	};
	496	};
	497
	498	/* Input port #3 is for ITM, not supported here */
	499
	500	port@4 {
	501	reg = <4>;
	502	funnel_in_port4: endpoint {
	503	slave-mode;
	504	remote-endpoint = <&etm1_out_port>;
	505	};
	506	};
	507
	508	port@5 {
	509	reg = <5>;
	510	funnel_in_port5: endpoint {
	511	slave-mode;
	512	remote-endpoint = <&etm2_out_port>;
	513	};
	514	};
	515	};
	516	};
	517
e6a7efad	518	ptm@2201c000 {
0bec8d82 MP	519	compatible = "arm,coresight-etm3x", "arm,primecell";
	520	reg = <0 0x2201c000 0 0x1000>;
	521
	522	cpu = <&cpu0>;
	523	clocks = <&oscclk6a>;
	524	clock-names = "apb_pclk";
	525	port {
	526	ptm0_out_port: endpoint {
	527	remote-endpoint = <&funnel_in_port0>;
	528	};
	529	};
	530	};
	531
e6a7efad	532	ptm@2201d000 {
0bec8d82 MP	533	compatible = "arm,coresight-etm3x", "arm,primecell";
	534	reg = <0 0x2201d000 0 0x1000>;
	535
	536	cpu = <&cpu1>;
	537	clocks = <&oscclk6a>;
	538	clock-names = "apb_pclk";
	539	port {
	540	ptm1_out_port: endpoint {
	541	remote-endpoint = <&funnel_in_port1>;
	542	};
	543	};
	544	};
	545
e6a7efad	546	etm@2203c000 {
0bec8d82 MP	547	compatible = "arm,coresight-etm3x", "arm,primecell";
	548	reg = <0 0x2203c000 0 0x1000>;
	549
	550	cpu = <&cpu2>;
	551	clocks = <&oscclk6a>;
	552	clock-names = "apb_pclk";
	553	port {
	554	etm0_out_port: endpoint {
	555	remote-endpoint = <&funnel_in_port2>;
	556	};
	557	};
	558	};
	559
e6a7efad	560	etm@2203d000 {
0bec8d82 MP	561	compatible = "arm,coresight-etm3x", "arm,primecell";
	562	reg = <0 0x2203d000 0 0x1000>;
	563
	564	cpu = <&cpu3>;
	565	clocks = <&oscclk6a>;
	566	clock-names = "apb_pclk";
	567	port {
	568	etm1_out_port: endpoint {
	569	remote-endpoint = <&funnel_in_port4>;
	570	};
	571	};
	572	};
	573
e6a7efad	574	etm@2203e000 {
0bec8d82 MP	575	compatible = "arm,coresight-etm3x", "arm,primecell";
	576	reg = <0 0x2203e000 0 0x1000>;
	577
	578	cpu = <&cpu4>;
	579	clocks = <&oscclk6a>;
	580	clock-names = "apb_pclk";
	581	port {
	582	etm2_out_port: endpoint {
	583	remote-endpoint = <&funnel_in_port5>;
	584	};
	585	};
	586	};
	587
bd7aff03	588	smb: smb@8000000 {
433683a6 PM	589	compatible = "simple-bus";
	590
	591	#address-cells = <2>;
	592	#size-cells = <1>;
375faa93 PM	593	ranges = <0 0 0 0x08000000 0x04000000>,
	594	<1 0 0 0x14000000 0x04000000>,
	595	<2 0 0 0x18000000 0x04000000>,
	596	<3 0 0 0x1c000000 0x04000000>,
	597	<4 0 0 0x0c000000 0x04000000>,
	598	<5 0 0 0x10000000 0x04000000>;
	599
433683a6	600	#interrupt-cells = <1>;
375faa93 PM	601	interrupt-map-mask = <0 0 63>;
	602	interrupt-map = <0 0 0 &gic 0 0 4>,
	603	<0 0 1 &gic 0 1 4>,
	604	<0 0 2 &gic 0 2 4>,
	605	<0 0 3 &gic 0 3 4>,
	606	<0 0 4 &gic 0 4 4>,
	607	<0 0 5 &gic 0 5 4>,
	608	<0 0 6 &gic 0 6 4>,
	609	<0 0 7 &gic 0 7 4>,
	610	<0 0 8 &gic 0 8 4>,
	611	<0 0 9 &gic 0 9 4>,
	612	<0 0 10 &gic 0 10 4>,
	613	<0 0 11 &gic 0 11 4>,
	614	<0 0 12 &gic 0 12 4>,
	615	<0 0 13 &gic 0 13 4>,
	616	<0 0 14 &gic 0 14 4>,
	617	<0 0 15 &gic 0 15 4>,
	618	<0 0 16 &gic 0 16 4>,
	619	<0 0 17 &gic 0 17 4>,
	620	<0 0 18 &gic 0 18 4>,
	621	<0 0 19 &gic 0 19 4>,
	622	<0 0 20 &gic 0 20 4>,
	623	<0 0 21 &gic 0 21 4>,
	624	<0 0 22 &gic 0 22 4>,
	625	<0 0 23 &gic 0 23 4>,
	626	<0 0 24 &gic 0 24 4>,
	627	<0 0 25 &gic 0 25 4>,
	628	<0 0 26 &gic 0 26 4>,
	629	<0 0 27 &gic 0 27 4>,
	630	<0 0 28 &gic 0 28 4>,
	631	<0 0 29 &gic 0 29 4>,
	632	<0 0 30 &gic 0 30 4>,
	633	<0 0 31 &gic 0 31 4>,
	634	<0 0 32 &gic 0 32 4>,
	635	<0 0 33 &gic 0 33 4>,
	636	<0 0 34 &gic 0 34 4>,
	637	<0 0 35 &gic 0 35 4>,
	638	<0 0 36 &gic 0 36 4>,
	639	<0 0 37 &gic 0 37 4>,
	640	<0 0 38 &gic 0 38 4>,
	641	<0 0 39 &gic 0 39 4>,
	642	<0 0 40 &gic 0 40 4>,
	643	<0 0 41 &gic 0 41 4>,
	644	<0 0 42 &gic 0 42 4>;
	645	};
2b4e38fd BS	646
	647	site2: hsb@40000000 {
	648	compatible = "simple-bus";
	649	#address-cells = <1>;
	650	#size-cells = <1>;
	651	ranges = <0 0 0x40000000 0x3fef0000>;
	652	#interrupt-cells = <1>;
	653	interrupt-map-mask = <0 3>;
	654	interrupt-map = <0 0 &gic 0 36 4>,
	655	<0 1 &gic 0 37 4>,
	656	<0 2 &gic 0 38 4>,
	657	<0 3 &gic 0 39 4>;
	658	};
375faa93	659	};