projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 8e678e06 | 1 | /* |
| 77896e4d | 2 | * Device Tree Source for UniPhier sLD8 SoC |
| 8e678e06 | 3 | * |
| 77896e4d MY |
4 | * Copyright (C) 2015-2016 Socionext Inc. |
| 5 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
| 8e678e06 | 6 | * |
| fa53757b | 7 | * SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 8e678e06 MY |
8 | */ |
| 9 | ||
| 8e678e06 | 10 | / { |
| 77896e4d | 11 | compatible = "socionext,uniphier-sld8"; |
| 8e2b908b MY |
12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; | |
| 8e678e06 MY |
14 | |
| 15 | cpus { | |
| 16 | #address-cells = <1>; | |
| 17 | #size-cells = <0>; | |
| 18 | ||
| 19 | cpu@0 { | |
| 20 | device_type = "cpu"; | |
| 21 | compatible = "arm,cortex-a9"; | |
| 22 | reg = <0>; | |
| 3bdba5ac | 23 | enable-method = "psci"; |
| 7c62f299 | 24 | next-level-cache = <&l2>; |
| 8e678e06 MY |
25 | }; |
| 26 | }; | |
| 27 | ||
| 2752bcaa MY |
28 | psci { |
| 29 | compatible = "arm,psci-0.2"; | |
| 30 | method = "smc"; | |
| 31 | }; | |
| 32 | ||
| 8e678e06 | 33 | clocks { |
| 2752bcaa MY |
34 | refclk: ref { |
| 35 | compatible = "fixed-clock"; | |
| 36 | #clock-cells = <0>; | |
| 37 | clock-frequency = <25000000>; | |
| 38 | }; | |
| 39 | ||
| 8e678e06 MY |
40 | arm_timer_clk: arm_timer_clk { |
| 41 | #clock-cells = <0>; | |
| 42 | compatible = "fixed-clock"; | |
| 43 | clock-frequency = <50000000>; | |
| 44 | }; | |
| 45 | }; | |
| 8e678e06 | 46 | |
| 2752bcaa MY |
47 | soc { |
| 48 | compatible = "simple-bus"; | |
| 629b557a | 49 | #address-cells = <1>; |
| 2752bcaa MY |
50 | #size-cells = <1>; |
| 51 | ranges; | |
| 52 | interrupt-parent = <&intc>; | |
| 3fbf02a8 | 53 | |
| 2752bcaa MY |
54 | l2: l2-cache@500c0000 { |
| 55 | compatible = "socionext,uniphier-system-cache"; | |
| 56 | reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, | |
| 57 | <0x506c0000 0x400>; | |
| 58 | interrupts = <0 174 4>, <0 175 4>; | |
| 59 | cache-unified; | |
| 60 | cache-size = <(256 * 1024)>; | |
| 61 | cache-sets = <256>; | |
| 62 | cache-line-size = <128>; | |
| 63 | cache-level = <2>; | |
| 64 | }; | |
| 3fbf02a8 | 65 | |
| 2752bcaa MY |
66 | serial0: serial@54006800 { |
| 67 | compatible = "socionext,uniphier-uart"; | |
| 68 | status = "disabled"; | |
| 69 | reg = <0x54006800 0x40>; | |
| 70 | interrupts = <0 33 4>; | |
| 71 | pinctrl-names = "default"; | |
| 72 | pinctrl-0 = <&pinctrl_uart0>; | |
| 73 | clocks = <&peri_clk 0>; | |
| 74 | }; | |
| 3fbf02a8 | 75 | |
| 2752bcaa MY |
76 | serial1: serial@54006900 { |
| 77 | compatible = "socionext,uniphier-uart"; | |
| 78 | status = "disabled"; | |
| 79 | reg = <0x54006900 0x40>; | |
| 80 | interrupts = <0 35 4>; | |
| 81 | pinctrl-names = "default"; | |
| 82 | pinctrl-0 = <&pinctrl_uart1>; | |
| 83 | clocks = <&peri_clk 1>; | |
| 84 | }; | |
| 55d945b2 | 85 | |
| 2752bcaa MY |
86 | serial2: serial@54006a00 { |
| 87 | compatible = "socionext,uniphier-uart"; | |
| 88 | status = "disabled"; | |
| 89 | reg = <0x54006a00 0x40>; | |
| 90 | interrupts = <0 37 4>; | |
| 91 | pinctrl-names = "default"; | |
| 92 | pinctrl-0 = <&pinctrl_uart2>; | |
| 93 | clocks = <&peri_clk 2>; | |
| 94 | }; | |
| 8e678e06 | 95 | |
| 2752bcaa MY |
96 | serial3: serial@54006b00 { |
| 97 | compatible = "socionext,uniphier-uart"; | |
| 98 | status = "disabled"; | |
| 99 | reg = <0x54006b00 0x40>; | |
| 100 | interrupts = <0 29 4>; | |
| 101 | pinctrl-names = "default"; | |
| 102 | pinctrl-0 = <&pinctrl_uart3>; | |
| 103 | clocks = <&peri_clk 3>; | |
| 104 | }; | |
| 8e678e06 | 105 | |
| 2752bcaa MY |
106 | i2c0: i2c@58400000 { |
| 107 | compatible = "socionext,uniphier-i2c"; | |
| 108 | status = "disabled"; | |
| 109 | reg = <0x58400000 0x40>; | |
| 110 | #address-cells = <1>; | |
| 111 | #size-cells = <0>; | |
| 112 | interrupts = <0 41 1>; | |
| 113 | pinctrl-names = "default"; | |
| 114 | pinctrl-0 = <&pinctrl_i2c0>; | |
| 115 | clocks = <&peri_clk 4>; | |
| 116 | clock-frequency = <100000>; | |
| 117 | }; | |
| 62237230 | 118 | |
| 2752bcaa MY |
119 | i2c1: i2c@58480000 { |
| 120 | compatible = "socionext,uniphier-i2c"; | |
| 121 | status = "disabled"; | |
| 122 | reg = <0x58480000 0x40>; | |
| 123 | #address-cells = <1>; | |
| 124 | #size-cells = <0>; | |
| 125 | interrupts = <0 42 1>; | |
| 126 | pinctrl-names = "default"; | |
| 127 | pinctrl-0 = <&pinctrl_i2c1>; | |
| 128 | clocks = <&peri_clk 5>; | |
| 129 | clock-frequency = <100000>; | |
| 130 | }; | |
| 61f838c7 | 131 | |
| 2752bcaa MY |
132 | /* chip-internal connection for DMD */ |
| 133 | i2c2: i2c@58500000 { | |
| 134 | compatible = "socionext,uniphier-i2c"; | |
| 135 | reg = <0x58500000 0x40>; | |
| 136 | #address-cells = <1>; | |
| 137 | #size-cells = <0>; | |
| 138 | interrupts = <0 43 1>; | |
| 139 | pinctrl-names = "default"; | |
| 140 | pinctrl-0 = <&pinctrl_i2c2>; | |
| 141 | clocks = <&peri_clk 6>; | |
| 142 | clock-frequency = <400000>; | |
| 143 | }; | |
| 629b557a | 144 | |
| 2752bcaa MY |
145 | i2c3: i2c@58580000 { |
| 146 | compatible = "socionext,uniphier-i2c"; | |
| 147 | status = "disabled"; | |
| 148 | reg = <0x58580000 0x40>; | |
| 149 | #address-cells = <1>; | |
| 150 | #size-cells = <0>; | |
| 151 | interrupts = <0 44 1>; | |
| 152 | pinctrl-names = "default"; | |
| 153 | pinctrl-0 = <&pinctrl_i2c3>; | |
| 154 | clocks = <&peri_clk 7>; | |
| 155 | clock-frequency = <100000>; | |
| 156 | }; | |
| ad0561d4 | 157 | |
| 2752bcaa MY |
158 | system_bus: system-bus@58c00000 { |
| 159 | compatible = "socionext,uniphier-system-bus"; | |
| 160 | status = "disabled"; | |
| 161 | reg = <0x58c00000 0x400>; | |
| 162 | #address-cells = <2>; | |
| 163 | #size-cells = <1>; | |
| 164 | pinctrl-names = "default"; | |
| 165 | pinctrl-0 = <&pinctrl_system_bus>; | |
| 166 | }; | |
| ad0561d4 | 167 | |
| 18088678 | 168 | smpctrl@59801000 { |
| 2752bcaa MY |
169 | compatible = "socionext,uniphier-smpctrl"; |
| 170 | reg = <0x59801000 0x400>; | |
| 171 | }; | |
| ad0561d4 | 172 | |
| 2752bcaa MY |
173 | mioctrl@59810000 { |
| 174 | compatible = "socionext,uniphier-sld8-mioctrl", | |
| 175 | "simple-mfd", "syscon"; | |
| 176 | reg = <0x59810000 0x800>; | |
| ad0561d4 | 177 | |
| 2752bcaa MY |
178 | mio_clk: clock { |
| 179 | compatible = "socionext,uniphier-sld8-mio-clock"; | |
| 180 | #clock-cells = <1>; | |
| 181 | }; | |
| ad0561d4 | 182 | |
| 2752bcaa MY |
183 | mio_rst: reset { |
| 184 | compatible = "socionext,uniphier-sld8-mio-reset"; | |
| 185 | #reset-cells = <1>; | |
| 186 | }; | |
| 187 | }; | |
| 188 | ||
| 189 | perictrl@59820000 { | |
| 190 | compatible = "socionext,uniphier-sld8-perictrl", | |
| 191 | "simple-mfd", "syscon"; | |
| 192 | reg = <0x59820000 0x200>; | |
| 193 | ||
| 194 | peri_clk: clock { | |
| 195 | compatible = "socionext,uniphier-sld8-peri-clock"; | |
| 196 | #clock-cells = <1>; | |
| 197 | }; | |
| 198 | ||
| 199 | peri_rst: reset { | |
| 200 | compatible = "socionext,uniphier-sld8-peri-reset"; | |
| 201 | #reset-cells = <1>; | |
| 202 | }; | |
| 203 | }; | |
| 204 | ||
| 205 | usb0: usb@5a800100 { | |
| 206 | compatible = "socionext,uniphier-ehci", "generic-ehci"; | |
| 207 | status = "disabled"; | |
| 208 | reg = <0x5a800100 0x100>; | |
| 209 | interrupts = <0 80 4>; | |
| 210 | pinctrl-names = "default"; | |
| 211 | pinctrl-0 = <&pinctrl_usb0>; | |
| ad81e78a MY |
212 | clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, |
| 213 | <&mio_clk 12>; | |
| 2752bcaa MY |
214 | resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, |
| 215 | <&mio_rst 12>; | |
| 216 | }; | |
| 217 | ||
| 218 | usb1: usb@5a810100 { | |
| 219 | compatible = "socionext,uniphier-ehci", "generic-ehci"; | |
| 220 | status = "disabled"; | |
| 221 | reg = <0x5a810100 0x100>; | |
| 222 | interrupts = <0 81 4>; | |
| 223 | pinctrl-names = "default"; | |
| 224 | pinctrl-0 = <&pinctrl_usb1>; | |
| ad81e78a MY |
225 | clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, |
| 226 | <&mio_clk 13>; | |
| 2752bcaa MY |
227 | resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, |
| 228 | <&mio_rst 13>; | |
| 229 | }; | |
| 230 | ||
| 231 | usb2: usb@5a820100 { | |
| 232 | compatible = "socionext,uniphier-ehci", "generic-ehci"; | |
| 233 | status = "disabled"; | |
| 234 | reg = <0x5a820100 0x100>; | |
| 235 | interrupts = <0 82 4>; | |
| 236 | pinctrl-names = "default"; | |
| 237 | pinctrl-0 = <&pinctrl_usb2>; | |
| ad81e78a MY |
238 | clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, |
| 239 | <&mio_clk 14>; | |
| 2752bcaa MY |
240 | resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, |
| 241 | <&mio_rst 14>; | |
| 242 | }; | |
| ad0561d4 | 243 | |
| 2752bcaa MY |
244 | soc-glue@5f800000 { |
| 245 | compatible = "socionext,uniphier-sld8-soc-glue", | |
| 246 | "simple-mfd", "syscon"; | |
| 247 | reg = <0x5f800000 0x2000>; | |
| 248 | ||
| 249 | pinctrl: pinctrl { | |
| 250 | compatible = "socionext,uniphier-sld8-pinctrl"; | |
| 251 | }; | |
| 252 | }; | |
| 253 | ||
| 254 | timer@60000200 { | |
| 255 | compatible = "arm,cortex-a9-global-timer"; | |
| 256 | reg = <0x60000200 0x20>; | |
| 257 | interrupts = <1 11 0x104>; | |
| 258 | clocks = <&arm_timer_clk>; | |
| 259 | }; | |
| 260 | ||
| 261 | timer@60000600 { | |
| 262 | compatible = "arm,cortex-a9-twd-timer"; | |
| 263 | reg = <0x60000600 0x20>; | |
| 264 | interrupts = <1 13 0x104>; | |
| 265 | clocks = <&arm_timer_clk>; | |
| 266 | }; | |
| 267 | ||
| 268 | intc: interrupt-controller@60001000 { | |
| 269 | compatible = "arm,cortex-a9-gic"; | |
| 270 | reg = <0x60001000 0x1000>, | |
| 271 | <0x60000100 0x100>; | |
| 272 | #interrupt-cells = <3>; | |
| 273 | interrupt-controller; | |
| 274 | }; | |
| 275 | ||
| 80a68704 MY |
276 | aidet: aidet@61830000 { |
| 277 | compatible = "socionext,uniphier-sld8-aidet"; | |
| 278 | reg = <0x61830000 0x200>; | |
| 279 | interrupt-controller; | |
| 280 | #interrupt-cells = <2>; | |
| 281 | }; | |
| 282 | ||
| 2752bcaa MY |
283 | sysctrl@61840000 { |
| 284 | compatible = "socionext,uniphier-sld8-sysctrl", | |
| 285 | "simple-mfd", "syscon"; | |
| 286 | reg = <0x61840000 0x10000>; | |
| 287 | ||
| 288 | sys_clk: clock { | |
| 289 | compatible = "socionext,uniphier-sld8-clock"; | |
| 290 | #clock-cells = <1>; | |
| 291 | }; | |
| 292 | ||
| 293 | sys_rst: reset { | |
| 294 | compatible = "socionext,uniphier-sld8-reset"; | |
| 295 | #reset-cells = <1>; | |
| 296 | }; | |
| 297 | }; | |
| 69f9cdc6 MY |
298 | |
| 299 | nand: nand@68000000 { | |
| 300 | compatible = "socionext,uniphier-denali-nand-v5a"; | |
| 301 | status = "disabled"; | |
| 302 | reg-names = "nand_data", "denali_reg"; | |
| 303 | reg = <0x68000000 0x20>, <0x68100000 0x1000>; | |
| 304 | interrupts = <0 65 4>; | |
| 305 | pinctrl-names = "default"; | |
| 306 | pinctrl-0 = <&pinctrl_nand2cs>; | |
| 307 | clocks = <&sys_clk 2>; | |
| 308 | }; | |
| 2752bcaa | 309 | }; |
| ad0561d4 | 310 | }; |
| 2752bcaa | 311 | |
| ed8bc76b | 312 | #include "uniphier-pinctrl.dtsi" |