[linux-2.6-block.git] / arch / arm / boot / dts / uniphier-ph1-pro5.dtsi

/*
 * Device Tree Source for UniPhier PH1-Pro5 SoC
 *
 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "socionext,ph1-pro5";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "socionext,uniphier-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			next-level-cache = <&l2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			next-level-cache = <&l2>;
		};
	};

	clocks {
		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};

		uart_clk: uart_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <73728000>;
		};

		i2c_clk: i2c_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		extbus: extbus {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <1>;
		};

		l2: l2-cache@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
			      <0x506c0000 0x400>;
			interrupts = <0 190 4>, <0 191 4>;
			cache-unified;
			cache-size = <(2 * 1024 * 1024)>;
			cache-sets = <512>;
			cache-line-size = <128>;
			cache-level = <2>;
			next-level-cache = <&l3>;
		};

		l3: l3-cache@500c8000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
			      <0x506c8000 0x400>;
			interrupts = <0 174 4>, <0 175 4>;
			cache-unified;
			cache-size = <(2 * 1024 * 1024)>;
			cache-sets = <512>;
			cache-line-size = <256>;
			cache-level = <3>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			interrupts = <0 33 4>;
			clocks = <&uart_clk>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			interrupts = <0 35 4>;
			clocks = <&uart_clk>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			interrupts = <0 37 4>;
			clocks = <&uart_clk>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			interrupts = <0 177 4>;
			clocks = <&uart_clk>;
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			interrupts = <0 41 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			interrupts = <0 42 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			interrupts = <0 43 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			interrupts = <0 44 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		/* i2c4 does not exist */

		/* chip-internal connection for DMD */
		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for HDMI */
		i2c6: i2c@58786000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58786000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 26 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <400000>;
		};

		system-bus-controller@58c00000 {
			compatible = "socionext,uniphier-system-bus-controller";
			reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
		};

		pinctrl: pinctrl@5f801000 {
			compatible = "socionext,ph1-pro5-pinctrl", "syscon";
			reg = <0x5f801000 0xe00>;
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <1 11 0x304>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <1 13 0x304>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
		};
	};
};

/include/ "uniphier-pinctrl.dtsi"
Commit	Line	Data
474e5ac6 MY	1	/*
	2	* Device Tree Source for UniPhier PH1-Pro5 SoC
	3	*
	4	* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	/include/ "skeleton.dtsi"
	46
	47	/ {
	48	compatible = "socionext,ph1-pro5";
	49
	50	cpus {
	51	#address-cells = <1>;
	52	#size-cells = <0>;
	53	enable-method = "socionext,uniphier-smp";
	54
	55	cpu@0 {
	56	device_type = "cpu";
	57	compatible = "arm,cortex-a9";
	58	reg = <0>;
7c62f299	59	next-level-cache = <&l2>;
474e5ac6 MY	60	};
	61
	62	cpu@1 {
	63	device_type = "cpu";
	64	compatible = "arm,cortex-a9";
	65	reg = <1>;
7c62f299	66	next-level-cache = <&l2>;
474e5ac6 MY	67	};
	68	};
	69
	70	clocks {
	71	arm_timer_clk: arm_timer_clk {
	72	#clock-cells = <0>;
	73	compatible = "fixed-clock";
	74	clock-frequency = <50000000>;
	75	};
	76
	77	uart_clk: uart_clk {
	78	#clock-cells = <0>;
	79	compatible = "fixed-clock";
	80	clock-frequency = <73728000>;
	81	};
	82
	83	i2c_clk: i2c_clk {
	84	#clock-cells = <0>;
	85	compatible = "fixed-clock";
	86	clock-frequency = <50000000>;
	87	};
	88	};
	89
	90	soc {
	91	compatible = "simple-bus";
	92	#address-cells = <1>;
	93	#size-cells = <1>;
	94	ranges;
	95	interrupt-parent = <&intc>;
	96
	97	extbus: extbus {
	98	compatible = "simple-bus";
	99	#address-cells = <2>;
	100	#size-cells = <1>;
	101	};
	102
7c62f299 MY	103	l2: l2-cache@500c0000 {
	104	compatible = "socionext,uniphier-system-cache";
	105	reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
	106	<0x506c0000 0x400>;
	107	interrupts = <0 190 4>, <0 191 4>;
	108	cache-unified;
	109	cache-size = <(2 * 1024 * 1024)>;
	110	cache-sets = <512>;
	111	cache-line-size = <128>;
	112	cache-level = <2>;
	113	next-level-cache = <&l3>;
	114	};
	115
	116	l3: l3-cache@500c8000 {
	117	compatible = "socionext,uniphier-system-cache";
	118	reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
	119	<0x506c8000 0x400>;
	120	interrupts = <0 174 4>, <0 175 4>;
	121	cache-unified;
	122	cache-size = <(2 * 1024 * 1024)>;
	123	cache-sets = <512>;
	124	cache-line-size = <256>;
	125	cache-level = <3>;
	126	};
	127
474e5ac6 MY	128	serial0: serial@54006800 {
	129	compatible = "socionext,uniphier-uart";
	130	status = "disabled";
	131	reg = <0x54006800 0x40>;
	132	pinctrl-names = "default";
	133	pinctrl-0 = <&pinctrl_uart0>;
	134	interrupts = <0 33 4>;
	135	clocks = <&uart_clk>;
	136	};
	137
	138	serial1: serial@54006900 {
	139	compatible = "socionext,uniphier-uart";
	140	status = "disabled";
	141	reg = <0x54006900 0x40>;
	142	pinctrl-names = "default";
	143	pinctrl-0 = <&pinctrl_uart1>;
	144	interrupts = <0 35 4>;
	145	clocks = <&uart_clk>;
	146	};
	147
	148	serial2: serial@54006a00 {
	149	compatible = "socionext,uniphier-uart";
	150	status = "disabled";
	151	reg = <0x54006a00 0x40>;
	152	pinctrl-names = "default";
	153	pinctrl-0 = <&pinctrl_uart2>;
	154	interrupts = <0 37 4>;
	155	clocks = <&uart_clk>;
	156	};
	157
	158	serial3: serial@54006b00 {
	159	compatible = "socionext,uniphier-uart";
	160	status = "disabled";
	161	reg = <0x54006b00 0x40>;
	162	pinctrl-names = "default";
	163	pinctrl-0 = <&pinctrl_uart3>;
	164	interrupts = <0 177 4>;
	165	clocks = <&uart_clk>;
	166	};
	167
	168	i2c0: i2c@58780000 {
	169	compatible = "socionext,uniphier-fi2c";
	170	status = "disabled";
	171	reg = <0x58780000 0x80>;
	172	#address-cells = <1>;
	173	#size-cells = <0>;
	174	pinctrl-names = "default";
	175	pinctrl-0 = <&pinctrl_i2c0>;
	176	interrupts = <0 41 4>;
	177	clocks = <&i2c_clk>;
	178	clock-frequency = <100000>;
	179	};
	180
	181	i2c1: i2c@58781000 {
	182	compatible = "socionext,uniphier-fi2c";
	183	status = "disabled";
	184	reg = <0x58781000 0x80>;
	185	#address-cells = <1>;
	186	#size-cells = <0>;
	187	pinctrl-names = "default";
	188	pinctrl-0 = <&pinctrl_i2c1>;
	189	interrupts = <0 42 4>;
	190	clocks = <&i2c_clk>;
	191	clock-frequency = <100000>;
192	};
193
194	i2c2: i2c@58782000 {
195	compatible = "socionext,uniphier-fi2c";
196	status = "disabled";
197	reg = <0x58782000 0x80>;
198	#address-cells = <1>;
199	#size-cells = <0>;
200	pinctrl-names = "default";
201	pinctrl-0 = <&pinctrl_i2c2>;
202	interrupts = <0 43 4>;
203	clocks = <&i2c_clk>;
204	clock-frequency = <100000>;
205	};
206
207	i2c3: i2c@58783000 {
208	compatible = "socionext,uniphier-fi2c";
209	status = "disabled";
210	reg = <0x58783000 0x80>;
211	#address-cells = <1>;
212	#size-cells = <0>;
213	pinctrl-names = "default";
214	pinctrl-0 = <&pinctrl_i2c3>;
215	interrupts = <0 44 4>;
216	clocks = <&i2c_clk>;
217	clock-frequency = <100000>;
218	};
219
220	/* i2c4 does not exist */
221
222	/* chip-internal connection for DMD */
223	i2c5: i2c@58785000 {
224	compatible = "socionext,uniphier-fi2c";
225	reg = <0x58785000 0x80>;
226	#address-cells = <1>;
227	#size-cells = <0>;
228	interrupts = <0 25 4>;
229	clocks = <&i2c_clk>;
230	clock-frequency = <400000>;
231	};
232
233	/* chip-internal connection for HDMI */
234	i2c6: i2c@58786000 {
235	compatible = "socionext,uniphier-fi2c";
236	reg = <0x58786000 0x80>;
237	#address-cells = <1>;
238	#size-cells = <0>;
239	interrupts = <0 26 4>;
240	clocks = <&i2c_clk>;
241	clock-frequency = <400000>;
242	};
243
1b38b0e3 MY	244	system-bus-controller@58c00000 {
	245	compatible = "socionext,uniphier-system-bus-controller";
	246	reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
474e5ac6 MY	247	};
	248
	249	pinctrl: pinctrl@5f801000 {
	250	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
	251	reg = <0x5f801000 0xe00>;
	252	};
	253
	254	timer@60000200 {
	255	compatible = "arm,cortex-a9-global-timer";
	256	reg = <0x60000200 0x20>;
	257	interrupts = <1 11 0x304>;
	258	clocks = <&arm_timer_clk>;
	259	};
	260
	261	timer@60000600 {
	262	compatible = "arm,cortex-a9-twd-timer";
	263	reg = <0x60000600 0x20>;
	264	interrupts = <1 13 0x304>;
	265	clocks = <&arm_timer_clk>;
	266	};
	267
	268	intc: interrupt-controller@60001000 {
	269	compatible = "arm,cortex-a9-gic";
	270	#interrupt-cells = <3>;
	271	interrupt-controller;
	272	reg = <0x60001000 0x1000>,
	273	<0x60000100 0x100>;
	274	};
	275	};
	276	};
	277
	278	/include/ "uniphier-pinctrl.dtsi"