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ARM: tegra: document use of standard DMA DT bindings
[linux-2.6-block.git] / arch / arm / boot / dts / tegra30.dtsi
CommitLineData
05849c93 1#include <dt-bindings/clock/tegra30-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
6cecf916 3#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 4
1bd0bd49 5#include "skeleton.dtsi"
c3e00a0e
PDS		 6
7/ {
8 compatible = "nvidia,tegra30";
9 interrupt-parent = <&intc>;
10
b6551bb9
LD		 11 aliases {
12 serial0 = &uarta;
13 serial1 = &uartb;
14 serial2 = &uartc;
15 serial3 = &uartd;
16 serial4 = &uarte;
17 };
18
e07e3dbd
TR		 19 pcie-controller {
20 compatible = "nvidia,tegra30-pcie";
21 device_type = "pci";
22 reg = <0x00003000 0x00000800 /* PADS registers */
23 0x00003800 0x00000200 /* AFI registers */
24 0x10000000 0x10000000>; /* configuration space */
25 reg-names = "pads", "afi", "cs";
26 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
27 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
28 interrupt-names = "intr", "msi";
29
30 bus-range = <0x00 0xff>;
31 #address-cells = <3>;
32 #size-cells = <2>;
33
34 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
35 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
36 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
37 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 38 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
39 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
e07e3dbd
TR		 40
41 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
42 <&tegra_car TEGRA30_CLK_AFI>,
43 <&tegra_car TEGRA30_CLK_PCIEX>,
44 <&tegra_car TEGRA30_CLK_PLL_E>,
45 <&tegra_car TEGRA30_CLK_CML0>;
46 clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
47 status = "disabled";
48
49 pci@1,0 {
50 device_type = "pci";
51 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
52 reg = <0x000800 0 0 0 0>;
53 status = "disabled";
54
55 #address-cells = <3>;
56 #size-cells = <2>;
57 ranges;
58
59 nvidia,num-lanes = <2>;
60 };
61
62 pci@2,0 {
63 device_type = "pci";
64 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
65 reg = <0x001000 0 0 0 0>;
66 status = "disabled";
67
68 #address-cells = <3>;
69 #size-cells = <2>;
70 ranges;
71
72 nvidia,num-lanes = <2>;
73 };
74
75 pci@3,0 {
76 device_type = "pci";
77 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
78 reg = <0x001800 0 0 0 0>;
79 status = "disabled";
80
81 #address-cells = <3>;
82 #size-cells = <2>;
83 ranges;
84
85 nvidia,num-lanes = <2>;
86 };
87 };
88
ed39097c
TR		 89 host1x {
90 compatible = "nvidia,tegra30-host1x", "simple-bus";
91 reg = <0x50000000 0x00024000>;
6cecf916
SW		 92 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
93 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
05849c93 94 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
ed39097c
TR		 95
96 #address-cells = <1>;
97 #size-cells = <1>;
98
99 ranges = <0x54000000 0x54000000 0x04000000>;
100
101 mpe {
102 compatible = "nvidia,tegra30-mpe";
103 reg = <0x54040000 0x00040000>;
6cecf916 104 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
05849c93 105 clocks = <&tegra_car TEGRA30_CLK_MPE>;
ed39097c
TR		 106 };
107
108 vi {
109 compatible = "nvidia,tegra30-vi";
110 reg = <0x54080000 0x00040000>;
6cecf916 111 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
05849c93 112 clocks = <&tegra_car TEGRA30_CLK_VI>;
ed39097c
TR		 113 };
114
115 epp {
116 compatible = "nvidia,tegra30-epp";
117 reg = <0x540c0000 0x00040000>;
6cecf916 118 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
05849c93 119 clocks = <&tegra_car TEGRA30_CLK_EPP>;
ed39097c
TR		 120 };
121
122 isp {
123 compatible = "nvidia,tegra30-isp";
124 reg = <0x54100000 0x00040000>;
6cecf916 125 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
05849c93 126 clocks = <&tegra_car TEGRA30_CLK_ISP>;
ed39097c
TR		 127 };
128
129 gr2d {
130 compatible = "nvidia,tegra30-gr2d";
131 reg = <0x54140000 0x00040000>;
6cecf916 132 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
05849c93 133 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
ed39097c
TR		 134 };
135
136 gr3d {
137 compatible = "nvidia,tegra30-gr3d";
138 reg = <0x54180000 0x00040000>;
c71d3909
TR		 139 clocks = <&tegra_car TEGRA30_CLK_GR3D
140 &tegra_car TEGRA30_CLK_GR3D2>;
1cbc733d 141 clock-names = "3d", "3d2";
ed39097c
TR		 142 };
143
144 dc@54200000 {
05465f4e 145 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
ed39097c 146 reg = <0x54200000 0x00040000>;
6cecf916 147 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 148 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
149 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 150 clock-names = "dc", "parent";
ed39097c
TR		 151
152 rgb {
153 status = "disabled";
154 };
155 };
156
157 dc@54240000 {
158 compatible = "nvidia,tegra30-dc";
159 reg = <0x54240000 0x00040000>;
6cecf916 160 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 161 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
162 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 163 clock-names = "dc", "parent";
ed39097c
TR		 164
165 rgb {
166 status = "disabled";
167 };
168 };
169
170 hdmi {
171 compatible = "nvidia,tegra30-hdmi";
172 reg = <0x54280000 0x00040000>;
6cecf916 173 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 174 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
175 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
1cbc733d 176 clock-names = "hdmi", "parent";
ed39097c
TR		 177 status = "disabled";
178 };
179
180 tvo {
181 compatible = "nvidia,tegra30-tvo";
182 reg = <0x542c0000 0x00040000>;
6cecf916 183 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
05849c93 184 clocks = <&tegra_car TEGRA30_CLK_TVO>;
ed39097c
TR		 185 status = "disabled";
186 };
187
188 dsi {
189 compatible = "nvidia,tegra30-dsi";
190 reg = <0x54300000 0x00040000>;
05849c93 191 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
ed39097c
TR		 192 status = "disabled";
193 };
194 };
195
73368ba0
SW		 196 timer@50004600 {
197 compatible = "arm,cortex-a9-twd-timer";
198 reg = <0x50040600 0x20>;
6cecf916
SW		 199 interrupts = <GIC_PPI 13
200 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
05849c93 201 clocks = <&tegra_car TEGRA30_CLK_TWD>;
73368ba0
SW		 202 };
203
f9eb26a4 204 intc: interrupt-controller {
c3e00a0e 205 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 206 reg = <0x50041000 0x1000
207 0x50040100 0x0100>;
2eaab06e
SW		 208 interrupt-controller;
209 #interrupt-cells = <3>;
c3e00a0e
PDS		 210 };
211
bb2c1de9
SW		 212 cache-controller {
213 compatible = "arm,pl310-cache";
214 reg = <0x50043000 0x1000>;
215 arm,data-latency = <6 6 2>;
216 arm,tag-latency = <5 5 2>;
217 cache-unified;
218 cache-level = <2>;
219 };
220
2f2b7fb2
SW		 221 timer@60005000 {
222 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
223 reg = <0x60005000 0x400>;
6cecf916
SW		 224 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
05849c93 230 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
2f2b7fb2
SW		 231 };
232
95985667
PG		 233 tegra_car: clock {
234 compatible = "nvidia,tegra30-car";
235 reg = <0x60006000 0x1000>;
236 #clock-cells = <1>;
237 };
238
f9eb26a4 239 apbdma: dma {
8051b75a
SW		 240 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
241 reg = <0x6000a000 0x1400>;
6cecf916
SW		 242 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
05849c93 274 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
8051b75a
SW		 275 };
276
c04abb3a
SW		 277 ahb: ahb {
278 compatible = "nvidia,tegra30-ahb";
279 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e
PDS		 280 };
281
f9eb26a4 282 gpio: gpio {
35f210ec 283 compatible = "nvidia,tegra30-gpio";
95decf84 284 reg = <0x6000d000 0x1000>;
6cecf916
SW		 285 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e
PDS		 293 #gpio-cells = <2>;
294 gpio-controller;
6f74dc9b
SW		 295 #interrupt-cells = <2>;
296 interrupt-controller;
c3e00a0e
PDS		 297 };
298
c04abb3a
SW		 299 pinmux: pinmux {
300 compatible = "nvidia,tegra30-pinmux";
322337b8
PR		 301 reg = <0x70000868 0xd4 /* Pad control registers */
302 0x70003000 0x3e4>; /* Mux registers */
c04abb3a
SW		 303 };
304
b6551bb9
LD		 305 /*
306 * There are two serial driver i.e. 8250 based simple serial
307 * driver and APB DMA based serial driver for higher baudrate
308 * and performace. To enable the 8250 based driver, the compatible
309 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
310 * the APB DMA based serial driver, the comptible is
311 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
312 */
313 uarta: serial@70006000 {
c3e00a0e
PDS		 314 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
315 reg = <0x70006000 0x40>;
316 reg-shift = <2>;
6cecf916 317 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 318 nvidia,dma-request-selector = <&apbdma 8>;
05849c93 319 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
223ef78d 320 status = "disabled";
c3e00a0e
PDS		 321 };
322
b6551bb9 323 uartb: serial@70006040 {
c3e00a0e
PDS		 324 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
325 reg = <0x70006040 0x40>;
326 reg-shift = <2>;
6cecf916 327 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 328 nvidia,dma-request-selector = <&apbdma 9>;
05849c93 329 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
223ef78d 330 status = "disabled";
c3e00a0e
PDS		 331 };
332
b6551bb9 333 uartc: serial@70006200 {
c3e00a0e
PDS		 334 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
335 reg = <0x70006200 0x100>;
336 reg-shift = <2>;
6cecf916 337 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 338 nvidia,dma-request-selector = <&apbdma 10>;
05849c93 339 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
223ef78d 340 status = "disabled";
c3e00a0e
PDS		 341 };
342
b6551bb9 343 uartd: serial@70006300 {
c3e00a0e
PDS		 344 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
345 reg = <0x70006300 0x100>;
346 reg-shift = <2>;
6cecf916 347 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 348 nvidia,dma-request-selector = <&apbdma 19>;
05849c93 349 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
223ef78d 350 status = "disabled";
c3e00a0e
PDS		 351 };
352
b6551bb9 353 uarte: serial@70006400 {
c3e00a0e
PDS		 354 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
355 reg = <0x70006400 0x100>;
356 reg-shift = <2>;
6cecf916 357 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 358 nvidia,dma-request-selector = <&apbdma 20>;
05849c93 359 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
223ef78d 360 status = "disabled";
c3e00a0e
PDS		 361 };
362
2b8b15da 363 pwm: pwm {
140fd977
TR		 364 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
365 reg = <0x7000a000 0x100>;
366 #pwm-cells = <2>;
05849c93 367 clocks = <&tegra_car TEGRA30_CLK_PWM>;
b69cd984 368 status = "disabled";
140fd977
TR		 369 };
370
380e04ac
SW		 371 rtc {
372 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
373 reg = <0x7000e000 0x100>;
6cecf916 374 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
05849c93 375 clocks = <&tegra_car TEGRA30_CLK_RTC>;
380e04ac
SW		 376 };
377
c04abb3a 378 i2c@7000c000 {
c04abb3a
SW		 379 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
380 reg = <0x7000c000 0x100>;
6cecf916 381 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 382 #address-cells = <1>;
383 #size-cells = <0>;
05849c93
HD		 384 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
385 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 386 clock-names = "div-clk", "fast-clk";
223ef78d 387 status = "disabled";
c3e00a0e
PDS		 388 };
389
c04abb3a 390 i2c@7000c400 {
c04abb3a
SW		 391 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
392 reg = <0x7000c400 0x100>;
6cecf916 393 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 394 #address-cells = <1>;
395 #size-cells = <0>;
05849c93
HD		 396 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
397 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 398 clock-names = "div-clk", "fast-clk";
223ef78d 399 status = "disabled";
c3e00a0e
PDS		 400 };
401
c04abb3a 402 i2c@7000c500 {
c04abb3a
SW		 403 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
404 reg = <0x7000c500 0x100>;
6cecf916 405 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 406 #address-cells = <1>;
407 #size-cells = <0>;
05849c93
HD		 408 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
409 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 410 clock-names = "div-clk", "fast-clk";
223ef78d 411 status = "disabled";
c3e00a0e
PDS		 412 };
413
c04abb3a 414 i2c@7000c700 {
c04abb3a
SW		 415 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
416 reg = <0x7000c700 0x100>;
6cecf916 417 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 418 #address-cells = <1>;
419 #size-cells = <0>;
05849c93
HD		 420 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
421 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 422 clock-names = "div-clk", "fast-clk";
223ef78d 423 status = "disabled";
c3e00a0e
PDS		 424 };
425
c04abb3a 426 i2c@7000d000 {
c04abb3a
SW		 427 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
428 reg = <0x7000d000 0x100>;
6cecf916 429 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 430 #address-cells = <1>;
431 #size-cells = <0>;
05849c93
HD		 432 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
433 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 434 clock-names = "div-clk", "fast-clk";
223ef78d 435 status = "disabled";
c04abb3a
SW		 436 };
437
a86b0db3
LD		 438 spi@7000d400 {
439 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
440 reg = <0x7000d400 0x200>;
6cecf916 441 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 442 nvidia,dma-request-selector = <&apbdma 15>;
443 #address-cells = <1>;
444 #size-cells = <0>;
05849c93 445 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
a86b0db3
LD		 446 status = "disabled";
447 };
448
449 spi@7000d600 {
450 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
451 reg = <0x7000d600 0x200>;
6cecf916 452 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 453 nvidia,dma-request-selector = <&apbdma 16>;
454 #address-cells = <1>;
455 #size-cells = <0>;
05849c93 456 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
a86b0db3
LD		 457 status = "disabled";
458 };
459
460 spi@7000d800 {
461 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d 462 reg = <0x7000d800 0x200>;
6cecf916 463 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 464 nvidia,dma-request-selector = <&apbdma 17>;
465 #address-cells = <1>;
466 #size-cells = <0>;
05849c93 467 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
a86b0db3
LD		 468 status = "disabled";
469 };
470
471 spi@7000da00 {
472 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
473 reg = <0x7000da00 0x200>;
6cecf916 474 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 475 nvidia,dma-request-selector = <&apbdma 18>;
476 #address-cells = <1>;
477 #size-cells = <0>;
05849c93 478 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
a86b0db3
LD		 479 status = "disabled";
480 };
481
482 spi@7000dc00 {
483 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
484 reg = <0x7000dc00 0x200>;
6cecf916 485 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 486 nvidia,dma-request-selector = <&apbdma 27>;
487 #address-cells = <1>;
488 #size-cells = <0>;
05849c93 489 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
a86b0db3
LD		 490 status = "disabled";
491 };
492
493 spi@7000de00 {
494 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
495 reg = <0x7000de00 0x200>;
6cecf916 496 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 497 nvidia,dma-request-selector = <&apbdma 28>;
498 #address-cells = <1>;
499 #size-cells = <0>;
05849c93 500 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
a86b0db3
LD		 501 status = "disabled";
502 };
503
699ed4b9
LD		 504 kbc {
505 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
506 reg = <0x7000e200 0x100>;
6cecf916 507 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
05849c93 508 clocks = <&tegra_car TEGRA30_CLK_KBC>;
699ed4b9
LD		 509 status = "disabled";
510 };
511
c04abb3a 512 pmc {
2b84e53b 513 compatible = "nvidia,tegra30-pmc";
c04abb3a 514 reg = <0x7000e400 0x400>;
05849c93 515 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
7021d122 516 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 517 };
518
a9140aa5 519 memory-controller {
c04abb3a
SW		 520 compatible = "nvidia,tegra30-mc";
521 reg = <0x7000f000 0x010
522 0x7000f03c 0x1b4
523 0x7000f200 0x028
524 0x7000f284 0x17c>;
6cecf916 525 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a
SW		 526 };
527
3fbf07d8 528 iommu {
c04abb3a
SW		 529 compatible = "nvidia,tegra30-smmu";
530 reg = <0x7000f010 0x02c
531 0x7000f1f0 0x010
532 0x7000f228 0x05c>;
533 nvidia,#asids = <4>; /* # of ASIDs */
534 dma-window = <0 0x40000000>; /* IOVA start & length */
535 nvidia,ahb = <&ahb>;
c3e00a0e 536 };
9ee6a5c4
SW		 537
538 ahub {
539 compatible = "nvidia,tegra30-ahub";
5ff48887
SW		 540 reg = <0x70080000 0x200
541 0x70080200 0x100>;
6cecf916 542 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9ee6a5c4 543 nvidia,dma-request-selector = <&apbdma 1>;
05849c93
HD		 544 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
545 <&tegra_car TEGRA30_CLK_APBIF>,
546 <&tegra_car TEGRA30_CLK_I2S0>,
547 <&tegra_car TEGRA30_CLK_I2S1>,
548 <&tegra_car TEGRA30_CLK_I2S2>,
549 <&tegra_car TEGRA30_CLK_I2S3>,
550 <&tegra_car TEGRA30_CLK_I2S4>,
551 <&tegra_car TEGRA30_CLK_DAM0>,
552 <&tegra_car TEGRA30_CLK_DAM1>,
553 <&tegra_car TEGRA30_CLK_DAM2>,
554 <&tegra_car TEGRA30_CLK_SPDIF_IN>;
1cbc733d
PG		 555 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
556 "i2s3", "i2s4", "dam0", "dam1", "dam2",
557 "spdif_in";
9ee6a5c4
SW		 558 ranges;
559 #address-cells = <1>;
560 #size-cells = <1>;
561
562 tegra_i2s0: i2s@70080300 {
563 compatible = "nvidia,tegra30-i2s";
564 reg = <0x70080300 0x100>;
565 nvidia,ahub-cif-ids = <4 4>;
05849c93 566 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
223ef78d 567 status = "disabled";
9ee6a5c4
SW		 568 };
569
570 tegra_i2s1: i2s@70080400 {
571 compatible = "nvidia,tegra30-i2s";
572 reg = <0x70080400 0x100>;
573 nvidia,ahub-cif-ids = <5 5>;
05849c93 574 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
223ef78d 575 status = "disabled";
9ee6a5c4
SW		 576 };
577
578 tegra_i2s2: i2s@70080500 {
579 compatible = "nvidia,tegra30-i2s";
580 reg = <0x70080500 0x100>;
581 nvidia,ahub-cif-ids = <6 6>;
05849c93 582 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
223ef78d 583 status = "disabled";
9ee6a5c4
SW		 584 };
585
586 tegra_i2s3: i2s@70080600 {
587 compatible = "nvidia,tegra30-i2s";
588 reg = <0x70080600 0x100>;
589 nvidia,ahub-cif-ids = <7 7>;
05849c93 590 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
223ef78d 591 status = "disabled";
9ee6a5c4
SW		 592 };
593
594 tegra_i2s4: i2s@70080700 {
595 compatible = "nvidia,tegra30-i2s";
596 reg = <0x70080700 0x100>;
597 nvidia,ahub-cif-ids = <8 8>;
05849c93 598 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
223ef78d 599 status = "disabled";
9ee6a5c4
SW		 600 };
601 };
7868a9bc 602
c04abb3a
SW		 603 sdhci@78000000 {
604 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
605 reg = <0x78000000 0x200>;
6cecf916 606 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
05849c93 607 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
223ef78d 608 status = "disabled";
7868a9bc 609 };
ecf43742 610
c04abb3a
SW		 611 sdhci@78000200 {
612 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
613 reg = <0x78000200 0x200>;
6cecf916 614 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
05849c93 615 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
223ef78d 616 status = "disabled";
ecf43742 617 };
54174a33 618
c04abb3a
SW		 619 sdhci@78000400 {
620 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
621 reg = <0x78000400 0x200>;
6cecf916 622 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
05849c93 623 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
223ef78d 624 status = "disabled";
c04abb3a
SW		 625 };
626
627 sdhci@78000600 {
628 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
629 reg = <0x78000600 0x200>;
6cecf916 630 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
05849c93 631 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
223ef78d 632 status = "disabled";
c04abb3a
SW		 633 };
634
cc34c9f7
TT		 635 usb@7d000000 {
636 compatible = "nvidia,tegra30-ehci", "usb-ehci";
637 reg = <0x7d000000 0x4000>;
638 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
639 phy_type = "utmi";
640 clocks = <&tegra_car TEGRA30_CLK_USBD>;
641 nvidia,needs-double-reset;
642 nvidia,phy = <&phy1>;
643 status = "disabled";
644 };
645
646 phy1: usb-phy@7d000000 {
647 compatible = "nvidia,tegra30-usb-phy";
648 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
649 phy_type = "utmi";
650 clocks = <&tegra_car TEGRA30_CLK_USBD>,
651 <&tegra_car TEGRA30_CLK_PLL_U>,
652 <&tegra_car TEGRA30_CLK_USBD>;
653 clock-names = "reg", "pll_u", "utmi-pads";
654 nvidia,hssync-start-delay = <9>;
655 nvidia,idle-wait-delay = <17>;
656 nvidia,elastic-limit = <16>;
657 nvidia,term-range-adj = <6>;
658 nvidia,xcvr-setup = <51>;
659 nvidia.xcvr-setup-use-fuses;
660 nvidia,xcvr-lsfslew = <1>;
661 nvidia,xcvr-lsrslew = <1>;
662 nvidia,xcvr-hsslew = <32>;
663 nvidia,hssquelch-level = <2>;
664 nvidia,hsdiscon-level = <5>;
665 status = "disabled";
666 };
667
668 usb@7d004000 {
669 compatible = "nvidia,tegra30-ehci", "usb-ehci";
670 reg = <0x7d004000 0x4000>;
671 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
672 phy_type = "ulpi";
673 clocks = <&tegra_car TEGRA30_CLK_USB2>;
674 nvidia,phy = <&phy2>;
675 status = "disabled";
676 };
677
678 phy2: usb-phy@7d004000 {
679 compatible = "nvidia,tegra30-usb-phy";
680 reg = <0x7d004000 0x4000>;
681 phy_type = "ulpi";
682 clocks = <&tegra_car TEGRA30_CLK_USB2>,
683 <&tegra_car TEGRA30_CLK_PLL_U>,
684 <&tegra_car TEGRA30_CLK_CDEV2>;
685 clock-names = "reg", "pll_u", "ulpi-link";
686 status = "disabled";
687 };
688
689 usb@7d008000 {
690 compatible = "nvidia,tegra30-ehci", "usb-ehci";
691 reg = <0x7d008000 0x4000>;
692 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
693 phy_type = "utmi";
694 clocks = <&tegra_car TEGRA30_CLK_USB3>;
695 nvidia,phy = <&phy3>;
696 status = "disabled";
697 };
698
699 phy3: usb-phy@7d008000 {
700 compatible = "nvidia,tegra30-usb-phy";
701 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
702 phy_type = "utmi";
703 clocks = <&tegra_car TEGRA30_CLK_USB3>,
704 <&tegra_car TEGRA30_CLK_PLL_U>,
705 <&tegra_car TEGRA30_CLK_USBD>;
706 clock-names = "reg", "pll_u", "utmi-pads";
707 nvidia,hssync-start-delay = <0>;
708 nvidia,idle-wait-delay = <17>;
709 nvidia,elastic-limit = <16>;
710 nvidia,term-range-adj = <6>;
711 nvidia,xcvr-setup = <51>;
712 nvidia.xcvr-setup-use-fuses;
713 nvidia,xcvr-lsfslew = <2>;
714 nvidia,xcvr-lsrslew = <2>;
715 nvidia,xcvr-hsslew = <32>;
716 nvidia,hssquelch-level = <2>;
717 nvidia,hsdiscon-level = <5>;
718 status = "disabled";
719 };
720
7d19a34a
HD		 721 cpus {
722 #address-cells = <1>;
723 #size-cells = <0>;
724
725 cpu@0 {
726 device_type = "cpu";
727 compatible = "arm,cortex-a9";
728 reg = <0>;
729 };
730
731 cpu@1 {
732 device_type = "cpu";
733 compatible = "arm,cortex-a9";
734 reg = <1>;
735 };
736
737 cpu@2 {
738 device_type = "cpu";
739 compatible = "arm,cortex-a9";
740 reg = <2>;
741 };
742
743 cpu@3 {
744 device_type = "cpu";
745 compatible = "arm,cortex-a9";
746 reg = <3>;
747 };
748 };
749
c04abb3a
SW		 750 pmu {
751 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 752 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
54174a33 756 };
c3e00a0e 757};
Linux 6.x block layer and io_uring tree(s)