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ARM: tegra: Add parent clock to DSI output
[linux-2.6-block.git] / arch / arm / boot / dts / tegra30.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
05849c93 2#include <dt-bindings/clock/tegra30-car.h>
3325f1bc 3#include <dt-bindings/gpio/tegra-gpio.h>
6d9adf6f 4#include <dt-bindings/memory/tegra30-mc.h>
a47c662a 5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 6#include <dt-bindings/interrupt-controller/arm-gic.h>
86614b5d 7#include <dt-bindings/soc/tegra-pmc.h>
3325f1bc 8
c3e00a0e
PDS		 9/ {
10 compatible = "nvidia,tegra30";
870c81a4 11 interrupt-parent = <&lic>;
f48ba1ae
KK		 12 #address-cells = <1>;
13 #size-cells = <1>;
14
48299769 15 memory@80000000 {
f48ba1ae 16 device_type = "memory";
48299769 17 reg = <0x80000000 0x0>;
f48ba1ae 18 };
c3e00a0e 19
508d690e 20 pcie@3000 {
e07e3dbd
TR		 21 compatible = "nvidia,tegra30-pcie";
22 device_type = "pci";
9482a170
TR		 23 reg = <0x00003000 0x00000800>, /* PADS registers */
24 <0x00003800 0x00000200>, /* AFI registers */
25 <0x10000000 0x10000000>; /* configuration space */
e07e3dbd 26 reg-names = "pads", "afi", "cs";
9482a170
TR		 27 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
28 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
e07e3dbd
TR		 29 interrupt-names = "intr", "msi";
30
97070bd4
LS		 31 #interrupt-cells = <1>;
32 interrupt-map-mask = <0 0 0 0>;
33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34
e07e3dbd
TR		 35 bus-range = <0x00 0xff>;
36 #address-cells = <3>;
37 #size-cells = <2>;
38
9482a170
TR		 39 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
40 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
41 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
42 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
43 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
44 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
e07e3dbd
TR		 45
46 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
47 <&tegra_car TEGRA30_CLK_AFI>,
e07e3dbd
TR		 48 <&tegra_car TEGRA30_CLK_PLL_E>,
49 <&tegra_car TEGRA30_CLK_CML0>;
2bd541ff 50 clock-names = "pex", "afi", "pll_e", "cml";
3393d422 51 resets = <&tegra_car 70>,
d8b316b2
MZ		 52 <&tegra_car 72>,
53 <&tegra_car 74>;
3393d422 54 reset-names = "pex", "afi", "pcie_x";
e07e3dbd
TR		 55 status = "disabled";
56
57 pci@1,0 {
58 device_type = "pci";
59 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
60 reg = <0x000800 0 0 0 0>;
508d690e 61 bus-range = <0x00 0xff>;
e07e3dbd
TR		 62 status = "disabled";
63
64 #address-cells = <3>;
65 #size-cells = <2>;
66 ranges;
67
68 nvidia,num-lanes = <2>;
69 };
70
71 pci@2,0 {
72 device_type = "pci";
73 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
74 reg = <0x001000 0 0 0 0>;
508d690e 75 bus-range = <0x00 0xff>;
e07e3dbd
TR		 76 status = "disabled";
77
78 #address-cells = <3>;
79 #size-cells = <2>;
80 ranges;
81
82 nvidia,num-lanes = <2>;
83 };
84
85 pci@3,0 {
86 device_type = "pci";
87 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
88 reg = <0x001800 0 0 0 0>;
508d690e 89 bus-range = <0x00 0xff>;
e07e3dbd
TR		 90 status = "disabled";
91
92 #address-cells = <3>;
93 #size-cells = <2>;
94 ranges;
95
96 nvidia,num-lanes = <2>;
97 };
98 };
99
7fb09952 100 sram@40000000 {
ea857036
DO		 101 compatible = "mmio-sram";
102 reg = <0x40000000 0x40000>;
103 #address-cells = <1>;
104 #size-cells = <1>;
105 ranges = <0 0x40000000 0x40000>;
55f939c2 106
7fb09952 107 vde_pool: sram@400 {
55f939c2
DO		 108 reg = <0x400 0x3fc00>;
109 pool;
110 };
ea857036
DO		 111 };
112
58ecb23f 113 host1x@50000000 {
f0fd20a5 114 compatible = "nvidia,tegra30-host1x";
ed39097c 115 reg = <0x50000000 0x00024000>;
6cecf916
SW		 116 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
117 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
6cc05ba2 118 interrupt-names = "syncpt", "host1x";
05849c93 119 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
6cc05ba2 120 clock-names = "host1x";
3393d422
SW		 121 resets = <&tegra_car 28>;
122 reset-names = "host1x";
1dac1827 123 iommus = <&mc TEGRA_SWGROUP_HC>;
ed39097c
TR		 124
125 #address-cells = <1>;
126 #size-cells = <1>;
127
128 ranges = <0x54000000 0x54000000 0x04000000>;
129
58ecb23f 130 mpe@54040000 {
ed39097c
TR		 131 compatible = "nvidia,tegra30-mpe";
132 reg = <0x54040000 0x00040000>;
6cecf916 133 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
05849c93 134 clocks = <&tegra_car TEGRA30_CLK_MPE>;
3393d422
SW		 135 resets = <&tegra_car 60>;
136 reset-names = "mpe";
1dac1827
DO		 137
138 iommus = <&mc TEGRA_SWGROUP_MPE>;
ed39097c
TR		 139 };
140
58ecb23f 141 vi@54080000 {
ed39097c
TR		 142 compatible = "nvidia,tegra30-vi";
143 reg = <0x54080000 0x00040000>;
6cecf916 144 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
05849c93 145 clocks = <&tegra_car TEGRA30_CLK_VI>;
3393d422
SW		 146 resets = <&tegra_car 20>;
147 reset-names = "vi";
1dac1827
DO		 148
149 iommus = <&mc TEGRA_SWGROUP_VI>;
ed39097c
TR		 150 };
151
58ecb23f 152 epp@540c0000 {
ed39097c
TR		 153 compatible = "nvidia,tegra30-epp";
154 reg = <0x540c0000 0x00040000>;
6cecf916 155 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
05849c93 156 clocks = <&tegra_car TEGRA30_CLK_EPP>;
3393d422
SW		 157 resets = <&tegra_car 19>;
158 reset-names = "epp";
1dac1827
DO		 159
160 iommus = <&mc TEGRA_SWGROUP_EPP>;
ed39097c
TR		 161 };
162
58ecb23f 163 isp@54100000 {
ed39097c
TR		 164 compatible = "nvidia,tegra30-isp";
165 reg = <0x54100000 0x00040000>;
6cecf916 166 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
05849c93 167 clocks = <&tegra_car TEGRA30_CLK_ISP>;
3393d422
SW		 168 resets = <&tegra_car 23>;
169 reset-names = "isp";
1dac1827
DO		 170
171 iommus = <&mc TEGRA_SWGROUP_ISP>;
ed39097c
TR		 172 };
173
58ecb23f 174 gr2d@54140000 {
ed39097c
TR		 175 compatible = "nvidia,tegra30-gr2d";
176 reg = <0x54140000 0x00040000>;
6cecf916 177 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
da45d738 178 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
3393d422
SW		 179 resets = <&tegra_car 21>;
180 reset-names = "2d";
1dac1827
DO		 181
182 iommus = <&mc TEGRA_SWGROUP_G2>;
ed39097c
TR		 183 };
184
58ecb23f 185 gr3d@54180000 {
ed39097c
TR		 186 compatible = "nvidia,tegra30-gr3d";
187 reg = <0x54180000 0x00040000>;
9482a170
TR		 188 clocks = <&tegra_car TEGRA30_CLK_GR3D>,
189 <&tegra_car TEGRA30_CLK_GR3D2>;
1cbc733d 190 clock-names = "3d", "3d2";
3393d422 191 resets = <&tegra_car 24>,
d8b316b2 192 <&tegra_car 98>;
3393d422 193 reset-names = "3d", "3d2";
1dac1827
DO		 194
195 iommus = <&mc TEGRA_SWGROUP_NV>,
196 <&mc TEGRA_SWGROUP_NV2>;
ed39097c
TR		 197 };
198
199 dc@54200000 {
05465f4e 200 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
ed39097c 201 reg = <0x54200000 0x00040000>;
6cecf916 202 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 203 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
204 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 205 clock-names = "dc", "parent";
3393d422
SW		 206 resets = <&tegra_car 27>;
207 reset-names = "dc";
ed39097c 208
6d9adf6f
TR		 209 iommus = <&mc TEGRA_SWGROUP_DC>;
210
688b56b4
TR		 211 nvidia,head = <0>;
212
ed39097c
TR		 213 rgb {
214 status = "disabled";
215 };
216 };
217
218 dc@54240000 {
219 compatible = "nvidia,tegra30-dc";
220 reg = <0x54240000 0x00040000>;
6cecf916 221 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 222 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
223 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 224 clock-names = "dc", "parent";
3393d422
SW		 225 resets = <&tegra_car 26>;
226 reset-names = "dc";
ed39097c 227
6d9adf6f
TR		 228 iommus = <&mc TEGRA_SWGROUP_DCB>;
229
688b56b4
TR		 230 nvidia,head = <1>;
231
ed39097c
TR		 232 rgb {
233 status = "disabled";
234 };
235 };
236
58ecb23f 237 hdmi@54280000 {
ed39097c
TR		 238 compatible = "nvidia,tegra30-hdmi";
239 reg = <0x54280000 0x00040000>;
6cecf916 240 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 241 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
242 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
1cbc733d 243 clock-names = "hdmi", "parent";
3393d422
SW		 244 resets = <&tegra_car 51>;
245 reset-names = "hdmi";
ed39097c
TR		 246 status = "disabled";
247 };
248
58ecb23f 249 tvo@542c0000 {
ed39097c
TR		 250 compatible = "nvidia,tegra30-tvo";
251 reg = <0x542c0000 0x00040000>;
6cecf916 252 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
05849c93 253 clocks = <&tegra_car TEGRA30_CLK_TVO>;
ed39097c
TR		 254 status = "disabled";
255 };
256
58ecb23f 257 dsi@54300000 {
ed39097c
TR		 258 compatible = "nvidia,tegra30-dsi";
259 reg = <0x54300000 0x00040000>;
eb6563a6
TR		 260 clocks = <&tegra_car TEGRA30_CLK_DSIA>,
261 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
262 clock-names = "dsi", "parent";
3393d422
SW		 263 resets = <&tegra_car 48>;
264 reset-names = "dsi";
ed39097c
TR		 265 status = "disabled";
266 };
267 };
268
2cda1880 269 timer@50040600 {
73368ba0
SW		 270 compatible = "arm,cortex-a9-twd-timer";
271 reg = <0x50040600 0x20>;
870c81a4 272 interrupt-parent = <&intc>;
6cecf916 273 interrupts = <GIC_PPI 13
e7d9b270 274 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
05849c93 275 clocks = <&tegra_car TEGRA30_CLK_TWD>;
73368ba0
SW		 276 };
277
58ecb23f 278 intc: interrupt-controller@50041000 {
c3e00a0e 279 compatible = "arm,cortex-a9-gic";
9482a170
TR		 280 reg = <0x50041000 0x1000>,
281 <0x50040100 0x0100>;
2eaab06e
SW		 282 interrupt-controller;
283 #interrupt-cells = <3>;
870c81a4 284 interrupt-parent = <&intc>;
c3e00a0e
PDS		 285 };
286
58ecb23f 287 cache-controller@50043000 {
bb2c1de9
SW		 288 compatible = "arm,pl310-cache";
289 reg = <0x50043000 0x1000>;
290 arm,data-latency = <6 6 2>;
291 arm,tag-latency = <5 5 2>;
292 cache-unified;
293 cache-level = <2>;
294 };
295
870c81a4
MZ		 296 lic: interrupt-controller@60004000 {
297 compatible = "nvidia,tegra30-ictlr";
298 reg = <0x60004000 0x100>,
299 <0x60004100 0x50>,
300 <0x60004200 0x50>,
301 <0x60004300 0x50>,
302 <0x60004400 0x50>;
303 interrupt-controller;
304 #interrupt-cells = <3>;
305 interrupt-parent = <&intc>;
306 };
307
2f2b7fb2
SW		 308 timer@60005000 {
309 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
310 reg = <0x60005000 0x400>;
6cecf916
SW		 311 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
05849c93 317 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
2f2b7fb2
SW		 318 };
319
58ecb23f 320 tegra_car: clock@60006000 {
95985667
PG		 321 compatible = "nvidia,tegra30-car";
322 reg = <0x60006000 0x1000>;
323 #clock-cells = <1>;
3393d422 324 #reset-cells = <1>;
95985667
PG		 325 };
326
b1023134
TR		 327 flow-controller@60007000 {
328 compatible = "nvidia,tegra30-flowctrl";
329 reg = <0x60007000 0x1000>;
330 };
331
58ecb23f 332 apbdma: dma@6000a000 {
8051b75a
SW		 333 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
334 reg = <0x6000a000 0x1400>;
6cecf916
SW		 335 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
05849c93 367 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
3393d422
SW		 368 resets = <&tegra_car 34>;
369 reset-names = "dma";
034d023f 370 #dma-cells = <1>;
8051b75a
SW		 371 };
372
0d5ccb38 373 ahb: ahb@6000c000 {
c04abb3a 374 compatible = "nvidia,tegra30-ahb";
0d5ccb38 375 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e
PDS		 376 };
377
1078946b
DO		 378 actmon@6000c800 {
379 compatible = "nvidia,tegra30-actmon";
380 reg = <0x6000c800 0x400>;
381 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
383 <&tegra_car TEGRA30_CLK_EMC>;
384 clock-names = "actmon", "emc";
385 resets = <&tegra_car TEGRA30_CLK_ACTMON>;
386 reset-names = "actmon";
387 };
388
58ecb23f 389 gpio: gpio@6000d000 {
35f210ec 390 compatible = "nvidia,tegra30-gpio";
95decf84 391 reg = <0x6000d000 0x1000>;
6cecf916
SW		 392 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e
PDS		 400 #gpio-cells = <2>;
401 gpio-controller;
6f74dc9b
SW		 402 #interrupt-cells = <2>;
403 interrupt-controller;
4f1d8414 404 /*
17cdddf0 405 gpio-ranges = <&pinmux 0 0 248>;
4f1d8414 406 */
c3e00a0e
PDS		 407 };
408
55f939c2
DO		 409 vde@6001a000 {
410 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
9482a170
TR		 411 reg = <0x6001a000 0x1000>, /* Syntax Engine */
412 <0x6001b000 0x1000>, /* Video Bitstream Engine */
413 <0x6001c000 0x100>, /* Macroblock Engine */
414 <0x6001c200 0x100>, /* Post-processing Engine */
415 <0x6001c400 0x100>, /* Motion Compensation Engine */
416 <0x6001c600 0x100>, /* Transform Engine */
417 <0x6001c800 0x100>, /* Pixel prediction block */
418 <0x6001ca00 0x100>, /* Video DMA */
419 <0x6001d800 0x400>; /* Video frame controls */
55f939c2
DO		 420 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
421 "tfe", "ppb", "vdma", "frameid";
422 iram = <&vde_pool>; /* IRAM region */
423 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
424 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
425 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
426 interrupt-names = "sync-token", "bsev", "sxe";
427 clocks = <&tegra_car TEGRA30_CLK_VDE>;
d072094b
DO		 428 reset-names = "vde", "mc";
429 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
cdc233fb 430 iommus = <&mc TEGRA_SWGROUP_VDE>;
55f939c2
DO		 431 };
432
155dfc7b
PDS		 433 apbmisc@70000800 {
434 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
9482a170
TR		 435 reg = <0x70000800 0x64>, /* Chip revision */
436 <0x70000008 0x04>; /* Strapping options */
155dfc7b
PDS		 437 };
438
58ecb23f 439 pinmux: pinmux@70000868 {
c04abb3a 440 compatible = "nvidia,tegra30-pinmux";
9482a170
TR		 441 reg = <0x70000868 0x0d4>, /* Pad control registers */
442 <0x70003000 0x3e4>; /* Mux registers */
c04abb3a
SW		 443 };
444
b6551bb9
LD		 445 /*
446 * There are two serial driver i.e. 8250 based simple serial
447 * driver and APB DMA based serial driver for higher baudrate
448 * and performace. To enable the 8250 based driver, the compatible
449 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
e1098248 450 * the APB DMA based serial driver, the compatible is
b6551bb9
LD		 451 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
452 */
453 uarta: serial@70006000 {
c3e00a0e
PDS		 454 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
455 reg = <0x70006000 0x40>;
456 reg-shift = <2>;
6cecf916 457 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
05849c93 458 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
3393d422
SW		 459 resets = <&tegra_car 6>;
460 reset-names = "serial";
034d023f
SW		 461 dmas = <&apbdma 8>, <&apbdma 8>;
462 dma-names = "rx", "tx";
223ef78d 463 status = "disabled";
c3e00a0e
PDS		 464 };
465
b6551bb9 466 uartb: serial@70006040 {
c3e00a0e
PDS		 467 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
468 reg = <0x70006040 0x40>;
469 reg-shift = <2>;
6cecf916 470 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
05849c93 471 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
3393d422
SW		 472 resets = <&tegra_car 7>;
473 reset-names = "serial";
034d023f
SW		 474 dmas = <&apbdma 9>, <&apbdma 9>;
475 dma-names = "rx", "tx";
223ef78d 476 status = "disabled";
c3e00a0e
PDS		 477 };
478
b6551bb9 479 uartc: serial@70006200 {
c3e00a0e
PDS		 480 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
481 reg = <0x70006200 0x100>;
482 reg-shift = <2>;
6cecf916 483 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
05849c93 484 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
3393d422
SW		 485 resets = <&tegra_car 55>;
486 reset-names = "serial";
034d023f
SW		 487 dmas = <&apbdma 10>, <&apbdma 10>;
488 dma-names = "rx", "tx";
223ef78d 489 status = "disabled";
c3e00a0e
PDS		 490 };
491
b6551bb9 492 uartd: serial@70006300 {
c3e00a0e
PDS		 493 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
494 reg = <0x70006300 0x100>;
495 reg-shift = <2>;
6cecf916 496 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
05849c93 497 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
3393d422
SW		 498 resets = <&tegra_car 65>;
499 reset-names = "serial";
034d023f
SW		 500 dmas = <&apbdma 19>, <&apbdma 19>;
501 dma-names = "rx", "tx";
223ef78d 502 status = "disabled";
c3e00a0e
PDS		 503 };
504
b6551bb9 505 uarte: serial@70006400 {
c3e00a0e
PDS		 506 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
507 reg = <0x70006400 0x100>;
508 reg-shift = <2>;
6cecf916 509 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
05849c93 510 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
3393d422
SW		 511 resets = <&tegra_car 66>;
512 reset-names = "serial";
034d023f
SW		 513 dmas = <&apbdma 20>, <&apbdma 20>;
514 dma-names = "rx", "tx";
223ef78d 515 status = "disabled";
c3e00a0e
PDS		 516 };
517
5e35c1f0
MK		 518 gmi@70009000 {
519 compatible = "nvidia,tegra30-gmi";
520 reg = <0x70009000 0x1000>;
521 #address-cells = <2>;
522 #size-cells = <1>;
523 ranges = <0 0 0x48000000 0x7ffffff>;
524 clocks = <&tegra_car TEGRA30_CLK_NOR>;
525 clock-names = "gmi";
526 resets = <&tegra_car 42>;
527 reset-names = "gmi";
528 status = "disabled";
529 };
530
58ecb23f 531 pwm: pwm@7000a000 {
140fd977
TR		 532 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
533 reg = <0x7000a000 0x100>;
534 #pwm-cells = <2>;
05849c93 535 clocks = <&tegra_car TEGRA30_CLK_PWM>;
3393d422
SW		 536 resets = <&tegra_car 17>;
537 reset-names = "pwm";
b69cd984 538 status = "disabled";
140fd977
TR		 539 };
540
58ecb23f 541 rtc@7000e000 {
380e04ac
SW		 542 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
543 reg = <0x7000e000 0x100>;
6cecf916 544 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
05849c93 545 clocks = <&tegra_car TEGRA30_CLK_RTC>;
380e04ac
SW		 546 };
547
c04abb3a 548 i2c@7000c000 {
d8b316b2 549 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a 550 reg = <0x7000c000 0x100>;
6cecf916 551 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 552 #address-cells = <1>;
553 #size-cells = <0>;
05849c93
HD		 554 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
555 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 556 clock-names = "div-clk", "fast-clk";
3393d422
SW		 557 resets = <&tegra_car 12>;
558 reset-names = "i2c";
034d023f
SW		 559 dmas = <&apbdma 21>, <&apbdma 21>;
560 dma-names = "rx", "tx";
223ef78d 561 status = "disabled";
c3e00a0e
PDS		 562 };
563
c04abb3a 564 i2c@7000c400 {
c04abb3a
SW		 565 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
566 reg = <0x7000c400 0x100>;
6cecf916 567 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 568 #address-cells = <1>;
569 #size-cells = <0>;
05849c93
HD		 570 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
571 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 572 clock-names = "div-clk", "fast-clk";
3393d422
SW		 573 resets = <&tegra_car 54>;
574 reset-names = "i2c";
034d023f
SW		 575 dmas = <&apbdma 22>, <&apbdma 22>;
576 dma-names = "rx", "tx";
223ef78d 577 status = "disabled";
c3e00a0e
PDS		 578 };
579
c04abb3a 580 i2c@7000c500 {
c04abb3a
SW		 581 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
582 reg = <0x7000c500 0x100>;
6cecf916 583 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 584 #address-cells = <1>;
585 #size-cells = <0>;
05849c93
HD		 586 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
587 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 588 clock-names = "div-clk", "fast-clk";
3393d422
SW		 589 resets = <&tegra_car 67>;
590 reset-names = "i2c";
034d023f
SW		 591 dmas = <&apbdma 23>, <&apbdma 23>;
592 dma-names = "rx", "tx";
223ef78d 593 status = "disabled";
c3e00a0e
PDS		 594 };
595
c04abb3a 596 i2c@7000c700 {
c04abb3a
SW		 597 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
598 reg = <0x7000c700 0x100>;
6cecf916 599 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 600 #address-cells = <1>;
601 #size-cells = <0>;
05849c93
HD		 602 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
603 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
3393d422
SW		 604 resets = <&tegra_car 103>;
605 reset-names = "i2c";
1cbc733d 606 clock-names = "div-clk", "fast-clk";
034d023f
SW		 607 dmas = <&apbdma 26>, <&apbdma 26>;
608 dma-names = "rx", "tx";
223ef78d 609 status = "disabled";
c3e00a0e
PDS		 610 };
611
c04abb3a 612 i2c@7000d000 {
c04abb3a
SW		 613 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
614 reg = <0x7000d000 0x100>;
6cecf916 615 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 616 #address-cells = <1>;
617 #size-cells = <0>;
05849c93
HD		 618 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
619 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 620 clock-names = "div-clk", "fast-clk";
3393d422
SW		 621 resets = <&tegra_car 47>;
622 reset-names = "i2c";
034d023f
SW		 623 dmas = <&apbdma 24>, <&apbdma 24>;
624 dma-names = "rx", "tx";
223ef78d 625 status = "disabled";
c04abb3a
SW		 626 };
627
a86b0db3
LD		 628 spi@7000d400 {
629 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
630 reg = <0x7000d400 0x200>;
6cecf916 631 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 632 #address-cells = <1>;
633 #size-cells = <0>;
05849c93 634 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
3393d422
SW		 635 resets = <&tegra_car 41>;
636 reset-names = "spi";
034d023f
SW		 637 dmas = <&apbdma 15>, <&apbdma 15>;
638 dma-names = "rx", "tx";
a86b0db3
LD		 639 status = "disabled";
640 };
641
642 spi@7000d600 {
643 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
644 reg = <0x7000d600 0x200>;
6cecf916 645 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 646 #address-cells = <1>;
647 #size-cells = <0>;
05849c93 648 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
3393d422
SW		 649 resets = <&tegra_car 44>;
650 reset-names = "spi";
034d023f
SW		 651 dmas = <&apbdma 16>, <&apbdma 16>;
652 dma-names = "rx", "tx";
a86b0db3
LD		 653 status = "disabled";
654 };
655
656 spi@7000d800 {
657 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d 658 reg = <0x7000d800 0x200>;
6cecf916 659 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 660 #address-cells = <1>;
661 #size-cells = <0>;
05849c93 662 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
3393d422
SW		 663 resets = <&tegra_car 46>;
664 reset-names = "spi";
034d023f
SW		 665 dmas = <&apbdma 17>, <&apbdma 17>;
666 dma-names = "rx", "tx";
a86b0db3
LD		 667 status = "disabled";
668 };
669
670 spi@7000da00 {
671 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
672 reg = <0x7000da00 0x200>;
6cecf916 673 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 674 #address-cells = <1>;
675 #size-cells = <0>;
05849c93 676 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
3393d422
SW		 677 resets = <&tegra_car 68>;
678 reset-names = "spi";
034d023f
SW		 679 dmas = <&apbdma 18>, <&apbdma 18>;
680 dma-names = "rx", "tx";
a86b0db3
LD		 681 status = "disabled";
682 };
683
684 spi@7000dc00 {
685 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
686 reg = <0x7000dc00 0x200>;
6cecf916 687 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 688 #address-cells = <1>;
689 #size-cells = <0>;
05849c93 690 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
3393d422
SW		 691 resets = <&tegra_car 104>;
692 reset-names = "spi";
034d023f
SW		 693 dmas = <&apbdma 27>, <&apbdma 27>;
694 dma-names = "rx", "tx";
a86b0db3
LD		 695 status = "disabled";
696 };
697
698 spi@7000de00 {
699 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
700 reg = <0x7000de00 0x200>;
6cecf916 701 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 702 #address-cells = <1>;
703 #size-cells = <0>;
05849c93 704 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
3393d422
SW		 705 resets = <&tegra_car 106>;
706 reset-names = "spi";
034d023f
SW		 707 dmas = <&apbdma 28>, <&apbdma 28>;
708 dma-names = "rx", "tx";
a86b0db3
LD		 709 status = "disabled";
710 };
711
58ecb23f 712 kbc@7000e200 {
699ed4b9
LD		 713 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
714 reg = <0x7000e200 0x100>;
6cecf916 715 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
05849c93 716 clocks = <&tegra_car TEGRA30_CLK_KBC>;
3393d422
SW		 717 resets = <&tegra_car 36>;
718 reset-names = "kbc";
699ed4b9
LD		 719 status = "disabled";
720 };
721
86614b5d 722 tegra_pmc: pmc@7000e400 {
2b84e53b 723 compatible = "nvidia,tegra30-pmc";
c04abb3a 724 reg = <0x7000e400 0x400>;
05849c93 725 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
7021d122 726 clock-names = "pclk", "clk32k_in";
86614b5d 727 #clock-cells = <1>;
c04abb3a
SW		 728 };
729
a9fe468f 730 mc: memory-controller@7000f000 {
c04abb3a 731 compatible = "nvidia,tegra30-mc";
a9fe468f
TR		 732 reg = <0x7000f000 0x400>;
733 clocks = <&tegra_car TEGRA30_CLK_MC>;
734 clock-names = "mc";
735
6cecf916 736 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a 737
a9fe468f 738 #iommu-cells = <1>;
d072094b 739 #reset-cells = <1>;
c3e00a0e 740 };
9ee6a5c4 741
3193a063
DO		 742 memory-controller@7000f400 {
743 compatible = "nvidia,tegra30-emc";
744 reg = <0x7000f400 0x400>;
745 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&tegra_car TEGRA30_CLK_EMC>;
747
748 nvidia,memory-controller = <&mc>;
749 };
750
155dfc7b
PDS		 751 fuse@7000f800 {
752 compatible = "nvidia,tegra30-efuse";
753 reg = <0x7000f800 0x400>;
754 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
755 clock-names = "fuse";
756 resets = <&tegra_car 39>;
757 reset-names = "fuse";
758 };
759
cbee2613
MZ		 760 hda@70030000 {
761 compatible = "nvidia,tegra30-hda";
762 reg = <0x70030000 0x10000>;
763 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&tegra_car TEGRA30_CLK_HDA>,
d8b316b2 765 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
cbee2613
MZ		 766 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
767 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
768 resets = <&tegra_car 125>, /* hda */
769 <&tegra_car 128>, /* hda2hdmi */
770 <&tegra_car 111>; /* hda2codec_2x */
771 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
772 status = "disabled";
773 };
774
58ecb23f 775 ahub@70080000 {
9ee6a5c4 776 compatible = "nvidia,tegra30-ahub";
9482a170
TR		 777 reg = <0x70080000 0x200>,
778 <0x70080200 0x100>;
6cecf916 779 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
05849c93 780 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
2bd541ff
SW		 781 <&tegra_car TEGRA30_CLK_APBIF>;
782 clock-names = "d_audio", "apbif";
3393d422
SW		 783 resets = <&tegra_car 106>, /* d_audio */
784 <&tegra_car 107>, /* apbif */
785 <&tegra_car 30>, /* i2s0 */
786 <&tegra_car 11>, /* i2s1 */
787 <&tegra_car 18>, /* i2s2 */
788 <&tegra_car 101>, /* i2s3 */
789 <&tegra_car 102>, /* i2s4 */
790 <&tegra_car 108>, /* dam0 */
791 <&tegra_car 109>, /* dam1 */
792 <&tegra_car 110>, /* dam2 */
793 <&tegra_car 10>; /* spdif */
794 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
795 "i2s3", "i2s4", "dam0", "dam1", "dam2",
796 "spdif";
034d023f
SW		 797 dmas = <&apbdma 1>, <&apbdma 1>,
798 <&apbdma 2>, <&apbdma 2>,
799 <&apbdma 3>, <&apbdma 3>,
800 <&apbdma 4>, <&apbdma 4>;
801 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
802 "rx3", "tx3";
9ee6a5c4
SW		 803 ranges;
804 #address-cells = <1>;
805 #size-cells = <1>;
806
807 tegra_i2s0: i2s@70080300 {
808 compatible = "nvidia,tegra30-i2s";
809 reg = <0x70080300 0x100>;
810 nvidia,ahub-cif-ids = <4 4>;
05849c93 811 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
3393d422
SW		 812 resets = <&tegra_car 30>;
813 reset-names = "i2s";
223ef78d 814 status = "disabled";
9ee6a5c4
SW		 815 };
816
817 tegra_i2s1: i2s@70080400 {
818 compatible = "nvidia,tegra30-i2s";
819 reg = <0x70080400 0x100>;
820 nvidia,ahub-cif-ids = <5 5>;
05849c93 821 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
3393d422
SW		 822 resets = <&tegra_car 11>;
823 reset-names = "i2s";
223ef78d 824 status = "disabled";
9ee6a5c4
SW		 825 };
826
827 tegra_i2s2: i2s@70080500 {
828 compatible = "nvidia,tegra30-i2s";
829 reg = <0x70080500 0x100>;
830 nvidia,ahub-cif-ids = <6 6>;
05849c93 831 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
3393d422
SW		 832 resets = <&tegra_car 18>;
833 reset-names = "i2s";
223ef78d 834 status = "disabled";
9ee6a5c4
SW		 835 };
836
837 tegra_i2s3: i2s@70080600 {
838 compatible = "nvidia,tegra30-i2s";
839 reg = <0x70080600 0x100>;
840 nvidia,ahub-cif-ids = <7 7>;
05849c93 841 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
3393d422
SW		 842 resets = <&tegra_car 101>;
843 reset-names = "i2s";
223ef78d 844 status = "disabled";
9ee6a5c4
SW		 845 };
846
847 tegra_i2s4: i2s@70080700 {
848 compatible = "nvidia,tegra30-i2s";
849 reg = <0x70080700 0x100>;
850 nvidia,ahub-cif-ids = <8 8>;
05849c93 851 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
3393d422
SW		 852 resets = <&tegra_car 102>;
853 reset-names = "i2s";
223ef78d 854 status = "disabled";
9ee6a5c4
SW		 855 };
856 };
7868a9bc 857
32c096c2 858 mmc@78000000 {
c04abb3a
SW		 859 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
860 reg = <0x78000000 0x200>;
6cecf916 861 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
05849c93 862 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
f538588b 863 clock-names = "sdhci";
3393d422
SW		 864 resets = <&tegra_car 14>;
865 reset-names = "sdhci";
223ef78d 866 status = "disabled";
7868a9bc 867 };
ecf43742 868
32c096c2 869 mmc@78000200 {
c04abb3a
SW		 870 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
871 reg = <0x78000200 0x200>;
6cecf916 872 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
05849c93 873 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
f538588b 874 clock-names = "sdhci";
3393d422
SW		 875 resets = <&tegra_car 9>;
876 reset-names = "sdhci";
223ef78d 877 status = "disabled";
ecf43742 878 };
54174a33 879
32c096c2 880 mmc@78000400 {
c04abb3a
SW		 881 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
882 reg = <0x78000400 0x200>;
6cecf916 883 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
05849c93 884 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
f538588b 885 clock-names = "sdhci";
3393d422
SW		 886 resets = <&tegra_car 69>;
887 reset-names = "sdhci";
223ef78d 888 status = "disabled";
c04abb3a
SW		 889 };
890
32c096c2 891 mmc@78000600 {
c04abb3a
SW		 892 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
893 reg = <0x78000600 0x200>;
6cecf916 894 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
05849c93 895 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
f538588b 896 clock-names = "sdhci";
3393d422
SW		 897 resets = <&tegra_car 15>;
898 reset-names = "sdhci";
223ef78d 899 status = "disabled";
c04abb3a
SW		 900 };
901
cc34c9f7
TT		 902 usb@7d000000 {
903 compatible = "nvidia,tegra30-ehci", "usb-ehci";
904 reg = <0x7d000000 0x4000>;
905 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
906 phy_type = "utmi";
907 clocks = <&tegra_car TEGRA30_CLK_USBD>;
3393d422
SW		 908 resets = <&tegra_car 22>;
909 reset-names = "usb";
cc34c9f7
TT		 910 nvidia,needs-double-reset;
911 nvidia,phy = <&phy1>;
912 status = "disabled";
913 };
914
915 phy1: usb-phy@7d000000 {
916 compatible = "nvidia,tegra30-usb-phy";
9482a170
TR		 917 reg = <0x7d000000 0x4000>,
918 <0x7d000000 0x4000>;
cc34c9f7
TT		 919 phy_type = "utmi";
920 clocks = <&tegra_car TEGRA30_CLK_USBD>,
921 <&tegra_car TEGRA30_CLK_PLL_U>,
922 <&tegra_car TEGRA30_CLK_USBD>;
923 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 924 resets = <&tegra_car 22>, <&tegra_car 22>;
925 reset-names = "usb", "utmi-pads";
4c0bb8ca 926 #phy-cells = <0>;
cc34c9f7
TT		 927 nvidia,hssync-start-delay = <9>;
928 nvidia,idle-wait-delay = <17>;
929 nvidia,elastic-limit = <16>;
930 nvidia,term-range-adj = <6>;
931 nvidia,xcvr-setup = <51>;
564706f6 932 nvidia,xcvr-setup-use-fuses;
cc34c9f7
TT		 933 nvidia,xcvr-lsfslew = <1>;
934 nvidia,xcvr-lsrslew = <1>;
935 nvidia,xcvr-hsslew = <32>;
936 nvidia,hssquelch-level = <2>;
937 nvidia,hsdiscon-level = <5>;
308efde2 938 nvidia,has-utmi-pad-registers;
cc34c9f7
TT		 939 status = "disabled";
940 };
941
942 usb@7d004000 {
943 compatible = "nvidia,tegra30-ehci", "usb-ehci";
944 reg = <0x7d004000 0x4000>;
945 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
fd6441ec 946 phy_type = "utmi";
cc34c9f7 947 clocks = <&tegra_car TEGRA30_CLK_USB2>;
3393d422
SW		 948 resets = <&tegra_car 58>;
949 reset-names = "usb";
cc34c9f7
TT		 950 nvidia,phy = <&phy2>;
951 status = "disabled";
952 };
953
954 phy2: usb-phy@7d004000 {
955 compatible = "nvidia,tegra30-usb-phy";
9482a170
TR		 956 reg = <0x7d004000 0x4000>,
957 <0x7d000000 0x4000>;
fd6441ec 958 phy_type = "utmi";
cc34c9f7
TT		 959 clocks = <&tegra_car TEGRA30_CLK_USB2>,
960 <&tegra_car TEGRA30_CLK_PLL_U>,
fd6441ec
EB		 961 <&tegra_car TEGRA30_CLK_USBD>;
962 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 963 resets = <&tegra_car 58>, <&tegra_car 22>;
964 reset-names = "usb", "utmi-pads";
4c0bb8ca 965 #phy-cells = <0>;
fd6441ec
EB		 966 nvidia,hssync-start-delay = <9>;
967 nvidia,idle-wait-delay = <17>;
968 nvidia,elastic-limit = <16>;
969 nvidia,term-range-adj = <6>;
970 nvidia,xcvr-setup = <51>;
564706f6 971 nvidia,xcvr-setup-use-fuses;
fd6441ec
EB		 972 nvidia,xcvr-lsfslew = <2>;
973 nvidia,xcvr-lsrslew = <2>;
974 nvidia,xcvr-hsslew = <32>;
975 nvidia,hssquelch-level = <2>;
976 nvidia,hsdiscon-level = <5>;
cc34c9f7
TT		 977 status = "disabled";
978 };
979
980 usb@7d008000 {
981 compatible = "nvidia,tegra30-ehci", "usb-ehci";
982 reg = <0x7d008000 0x4000>;
983 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
984 phy_type = "utmi";
985 clocks = <&tegra_car TEGRA30_CLK_USB3>;
3393d422
SW		 986 resets = <&tegra_car 59>;
987 reset-names = "usb";
cc34c9f7
TT		 988 nvidia,phy = <&phy3>;
989 status = "disabled";
990 };
991
992 phy3: usb-phy@7d008000 {
993 compatible = "nvidia,tegra30-usb-phy";
9482a170
TR		 994 reg = <0x7d008000 0x4000>,
995 <0x7d000000 0x4000>;
cc34c9f7
TT		 996 phy_type = "utmi";
997 clocks = <&tegra_car TEGRA30_CLK_USB3>,
998 <&tegra_car TEGRA30_CLK_PLL_U>,
999 <&tegra_car TEGRA30_CLK_USBD>;
1000 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 1001 resets = <&tegra_car 59>, <&tegra_car 22>;
1002 reset-names = "usb", "utmi-pads";
4c0bb8ca 1003 #phy-cells = <0>;
cc34c9f7
TT		 1004 nvidia,hssync-start-delay = <0>;
1005 nvidia,idle-wait-delay = <17>;
1006 nvidia,elastic-limit = <16>;
1007 nvidia,term-range-adj = <6>;
1008 nvidia,xcvr-setup = <51>;
564706f6 1009 nvidia,xcvr-setup-use-fuses;
cc34c9f7
TT		 1010 nvidia,xcvr-lsfslew = <2>;
1011 nvidia,xcvr-lsrslew = <2>;
1012 nvidia,xcvr-hsslew = <32>;
1013 nvidia,hssquelch-level = <2>;
1014 nvidia,hsdiscon-level = <5>;
1015 status = "disabled";
1016 };
1017
7d19a34a
HD		 1018 cpus {
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021
1022 cpu@0 {
1023 device_type = "cpu";
1024 compatible = "arm,cortex-a9";
1025 reg = <0>;
663bd487 1026 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
7d19a34a
HD		 1027 };
1028
1029 cpu@1 {
1030 device_type = "cpu";
1031 compatible = "arm,cortex-a9";
1032 reg = <1>;
663bd487 1033 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
7d19a34a
HD		 1034 };
1035
1036 cpu@2 {
1037 device_type = "cpu";
1038 compatible = "arm,cortex-a9";
1039 reg = <2>;
663bd487 1040 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
7d19a34a
HD		 1041 };
1042
1043 cpu@3 {
1044 device_type = "cpu";
1045 compatible = "arm,cortex-a9";
1046 reg = <3>;
663bd487 1047 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
7d19a34a
HD		 1048 };
1049 };
1050
c04abb3a
SW		 1051 pmu {
1052 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 1053 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1054 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1055 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
2db12b16
MZ		 1057 interrupt-affinity = <&{/cpus/cpu@0}>,
1058 <&{/cpus/cpu@1}>,
1059 <&{/cpus/cpu@2}>,
1060 <&{/cpus/cpu@3}>;
54174a33 1061 };
c3e00a0e 1062};
Linux 6.x block layer and io_uring tree(s)