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ARM: tegra: Add IRAM node on Tegra30
[linux-2.6-block.git] / arch / arm / boot / dts / tegra30.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
05849c93 2#include <dt-bindings/clock/tegra30-car.h>
3325f1bc 3#include <dt-bindings/gpio/tegra-gpio.h>
6d9adf6f 4#include <dt-bindings/memory/tegra30-mc.h>
a47c662a 5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 6#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 7
1bd0bd49 8#include "skeleton.dtsi"
c3e00a0e
PDS		 9
10/ {
11 compatible = "nvidia,tegra30";
870c81a4 12 interrupt-parent = <&lic>;
c3e00a0e 13
508d690e 14 pcie@3000 {
e07e3dbd
TR		 15 compatible = "nvidia,tegra30-pcie";
16 device_type = "pci";
17 reg = <0x00003000 0x00000800 /* PADS registers */
18 0x00003800 0x00000200 /* AFI registers */
19 0x10000000 0x10000000>; /* configuration space */
20 reg-names = "pads", "afi", "cs";
21 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
22 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
23 interrupt-names = "intr", "msi";
24
97070bd4
LS		 25 #interrupt-cells = <1>;
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28
e07e3dbd
TR		 29 bus-range = <0x00 0xff>;
30 #address-cells = <3>;
31 #size-cells = <2>;
32
33 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
35 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
36 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 37 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
38 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
e07e3dbd
TR		 39
40 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
41 <&tegra_car TEGRA30_CLK_AFI>,
e07e3dbd
TR		 42 <&tegra_car TEGRA30_CLK_PLL_E>,
43 <&tegra_car TEGRA30_CLK_CML0>;
2bd541ff 44 clock-names = "pex", "afi", "pll_e", "cml";
3393d422 45 resets = <&tegra_car 70>,
d8b316b2
MZ		 46 <&tegra_car 72>,
47 <&tegra_car 74>;
3393d422 48 reset-names = "pex", "afi", "pcie_x";
e07e3dbd
TR		 49 status = "disabled";
50
51 pci@1,0 {
52 device_type = "pci";
53 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
54 reg = <0x000800 0 0 0 0>;
508d690e 55 bus-range = <0x00 0xff>;
e07e3dbd
TR		 56 status = "disabled";
57
58 #address-cells = <3>;
59 #size-cells = <2>;
60 ranges;
61
62 nvidia,num-lanes = <2>;
63 };
64
65 pci@2,0 {
66 device_type = "pci";
67 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
68 reg = <0x001000 0 0 0 0>;
508d690e 69 bus-range = <0x00 0xff>;
e07e3dbd
TR		 70 status = "disabled";
71
72 #address-cells = <3>;
73 #size-cells = <2>;
74 ranges;
75
76 nvidia,num-lanes = <2>;
77 };
78
79 pci@3,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
82 reg = <0x001800 0 0 0 0>;
508d690e 83 bus-range = <0x00 0xff>;
e07e3dbd
TR		 84 status = "disabled";
85
86 #address-cells = <3>;
87 #size-cells = <2>;
88 ranges;
89
90 nvidia,num-lanes = <2>;
91 };
92 };
93
ea857036
DO		 94 iram@40000000 {
95 compatible = "mmio-sram";
96 reg = <0x40000000 0x40000>;
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges = <0 0x40000000 0x40000>;
100 };
101
58ecb23f 102 host1x@50000000 {
ed39097c
TR		 103 compatible = "nvidia,tegra30-host1x", "simple-bus";
104 reg = <0x50000000 0x00024000>;
6cecf916
SW		 105 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
106 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
05849c93 107 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
3393d422
SW		 108 resets = <&tegra_car 28>;
109 reset-names = "host1x";
ed39097c
TR		 110
111 #address-cells = <1>;
112 #size-cells = <1>;
113
114 ranges = <0x54000000 0x54000000 0x04000000>;
115
58ecb23f 116 mpe@54040000 {
ed39097c
TR		 117 compatible = "nvidia,tegra30-mpe";
118 reg = <0x54040000 0x00040000>;
6cecf916 119 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
05849c93 120 clocks = <&tegra_car TEGRA30_CLK_MPE>;
3393d422
SW		 121 resets = <&tegra_car 60>;
122 reset-names = "mpe";
ed39097c
TR		 123 };
124
58ecb23f 125 vi@54080000 {
ed39097c
TR		 126 compatible = "nvidia,tegra30-vi";
127 reg = <0x54080000 0x00040000>;
6cecf916 128 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
05849c93 129 clocks = <&tegra_car TEGRA30_CLK_VI>;
3393d422
SW		 130 resets = <&tegra_car 20>;
131 reset-names = "vi";
ed39097c
TR		 132 };
133
58ecb23f 134 epp@540c0000 {
ed39097c
TR		 135 compatible = "nvidia,tegra30-epp";
136 reg = <0x540c0000 0x00040000>;
6cecf916 137 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
05849c93 138 clocks = <&tegra_car TEGRA30_CLK_EPP>;
3393d422
SW		 139 resets = <&tegra_car 19>;
140 reset-names = "epp";
ed39097c
TR		 141 };
142
58ecb23f 143 isp@54100000 {
ed39097c
TR		 144 compatible = "nvidia,tegra30-isp";
145 reg = <0x54100000 0x00040000>;
6cecf916 146 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
05849c93 147 clocks = <&tegra_car TEGRA30_CLK_ISP>;
3393d422
SW		 148 resets = <&tegra_car 23>;
149 reset-names = "isp";
ed39097c
TR		 150 };
151
58ecb23f 152 gr2d@54140000 {
ed39097c
TR		 153 compatible = "nvidia,tegra30-gr2d";
154 reg = <0x54140000 0x00040000>;
6cecf916 155 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
da45d738 156 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
3393d422
SW		 157 resets = <&tegra_car 21>;
158 reset-names = "2d";
ed39097c
TR		 159 };
160
58ecb23f 161 gr3d@54180000 {
ed39097c
TR		 162 compatible = "nvidia,tegra30-gr3d";
163 reg = <0x54180000 0x00040000>;
c71d3909
TR		 164 clocks = <&tegra_car TEGRA30_CLK_GR3D
165 &tegra_car TEGRA30_CLK_GR3D2>;
1cbc733d 166 clock-names = "3d", "3d2";
3393d422 167 resets = <&tegra_car 24>,
d8b316b2 168 <&tegra_car 98>;
3393d422 169 reset-names = "3d", "3d2";
ed39097c
TR		 170 };
171
172 dc@54200000 {
05465f4e 173 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
ed39097c 174 reg = <0x54200000 0x00040000>;
6cecf916 175 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 176 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
177 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 178 clock-names = "dc", "parent";
3393d422
SW		 179 resets = <&tegra_car 27>;
180 reset-names = "dc";
ed39097c 181
6d9adf6f
TR		 182 iommus = <&mc TEGRA_SWGROUP_DC>;
183
688b56b4
TR		 184 nvidia,head = <0>;
185
ed39097c
TR		 186 rgb {
187 status = "disabled";
188 };
189 };
190
191 dc@54240000 {
192 compatible = "nvidia,tegra30-dc";
193 reg = <0x54240000 0x00040000>;
6cecf916 194 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 195 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
196 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 197 clock-names = "dc", "parent";
3393d422
SW		 198 resets = <&tegra_car 26>;
199 reset-names = "dc";
ed39097c 200
6d9adf6f
TR		 201 iommus = <&mc TEGRA_SWGROUP_DCB>;
202
688b56b4
TR		 203 nvidia,head = <1>;
204
ed39097c
TR		 205 rgb {
206 status = "disabled";
207 };
208 };
209
58ecb23f 210 hdmi@54280000 {
ed39097c
TR		 211 compatible = "nvidia,tegra30-hdmi";
212 reg = <0x54280000 0x00040000>;
6cecf916 213 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 214 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
215 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
1cbc733d 216 clock-names = "hdmi", "parent";
3393d422
SW		 217 resets = <&tegra_car 51>;
218 reset-names = "hdmi";
ed39097c
TR		 219 status = "disabled";
220 };
221
58ecb23f 222 tvo@542c0000 {
ed39097c
TR		 223 compatible = "nvidia,tegra30-tvo";
224 reg = <0x542c0000 0x00040000>;
6cecf916 225 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
05849c93 226 clocks = <&tegra_car TEGRA30_CLK_TVO>;
ed39097c
TR		 227 status = "disabled";
228 };
229
58ecb23f 230 dsi@54300000 {
ed39097c
TR		 231 compatible = "nvidia,tegra30-dsi";
232 reg = <0x54300000 0x00040000>;
05849c93 233 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
3393d422
SW		 234 resets = <&tegra_car 48>;
235 reset-names = "dsi";
ed39097c
TR		 236 status = "disabled";
237 };
238 };
239
2cda1880 240 timer@50040600 {
73368ba0
SW		 241 compatible = "arm,cortex-a9-twd-timer";
242 reg = <0x50040600 0x20>;
870c81a4 243 interrupt-parent = <&intc>;
6cecf916 244 interrupts = <GIC_PPI 13
e7d9b270 245 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
05849c93 246 clocks = <&tegra_car TEGRA30_CLK_TWD>;
73368ba0
SW		 247 };
248
58ecb23f 249 intc: interrupt-controller@50041000 {
c3e00a0e 250 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 251 reg = <0x50041000 0x1000
252 0x50040100 0x0100>;
2eaab06e
SW		 253 interrupt-controller;
254 #interrupt-cells = <3>;
870c81a4 255 interrupt-parent = <&intc>;
c3e00a0e
PDS		 256 };
257
58ecb23f 258 cache-controller@50043000 {
bb2c1de9
SW		 259 compatible = "arm,pl310-cache";
260 reg = <0x50043000 0x1000>;
261 arm,data-latency = <6 6 2>;
262 arm,tag-latency = <5 5 2>;
263 cache-unified;
264 cache-level = <2>;
265 };
266
870c81a4
MZ		 267 lic: interrupt-controller@60004000 {
268 compatible = "nvidia,tegra30-ictlr";
269 reg = <0x60004000 0x100>,
270 <0x60004100 0x50>,
271 <0x60004200 0x50>,
272 <0x60004300 0x50>,
273 <0x60004400 0x50>;
274 interrupt-controller;
275 #interrupt-cells = <3>;
276 interrupt-parent = <&intc>;
277 };
278
2f2b7fb2
SW		 279 timer@60005000 {
280 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
281 reg = <0x60005000 0x400>;
6cecf916
SW		 282 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
05849c93 288 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
2f2b7fb2
SW		 289 };
290
58ecb23f 291 tegra_car: clock@60006000 {
95985667
PG		 292 compatible = "nvidia,tegra30-car";
293 reg = <0x60006000 0x1000>;
294 #clock-cells = <1>;
3393d422 295 #reset-cells = <1>;
95985667
PG		 296 };
297
b1023134
TR		 298 flow-controller@60007000 {
299 compatible = "nvidia,tegra30-flowctrl";
300 reg = <0x60007000 0x1000>;
301 };
302
58ecb23f 303 apbdma: dma@6000a000 {
8051b75a
SW		 304 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
305 reg = <0x6000a000 0x1400>;
6cecf916
SW		 306 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
05849c93 338 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
3393d422
SW		 339 resets = <&tegra_car 34>;
340 reset-names = "dma";
034d023f 341 #dma-cells = <1>;
8051b75a
SW		 342 };
343
0d5ccb38 344 ahb: ahb@6000c000 {
c04abb3a 345 compatible = "nvidia,tegra30-ahb";
0d5ccb38 346 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e
PDS		 347 };
348
58ecb23f 349 gpio: gpio@6000d000 {
35f210ec 350 compatible = "nvidia,tegra30-gpio";
95decf84 351 reg = <0x6000d000 0x1000>;
6cecf916
SW		 352 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e
PDS		 360 #gpio-cells = <2>;
361 gpio-controller;
6f74dc9b
SW		 362 #interrupt-cells = <2>;
363 interrupt-controller;
4f1d8414 364 /*
17cdddf0 365 gpio-ranges = <&pinmux 0 0 248>;
4f1d8414 366 */
c3e00a0e
PDS		 367 };
368
155dfc7b
PDS		 369 apbmisc@70000800 {
370 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
371 reg = <0x70000800 0x64 /* Chip revision */
372 0x70000008 0x04>; /* Strapping options */
373 };
374
58ecb23f 375 pinmux: pinmux@70000868 {
c04abb3a 376 compatible = "nvidia,tegra30-pinmux";
322337b8
PR		 377 reg = <0x70000868 0xd4 /* Pad control registers */
378 0x70003000 0x3e4>; /* Mux registers */
c04abb3a
SW		 379 };
380
b6551bb9
LD		 381 /*
382 * There are two serial driver i.e. 8250 based simple serial
383 * driver and APB DMA based serial driver for higher baudrate
384 * and performace. To enable the 8250 based driver, the compatible
385 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
e1098248 386 * the APB DMA based serial driver, the compatible is
b6551bb9
LD		 387 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
388 */
389 uarta: serial@70006000 {
c3e00a0e
PDS		 390 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
391 reg = <0x70006000 0x40>;
392 reg-shift = <2>;
6cecf916 393 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
05849c93 394 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
3393d422
SW		 395 resets = <&tegra_car 6>;
396 reset-names = "serial";
034d023f
SW		 397 dmas = <&apbdma 8>, <&apbdma 8>;
398 dma-names = "rx", "tx";
223ef78d 399 status = "disabled";
c3e00a0e
PDS		 400 };
401
b6551bb9 402 uartb: serial@70006040 {
c3e00a0e
PDS		 403 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
404 reg = <0x70006040 0x40>;
405 reg-shift = <2>;
6cecf916 406 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
05849c93 407 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
3393d422
SW		 408 resets = <&tegra_car 7>;
409 reset-names = "serial";
034d023f
SW		 410 dmas = <&apbdma 9>, <&apbdma 9>;
411 dma-names = "rx", "tx";
223ef78d 412 status = "disabled";
c3e00a0e
PDS		 413 };
414
b6551bb9 415 uartc: serial@70006200 {
c3e00a0e
PDS		 416 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
417 reg = <0x70006200 0x100>;
418 reg-shift = <2>;
6cecf916 419 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
05849c93 420 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
3393d422
SW		 421 resets = <&tegra_car 55>;
422 reset-names = "serial";
034d023f
SW		 423 dmas = <&apbdma 10>, <&apbdma 10>;
424 dma-names = "rx", "tx";
223ef78d 425 status = "disabled";
c3e00a0e
PDS		 426 };
427
b6551bb9 428 uartd: serial@70006300 {
c3e00a0e
PDS		 429 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
430 reg = <0x70006300 0x100>;
431 reg-shift = <2>;
6cecf916 432 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
05849c93 433 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
3393d422
SW		 434 resets = <&tegra_car 65>;
435 reset-names = "serial";
034d023f
SW		 436 dmas = <&apbdma 19>, <&apbdma 19>;
437 dma-names = "rx", "tx";
223ef78d 438 status = "disabled";
c3e00a0e
PDS		 439 };
440
b6551bb9 441 uarte: serial@70006400 {
c3e00a0e
PDS		 442 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
443 reg = <0x70006400 0x100>;
444 reg-shift = <2>;
6cecf916 445 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
05849c93 446 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
3393d422
SW		 447 resets = <&tegra_car 66>;
448 reset-names = "serial";
034d023f
SW		 449 dmas = <&apbdma 20>, <&apbdma 20>;
450 dma-names = "rx", "tx";
223ef78d 451 status = "disabled";
c3e00a0e
PDS		 452 };
453
5e35c1f0
MK		 454 gmi@70009000 {
455 compatible = "nvidia,tegra30-gmi";
456 reg = <0x70009000 0x1000>;
457 #address-cells = <2>;
458 #size-cells = <1>;
459 ranges = <0 0 0x48000000 0x7ffffff>;
460 clocks = <&tegra_car TEGRA30_CLK_NOR>;
461 clock-names = "gmi";
462 resets = <&tegra_car 42>;
463 reset-names = "gmi";
464 status = "disabled";
465 };
466
58ecb23f 467 pwm: pwm@7000a000 {
140fd977
TR		 468 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
469 reg = <0x7000a000 0x100>;
470 #pwm-cells = <2>;
05849c93 471 clocks = <&tegra_car TEGRA30_CLK_PWM>;
3393d422
SW		 472 resets = <&tegra_car 17>;
473 reset-names = "pwm";
b69cd984 474 status = "disabled";
140fd977
TR		 475 };
476
58ecb23f 477 rtc@7000e000 {
380e04ac
SW		 478 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
479 reg = <0x7000e000 0x100>;
6cecf916 480 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
05849c93 481 clocks = <&tegra_car TEGRA30_CLK_RTC>;
380e04ac
SW		 482 };
483
c04abb3a 484 i2c@7000c000 {
d8b316b2 485 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a 486 reg = <0x7000c000 0x100>;
6cecf916 487 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 488 #address-cells = <1>;
489 #size-cells = <0>;
05849c93
HD		 490 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
491 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 492 clock-names = "div-clk", "fast-clk";
3393d422
SW		 493 resets = <&tegra_car 12>;
494 reset-names = "i2c";
034d023f
SW		 495 dmas = <&apbdma 21>, <&apbdma 21>;
496 dma-names = "rx", "tx";
223ef78d 497 status = "disabled";
c3e00a0e
PDS		 498 };
499
c04abb3a 500 i2c@7000c400 {
c04abb3a
SW		 501 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
502 reg = <0x7000c400 0x100>;
6cecf916 503 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 504 #address-cells = <1>;
505 #size-cells = <0>;
05849c93
HD		 506 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
507 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 508 clock-names = "div-clk", "fast-clk";
3393d422
SW		 509 resets = <&tegra_car 54>;
510 reset-names = "i2c";
034d023f
SW		 511 dmas = <&apbdma 22>, <&apbdma 22>;
512 dma-names = "rx", "tx";
223ef78d 513 status = "disabled";
c3e00a0e
PDS		 514 };
515
c04abb3a 516 i2c@7000c500 {
c04abb3a
SW		 517 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
518 reg = <0x7000c500 0x100>;
6cecf916 519 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 520 #address-cells = <1>;
521 #size-cells = <0>;
05849c93
HD		 522 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
523 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 524 clock-names = "div-clk", "fast-clk";
3393d422
SW		 525 resets = <&tegra_car 67>;
526 reset-names = "i2c";
034d023f
SW		 527 dmas = <&apbdma 23>, <&apbdma 23>;
528 dma-names = "rx", "tx";
223ef78d 529 status = "disabled";
c3e00a0e
PDS		 530 };
531
c04abb3a 532 i2c@7000c700 {
c04abb3a
SW		 533 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
534 reg = <0x7000c700 0x100>;
6cecf916 535 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 536 #address-cells = <1>;
537 #size-cells = <0>;
05849c93
HD		 538 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
539 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
3393d422
SW		 540 resets = <&tegra_car 103>;
541 reset-names = "i2c";
1cbc733d 542 clock-names = "div-clk", "fast-clk";
034d023f
SW		 543 dmas = <&apbdma 26>, <&apbdma 26>;
544 dma-names = "rx", "tx";
223ef78d 545 status = "disabled";
c3e00a0e
PDS		 546 };
547
c04abb3a 548 i2c@7000d000 {
c04abb3a
SW		 549 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
550 reg = <0x7000d000 0x100>;
6cecf916 551 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 552 #address-cells = <1>;
553 #size-cells = <0>;
05849c93
HD		 554 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
555 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 556 clock-names = "div-clk", "fast-clk";
3393d422
SW		 557 resets = <&tegra_car 47>;
558 reset-names = "i2c";
034d023f
SW		 559 dmas = <&apbdma 24>, <&apbdma 24>;
560 dma-names = "rx", "tx";
223ef78d 561 status = "disabled";
c04abb3a
SW		 562 };
563
a86b0db3
LD		 564 spi@7000d400 {
565 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
566 reg = <0x7000d400 0x200>;
6cecf916 567 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 568 #address-cells = <1>;
569 #size-cells = <0>;
05849c93 570 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
3393d422
SW		 571 resets = <&tegra_car 41>;
572 reset-names = "spi";
034d023f
SW		 573 dmas = <&apbdma 15>, <&apbdma 15>;
574 dma-names = "rx", "tx";
a86b0db3
LD		 575 status = "disabled";
576 };
577
578 spi@7000d600 {
579 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
580 reg = <0x7000d600 0x200>;
6cecf916 581 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 582 #address-cells = <1>;
583 #size-cells = <0>;
05849c93 584 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
3393d422
SW		 585 resets = <&tegra_car 44>;
586 reset-names = "spi";
034d023f
SW		 587 dmas = <&apbdma 16>, <&apbdma 16>;
588 dma-names = "rx", "tx";
a86b0db3
LD		 589 status = "disabled";
590 };
591
592 spi@7000d800 {
593 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d 594 reg = <0x7000d800 0x200>;
6cecf916 595 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 596 #address-cells = <1>;
597 #size-cells = <0>;
05849c93 598 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
3393d422
SW		 599 resets = <&tegra_car 46>;
600 reset-names = "spi";
034d023f
SW		 601 dmas = <&apbdma 17>, <&apbdma 17>;
602 dma-names = "rx", "tx";
a86b0db3
LD		 603 status = "disabled";
604 };
605
606 spi@7000da00 {
607 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
608 reg = <0x7000da00 0x200>;
6cecf916 609 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 610 #address-cells = <1>;
611 #size-cells = <0>;
05849c93 612 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
3393d422
SW		 613 resets = <&tegra_car 68>;
614 reset-names = "spi";
034d023f
SW		 615 dmas = <&apbdma 18>, <&apbdma 18>;
616 dma-names = "rx", "tx";
a86b0db3
LD		 617 status = "disabled";
618 };
619
620 spi@7000dc00 {
621 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
622 reg = <0x7000dc00 0x200>;
6cecf916 623 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 624 #address-cells = <1>;
625 #size-cells = <0>;
05849c93 626 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
3393d422
SW		 627 resets = <&tegra_car 104>;
628 reset-names = "spi";
034d023f
SW		 629 dmas = <&apbdma 27>, <&apbdma 27>;
630 dma-names = "rx", "tx";
a86b0db3
LD		 631 status = "disabled";
632 };
633
634 spi@7000de00 {
635 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
636 reg = <0x7000de00 0x200>;
6cecf916 637 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 638 #address-cells = <1>;
639 #size-cells = <0>;
05849c93 640 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
3393d422
SW		 641 resets = <&tegra_car 106>;
642 reset-names = "spi";
034d023f
SW		 643 dmas = <&apbdma 28>, <&apbdma 28>;
644 dma-names = "rx", "tx";
a86b0db3
LD		 645 status = "disabled";
646 };
647
58ecb23f 648 kbc@7000e200 {
699ed4b9
LD		 649 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
650 reg = <0x7000e200 0x100>;
6cecf916 651 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
05849c93 652 clocks = <&tegra_car TEGRA30_CLK_KBC>;
3393d422
SW		 653 resets = <&tegra_car 36>;
654 reset-names = "kbc";
699ed4b9
LD		 655 status = "disabled";
656 };
657
58ecb23f 658 pmc@7000e400 {
2b84e53b 659 compatible = "nvidia,tegra30-pmc";
c04abb3a 660 reg = <0x7000e400 0x400>;
05849c93 661 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
7021d122 662 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 663 };
664
a9fe468f 665 mc: memory-controller@7000f000 {
c04abb3a 666 compatible = "nvidia,tegra30-mc";
a9fe468f
TR		 667 reg = <0x7000f000 0x400>;
668 clocks = <&tegra_car TEGRA30_CLK_MC>;
669 clock-names = "mc";
670
6cecf916 671 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a 672
a9fe468f 673 #iommu-cells = <1>;
c3e00a0e 674 };
9ee6a5c4 675
155dfc7b
PDS		 676 fuse@7000f800 {
677 compatible = "nvidia,tegra30-efuse";
678 reg = <0x7000f800 0x400>;
679 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
680 clock-names = "fuse";
681 resets = <&tegra_car 39>;
682 reset-names = "fuse";
683 };
684
cbee2613
MZ		 685 hda@70030000 {
686 compatible = "nvidia,tegra30-hda";
687 reg = <0x70030000 0x10000>;
688 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&tegra_car TEGRA30_CLK_HDA>,
d8b316b2 690 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
cbee2613
MZ		 691 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
692 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
693 resets = <&tegra_car 125>, /* hda */
694 <&tegra_car 128>, /* hda2hdmi */
695 <&tegra_car 111>; /* hda2codec_2x */
696 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
697 status = "disabled";
698 };
699
58ecb23f 700 ahub@70080000 {
9ee6a5c4 701 compatible = "nvidia,tegra30-ahub";
5ff48887
SW		 702 reg = <0x70080000 0x200
703 0x70080200 0x100>;
6cecf916 704 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
05849c93 705 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
2bd541ff
SW		 706 <&tegra_car TEGRA30_CLK_APBIF>;
707 clock-names = "d_audio", "apbif";
3393d422
SW		 708 resets = <&tegra_car 106>, /* d_audio */
709 <&tegra_car 107>, /* apbif */
710 <&tegra_car 30>, /* i2s0 */
711 <&tegra_car 11>, /* i2s1 */
712 <&tegra_car 18>, /* i2s2 */
713 <&tegra_car 101>, /* i2s3 */
714 <&tegra_car 102>, /* i2s4 */
715 <&tegra_car 108>, /* dam0 */
716 <&tegra_car 109>, /* dam1 */
717 <&tegra_car 110>, /* dam2 */
718 <&tegra_car 10>; /* spdif */
719 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
720 "i2s3", "i2s4", "dam0", "dam1", "dam2",
721 "spdif";
034d023f
SW		 722 dmas = <&apbdma 1>, <&apbdma 1>,
723 <&apbdma 2>, <&apbdma 2>,
724 <&apbdma 3>, <&apbdma 3>,
725 <&apbdma 4>, <&apbdma 4>;
726 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
727 "rx3", "tx3";
9ee6a5c4
SW		 728 ranges;
729 #address-cells = <1>;
730 #size-cells = <1>;
731
732 tegra_i2s0: i2s@70080300 {
733 compatible = "nvidia,tegra30-i2s";
734 reg = <0x70080300 0x100>;
735 nvidia,ahub-cif-ids = <4 4>;
05849c93 736 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
3393d422
SW		 737 resets = <&tegra_car 30>;
738 reset-names = "i2s";
223ef78d 739 status = "disabled";
9ee6a5c4
SW		 740 };
741
742 tegra_i2s1: i2s@70080400 {
743 compatible = "nvidia,tegra30-i2s";
744 reg = <0x70080400 0x100>;
745 nvidia,ahub-cif-ids = <5 5>;
05849c93 746 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
3393d422
SW		 747 resets = <&tegra_car 11>;
748 reset-names = "i2s";
223ef78d 749 status = "disabled";
9ee6a5c4
SW		 750 };
751
752 tegra_i2s2: i2s@70080500 {
753 compatible = "nvidia,tegra30-i2s";
754 reg = <0x70080500 0x100>;
755 nvidia,ahub-cif-ids = <6 6>;
05849c93 756 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
3393d422
SW		 757 resets = <&tegra_car 18>;
758 reset-names = "i2s";
223ef78d 759 status = "disabled";
9ee6a5c4
SW		 760 };
761
762 tegra_i2s3: i2s@70080600 {
763 compatible = "nvidia,tegra30-i2s";
764 reg = <0x70080600 0x100>;
765 nvidia,ahub-cif-ids = <7 7>;
05849c93 766 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
3393d422
SW		 767 resets = <&tegra_car 101>;
768 reset-names = "i2s";
223ef78d 769 status = "disabled";
9ee6a5c4
SW		 770 };
771
772 tegra_i2s4: i2s@70080700 {
773 compatible = "nvidia,tegra30-i2s";
774 reg = <0x70080700 0x100>;
775 nvidia,ahub-cif-ids = <8 8>;
05849c93 776 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
3393d422
SW		 777 resets = <&tegra_car 102>;
778 reset-names = "i2s";
223ef78d 779 status = "disabled";
9ee6a5c4
SW		 780 };
781 };
7868a9bc 782
c04abb3a
SW		 783 sdhci@78000000 {
784 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
785 reg = <0x78000000 0x200>;
6cecf916 786 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
05849c93 787 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
3393d422
SW		 788 resets = <&tegra_car 14>;
789 reset-names = "sdhci";
223ef78d 790 status = "disabled";
7868a9bc 791 };
ecf43742 792
c04abb3a
SW		 793 sdhci@78000200 {
794 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
795 reg = <0x78000200 0x200>;
6cecf916 796 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
05849c93 797 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
3393d422
SW		 798 resets = <&tegra_car 9>;
799 reset-names = "sdhci";
223ef78d 800 status = "disabled";
ecf43742 801 };
54174a33 802
c04abb3a
SW		 803 sdhci@78000400 {
804 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
805 reg = <0x78000400 0x200>;
6cecf916 806 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
05849c93 807 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
3393d422
SW		 808 resets = <&tegra_car 69>;
809 reset-names = "sdhci";
223ef78d 810 status = "disabled";
c04abb3a
SW		 811 };
812
813 sdhci@78000600 {
814 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
815 reg = <0x78000600 0x200>;
6cecf916 816 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
05849c93 817 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
3393d422
SW		 818 resets = <&tegra_car 15>;
819 reset-names = "sdhci";
223ef78d 820 status = "disabled";
c04abb3a
SW		 821 };
822
cc34c9f7
TT		 823 usb@7d000000 {
824 compatible = "nvidia,tegra30-ehci", "usb-ehci";
825 reg = <0x7d000000 0x4000>;
826 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
827 phy_type = "utmi";
828 clocks = <&tegra_car TEGRA30_CLK_USBD>;
3393d422
SW		 829 resets = <&tegra_car 22>;
830 reset-names = "usb";
cc34c9f7
TT		 831 nvidia,needs-double-reset;
832 nvidia,phy = <&phy1>;
833 status = "disabled";
834 };
835
836 phy1: usb-phy@7d000000 {
837 compatible = "nvidia,tegra30-usb-phy";
838 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
839 phy_type = "utmi";
840 clocks = <&tegra_car TEGRA30_CLK_USBD>,
841 <&tegra_car TEGRA30_CLK_PLL_U>,
842 <&tegra_car TEGRA30_CLK_USBD>;
843 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 844 resets = <&tegra_car 22>, <&tegra_car 22>;
845 reset-names = "usb", "utmi-pads";
cc34c9f7
TT		 846 nvidia,hssync-start-delay = <9>;
847 nvidia,idle-wait-delay = <17>;
848 nvidia,elastic-limit = <16>;
849 nvidia,term-range-adj = <6>;
850 nvidia,xcvr-setup = <51>;
851 nvidia.xcvr-setup-use-fuses;
852 nvidia,xcvr-lsfslew = <1>;
853 nvidia,xcvr-lsrslew = <1>;
854 nvidia,xcvr-hsslew = <32>;
855 nvidia,hssquelch-level = <2>;
856 nvidia,hsdiscon-level = <5>;
308efde2 857 nvidia,has-utmi-pad-registers;
cc34c9f7
TT		 858 status = "disabled";
859 };
860
861 usb@7d004000 {
862 compatible = "nvidia,tegra30-ehci", "usb-ehci";
863 reg = <0x7d004000 0x4000>;
864 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
fd6441ec 865 phy_type = "utmi";
cc34c9f7 866 clocks = <&tegra_car TEGRA30_CLK_USB2>;
3393d422
SW		 867 resets = <&tegra_car 58>;
868 reset-names = "usb";
cc34c9f7
TT		 869 nvidia,phy = <&phy2>;
870 status = "disabled";
871 };
872
873 phy2: usb-phy@7d004000 {
874 compatible = "nvidia,tegra30-usb-phy";
fd6441ec
EB		 875 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
876 phy_type = "utmi";
cc34c9f7
TT		 877 clocks = <&tegra_car TEGRA30_CLK_USB2>,
878 <&tegra_car TEGRA30_CLK_PLL_U>,
fd6441ec
EB		 879 <&tegra_car TEGRA30_CLK_USBD>;
880 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 881 resets = <&tegra_car 58>, <&tegra_car 22>;
882 reset-names = "usb", "utmi-pads";
fd6441ec
EB		 883 nvidia,hssync-start-delay = <9>;
884 nvidia,idle-wait-delay = <17>;
885 nvidia,elastic-limit = <16>;
886 nvidia,term-range-adj = <6>;
887 nvidia,xcvr-setup = <51>;
888 nvidia.xcvr-setup-use-fuses;
889 nvidia,xcvr-lsfslew = <2>;
890 nvidia,xcvr-lsrslew = <2>;
891 nvidia,xcvr-hsslew = <32>;
892 nvidia,hssquelch-level = <2>;
893 nvidia,hsdiscon-level = <5>;
cc34c9f7
TT		 894 status = "disabled";
895 };
896
897 usb@7d008000 {
898 compatible = "nvidia,tegra30-ehci", "usb-ehci";
899 reg = <0x7d008000 0x4000>;
900 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
901 phy_type = "utmi";
902 clocks = <&tegra_car TEGRA30_CLK_USB3>;
3393d422
SW		 903 resets = <&tegra_car 59>;
904 reset-names = "usb";
cc34c9f7
TT		 905 nvidia,phy = <&phy3>;
906 status = "disabled";
907 };
908
909 phy3: usb-phy@7d008000 {
910 compatible = "nvidia,tegra30-usb-phy";
911 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
912 phy_type = "utmi";
913 clocks = <&tegra_car TEGRA30_CLK_USB3>,
914 <&tegra_car TEGRA30_CLK_PLL_U>,
915 <&tegra_car TEGRA30_CLK_USBD>;
916 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 917 resets = <&tegra_car 59>, <&tegra_car 22>;
918 reset-names = "usb", "utmi-pads";
cc34c9f7
TT		 919 nvidia,hssync-start-delay = <0>;
920 nvidia,idle-wait-delay = <17>;
921 nvidia,elastic-limit = <16>;
922 nvidia,term-range-adj = <6>;
923 nvidia,xcvr-setup = <51>;
924 nvidia.xcvr-setup-use-fuses;
925 nvidia,xcvr-lsfslew = <2>;
926 nvidia,xcvr-lsrslew = <2>;
927 nvidia,xcvr-hsslew = <32>;
928 nvidia,hssquelch-level = <2>;
929 nvidia,hsdiscon-level = <5>;
930 status = "disabled";
931 };
932
7d19a34a
HD		 933 cpus {
934 #address-cells = <1>;
935 #size-cells = <0>;
936
937 cpu@0 {
938 device_type = "cpu";
939 compatible = "arm,cortex-a9";
940 reg = <0>;
941 };
942
943 cpu@1 {
944 device_type = "cpu";
945 compatible = "arm,cortex-a9";
946 reg = <1>;
947 };
948
949 cpu@2 {
950 device_type = "cpu";
951 compatible = "arm,cortex-a9";
952 reg = <2>;
953 };
954
955 cpu@3 {
956 device_type = "cpu";
957 compatible = "arm,cortex-a9";
958 reg = <3>;
959 };
960 };
961
c04abb3a
SW		 962 pmu {
963 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 964 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
54174a33 968 };
c3e00a0e 969};
Linux 6.x block layer and io_uring tree(s)