Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
05849c93 | 2 | #include <dt-bindings/clock/tegra30-car.h> |
3325f1bc | 3 | #include <dt-bindings/gpio/tegra-gpio.h> |
6d9adf6f | 4 | #include <dt-bindings/memory/tegra30-mc.h> |
a47c662a | 5 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
6cecf916 | 6 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
86614b5d | 7 | #include <dt-bindings/soc/tegra-pmc.h> |
13a2a5ea | 8 | #include <dt-bindings/thermal/thermal.h> |
3325f1bc | 9 | |
881741fa DO |
10 | #include "tegra30-peripherals-opp.dtsi" |
11 | ||
c3e00a0e PDS |
12 | / { |
13 | compatible = "nvidia,tegra30"; | |
870c81a4 | 14 | interrupt-parent = <&lic>; |
f48ba1ae KK |
15 | #address-cells = <1>; |
16 | #size-cells = <1>; | |
17 | ||
48299769 | 18 | memory@80000000 { |
f48ba1ae | 19 | device_type = "memory"; |
48299769 | 20 | reg = <0x80000000 0x0>; |
f48ba1ae | 21 | }; |
c3e00a0e | 22 | |
508d690e | 23 | pcie@3000 { |
e07e3dbd TR |
24 | compatible = "nvidia,tegra30-pcie"; |
25 | device_type = "pci"; | |
9482a170 TR |
26 | reg = <0x00003000 0x00000800>, /* PADS registers */ |
27 | <0x00003800 0x00000200>, /* AFI registers */ | |
28 | <0x10000000 0x10000000>; /* configuration space */ | |
e07e3dbd | 29 | reg-names = "pads", "afi", "cs"; |
9482a170 TR |
30 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ |
31 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
e07e3dbd TR |
32 | interrupt-names = "intr", "msi"; |
33 | ||
97070bd4 LS |
34 | #interrupt-cells = <1>; |
35 | interrupt-map-mask = <0 0 0 0>; | |
36 | interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
37 | ||
e07e3dbd TR |
38 | bus-range = <0x00 0xff>; |
39 | #address-cells = <3>; | |
40 | #size-cells = <2>; | |
41 | ||
9482a170 TR |
42 | ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ |
43 | <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ | |
44 | <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ | |
45 | <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ | |
46 | <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ | |
47 | <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ | |
e07e3dbd TR |
48 | |
49 | clocks = <&tegra_car TEGRA30_CLK_PCIE>, | |
50 | <&tegra_car TEGRA30_CLK_AFI>, | |
e07e3dbd TR |
51 | <&tegra_car TEGRA30_CLK_PLL_E>, |
52 | <&tegra_car TEGRA30_CLK_CML0>; | |
2bd541ff | 53 | clock-names = "pex", "afi", "pll_e", "cml"; |
3393d422 | 54 | resets = <&tegra_car 70>, |
d8b316b2 MZ |
55 | <&tegra_car 72>, |
56 | <&tegra_car 74>; | |
3393d422 | 57 | reset-names = "pex", "afi", "pcie_x"; |
e07e3dbd TR |
58 | status = "disabled"; |
59 | ||
60 | pci@1,0 { | |
61 | device_type = "pci"; | |
62 | assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; | |
63 | reg = <0x000800 0 0 0 0>; | |
508d690e | 64 | bus-range = <0x00 0xff>; |
e07e3dbd TR |
65 | status = "disabled"; |
66 | ||
67 | #address-cells = <3>; | |
68 | #size-cells = <2>; | |
69 | ranges; | |
70 | ||
71 | nvidia,num-lanes = <2>; | |
72 | }; | |
73 | ||
74 | pci@2,0 { | |
75 | device_type = "pci"; | |
76 | assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; | |
77 | reg = <0x001000 0 0 0 0>; | |
508d690e | 78 | bus-range = <0x00 0xff>; |
e07e3dbd TR |
79 | status = "disabled"; |
80 | ||
81 | #address-cells = <3>; | |
82 | #size-cells = <2>; | |
83 | ranges; | |
84 | ||
85 | nvidia,num-lanes = <2>; | |
86 | }; | |
87 | ||
88 | pci@3,0 { | |
89 | device_type = "pci"; | |
90 | assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; | |
91 | reg = <0x001800 0 0 0 0>; | |
508d690e | 92 | bus-range = <0x00 0xff>; |
e07e3dbd TR |
93 | status = "disabled"; |
94 | ||
95 | #address-cells = <3>; | |
96 | #size-cells = <2>; | |
97 | ranges; | |
98 | ||
99 | nvidia,num-lanes = <2>; | |
100 | }; | |
101 | }; | |
102 | ||
7fb09952 | 103 | sram@40000000 { |
ea857036 DO |
104 | compatible = "mmio-sram"; |
105 | reg = <0x40000000 0x40000>; | |
106 | #address-cells = <1>; | |
107 | #size-cells = <1>; | |
108 | ranges = <0 0x40000000 0x40000>; | |
55f939c2 | 109 | |
7fb09952 | 110 | vde_pool: sram@400 { |
55f939c2 DO |
111 | reg = <0x400 0x3fc00>; |
112 | pool; | |
113 | }; | |
ea857036 DO |
114 | }; |
115 | ||
58ecb23f | 116 | host1x@50000000 { |
f0fd20a5 | 117 | compatible = "nvidia,tegra30-host1x"; |
ed39097c | 118 | reg = <0x50000000 0x00024000>; |
6cecf916 SW |
119 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
120 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
6cc05ba2 | 121 | interrupt-names = "syncpt", "host1x"; |
05849c93 | 122 | clocks = <&tegra_car TEGRA30_CLK_HOST1X>; |
6cc05ba2 | 123 | clock-names = "host1x"; |
3393d422 SW |
124 | resets = <&tegra_car 28>; |
125 | reset-names = "host1x"; | |
1dac1827 | 126 | iommus = <&mc TEGRA_SWGROUP_HC>; |
ed39097c TR |
127 | |
128 | #address-cells = <1>; | |
129 | #size-cells = <1>; | |
130 | ||
131 | ranges = <0x54000000 0x54000000 0x04000000>; | |
132 | ||
58ecb23f | 133 | mpe@54040000 { |
ed39097c TR |
134 | compatible = "nvidia,tegra30-mpe"; |
135 | reg = <0x54040000 0x00040000>; | |
6cecf916 | 136 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 137 | clocks = <&tegra_car TEGRA30_CLK_MPE>; |
3393d422 SW |
138 | resets = <&tegra_car 60>; |
139 | reset-names = "mpe"; | |
1dac1827 DO |
140 | |
141 | iommus = <&mc TEGRA_SWGROUP_MPE>; | |
ed39097c TR |
142 | }; |
143 | ||
58ecb23f | 144 | vi@54080000 { |
ed39097c TR |
145 | compatible = "nvidia,tegra30-vi"; |
146 | reg = <0x54080000 0x00040000>; | |
6cecf916 | 147 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 148 | clocks = <&tegra_car TEGRA30_CLK_VI>; |
3393d422 SW |
149 | resets = <&tegra_car 20>; |
150 | reset-names = "vi"; | |
1dac1827 DO |
151 | |
152 | iommus = <&mc TEGRA_SWGROUP_VI>; | |
ed39097c TR |
153 | }; |
154 | ||
58ecb23f | 155 | epp@540c0000 { |
ed39097c TR |
156 | compatible = "nvidia,tegra30-epp"; |
157 | reg = <0x540c0000 0x00040000>; | |
6cecf916 | 158 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 159 | clocks = <&tegra_car TEGRA30_CLK_EPP>; |
3393d422 SW |
160 | resets = <&tegra_car 19>; |
161 | reset-names = "epp"; | |
1dac1827 DO |
162 | |
163 | iommus = <&mc TEGRA_SWGROUP_EPP>; | |
ed39097c TR |
164 | }; |
165 | ||
58ecb23f | 166 | isp@54100000 { |
ed39097c TR |
167 | compatible = "nvidia,tegra30-isp"; |
168 | reg = <0x54100000 0x00040000>; | |
6cecf916 | 169 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 170 | clocks = <&tegra_car TEGRA30_CLK_ISP>; |
3393d422 SW |
171 | resets = <&tegra_car 23>; |
172 | reset-names = "isp"; | |
1dac1827 DO |
173 | |
174 | iommus = <&mc TEGRA_SWGROUP_ISP>; | |
ed39097c TR |
175 | }; |
176 | ||
58ecb23f | 177 | gr2d@54140000 { |
ed39097c TR |
178 | compatible = "nvidia,tegra30-gr2d"; |
179 | reg = <0x54140000 0x00040000>; | |
6cecf916 | 180 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
da45d738 | 181 | clocks = <&tegra_car TEGRA30_CLK_GR2D>; |
3393d422 SW |
182 | resets = <&tegra_car 21>; |
183 | reset-names = "2d"; | |
1dac1827 DO |
184 | |
185 | iommus = <&mc TEGRA_SWGROUP_G2>; | |
ed39097c TR |
186 | }; |
187 | ||
58ecb23f | 188 | gr3d@54180000 { |
ed39097c TR |
189 | compatible = "nvidia,tegra30-gr3d"; |
190 | reg = <0x54180000 0x00040000>; | |
9482a170 TR |
191 | clocks = <&tegra_car TEGRA30_CLK_GR3D>, |
192 | <&tegra_car TEGRA30_CLK_GR3D2>; | |
1cbc733d | 193 | clock-names = "3d", "3d2"; |
3393d422 | 194 | resets = <&tegra_car 24>, |
d8b316b2 | 195 | <&tegra_car 98>; |
3393d422 | 196 | reset-names = "3d", "3d2"; |
1dac1827 DO |
197 | |
198 | iommus = <&mc TEGRA_SWGROUP_NV>, | |
199 | <&mc TEGRA_SWGROUP_NV2>; | |
ed39097c TR |
200 | }; |
201 | ||
202 | dc@54200000 { | |
06227e3a | 203 | compatible = "nvidia,tegra30-dc"; |
ed39097c | 204 | reg = <0x54200000 0x00040000>; |
6cecf916 | 205 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
206 | clocks = <&tegra_car TEGRA30_CLK_DISP1>, |
207 | <&tegra_car TEGRA30_CLK_PLL_P>; | |
d8f64797 | 208 | clock-names = "dc", "parent"; |
3393d422 SW |
209 | resets = <&tegra_car 27>; |
210 | reset-names = "dc"; | |
ed39097c | 211 | |
6d9adf6f TR |
212 | iommus = <&mc TEGRA_SWGROUP_DC>; |
213 | ||
688b56b4 TR |
214 | nvidia,head = <0>; |
215 | ||
69ea8fa7 DO |
216 | interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, |
217 | <&mc TEGRA30_MC_DISPLAY0B &emc>, | |
218 | <&mc TEGRA30_MC_DISPLAY1B &emc>, | |
219 | <&mc TEGRA30_MC_DISPLAY0C &emc>, | |
220 | <&mc TEGRA30_MC_DISPLAYHC &emc>; | |
221 | interconnect-names = "wina", | |
222 | "winb", | |
223 | "winb-vfilter", | |
224 | "winc", | |
225 | "cursor"; | |
226 | ||
ed39097c TR |
227 | rgb { |
228 | status = "disabled"; | |
229 | }; | |
230 | }; | |
231 | ||
232 | dc@54240000 { | |
233 | compatible = "nvidia,tegra30-dc"; | |
234 | reg = <0x54240000 0x00040000>; | |
6cecf916 | 235 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
236 | clocks = <&tegra_car TEGRA30_CLK_DISP2>, |
237 | <&tegra_car TEGRA30_CLK_PLL_P>; | |
d8f64797 | 238 | clock-names = "dc", "parent"; |
3393d422 SW |
239 | resets = <&tegra_car 26>; |
240 | reset-names = "dc"; | |
ed39097c | 241 | |
6d9adf6f TR |
242 | iommus = <&mc TEGRA_SWGROUP_DCB>; |
243 | ||
688b56b4 TR |
244 | nvidia,head = <1>; |
245 | ||
69ea8fa7 DO |
246 | interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, |
247 | <&mc TEGRA30_MC_DISPLAY0BB &emc>, | |
248 | <&mc TEGRA30_MC_DISPLAY1BB &emc>, | |
249 | <&mc TEGRA30_MC_DISPLAY0CB &emc>, | |
250 | <&mc TEGRA30_MC_DISPLAYHCB &emc>; | |
251 | interconnect-names = "wina", | |
252 | "winb", | |
253 | "winb-vfilter", | |
254 | "winc", | |
255 | "cursor"; | |
256 | ||
ed39097c TR |
257 | rgb { |
258 | status = "disabled"; | |
259 | }; | |
260 | }; | |
261 | ||
58ecb23f | 262 | hdmi@54280000 { |
ed39097c TR |
263 | compatible = "nvidia,tegra30-hdmi"; |
264 | reg = <0x54280000 0x00040000>; | |
6cecf916 | 265 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
266 | clocks = <&tegra_car TEGRA30_CLK_HDMI>, |
267 | <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; | |
1cbc733d | 268 | clock-names = "hdmi", "parent"; |
3393d422 SW |
269 | resets = <&tegra_car 51>; |
270 | reset-names = "hdmi"; | |
ed39097c TR |
271 | status = "disabled"; |
272 | }; | |
273 | ||
58ecb23f | 274 | tvo@542c0000 { |
ed39097c TR |
275 | compatible = "nvidia,tegra30-tvo"; |
276 | reg = <0x542c0000 0x00040000>; | |
6cecf916 | 277 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 278 | clocks = <&tegra_car TEGRA30_CLK_TVO>; |
ed39097c TR |
279 | status = "disabled"; |
280 | }; | |
281 | ||
58ecb23f | 282 | dsi@54300000 { |
ed39097c TR |
283 | compatible = "nvidia,tegra30-dsi"; |
284 | reg = <0x54300000 0x00040000>; | |
eb6563a6 TR |
285 | clocks = <&tegra_car TEGRA30_CLK_DSIA>, |
286 | <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; | |
287 | clock-names = "dsi", "parent"; | |
3393d422 SW |
288 | resets = <&tegra_car 48>; |
289 | reset-names = "dsi"; | |
ed39097c TR |
290 | status = "disabled"; |
291 | }; | |
7ee1e9fe TR |
292 | |
293 | dsi@54400000 { | |
294 | compatible = "nvidia,tegra30-dsi"; | |
295 | reg = <0x54400000 0x00040000>; | |
296 | clocks = <&tegra_car TEGRA30_CLK_DSIB>, | |
297 | <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; | |
298 | clock-names = "dsi", "parent"; | |
299 | resets = <&tegra_car 84>; | |
300 | reset-names = "dsi"; | |
301 | status = "disabled"; | |
302 | }; | |
ed39097c TR |
303 | }; |
304 | ||
2cda1880 | 305 | timer@50040600 { |
73368ba0 SW |
306 | compatible = "arm,cortex-a9-twd-timer"; |
307 | reg = <0x50040600 0x20>; | |
870c81a4 | 308 | interrupt-parent = <&intc>; |
6cecf916 | 309 | interrupts = <GIC_PPI 13 |
e7d9b270 | 310 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; |
05849c93 | 311 | clocks = <&tegra_car TEGRA30_CLK_TWD>; |
73368ba0 SW |
312 | }; |
313 | ||
58ecb23f | 314 | intc: interrupt-controller@50041000 { |
c3e00a0e | 315 | compatible = "arm,cortex-a9-gic"; |
9482a170 TR |
316 | reg = <0x50041000 0x1000>, |
317 | <0x50040100 0x0100>; | |
2eaab06e SW |
318 | interrupt-controller; |
319 | #interrupt-cells = <3>; | |
870c81a4 | 320 | interrupt-parent = <&intc>; |
c3e00a0e PDS |
321 | }; |
322 | ||
58ecb23f | 323 | cache-controller@50043000 { |
bb2c1de9 SW |
324 | compatible = "arm,pl310-cache"; |
325 | reg = <0x50043000 0x1000>; | |
326 | arm,data-latency = <6 6 2>; | |
327 | arm,tag-latency = <5 5 2>; | |
328 | cache-unified; | |
329 | cache-level = <2>; | |
330 | }; | |
331 | ||
870c81a4 MZ |
332 | lic: interrupt-controller@60004000 { |
333 | compatible = "nvidia,tegra30-ictlr"; | |
334 | reg = <0x60004000 0x100>, | |
335 | <0x60004100 0x50>, | |
336 | <0x60004200 0x50>, | |
337 | <0x60004300 0x50>, | |
338 | <0x60004400 0x50>; | |
339 | interrupt-controller; | |
340 | #interrupt-cells = <3>; | |
341 | interrupt-parent = <&intc>; | |
342 | }; | |
343 | ||
2f2b7fb2 SW |
344 | timer@60005000 { |
345 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; | |
346 | reg = <0x60005000 0x400>; | |
6cecf916 SW |
347 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
348 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
349 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
350 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
351 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
352 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
05849c93 | 353 | clocks = <&tegra_car TEGRA30_CLK_TIMER>; |
2f2b7fb2 SW |
354 | }; |
355 | ||
58ecb23f | 356 | tegra_car: clock@60006000 { |
95985667 PG |
357 | compatible = "nvidia,tegra30-car"; |
358 | reg = <0x60006000 0x1000>; | |
359 | #clock-cells = <1>; | |
3393d422 | 360 | #reset-cells = <1>; |
95985667 PG |
361 | }; |
362 | ||
b1023134 TR |
363 | flow-controller@60007000 { |
364 | compatible = "nvidia,tegra30-flowctrl"; | |
365 | reg = <0x60007000 0x1000>; | |
366 | }; | |
367 | ||
58ecb23f | 368 | apbdma: dma@6000a000 { |
8051b75a SW |
369 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
370 | reg = <0x6000a000 0x1400>; | |
6cecf916 SW |
371 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
372 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
373 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
374 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
375 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
376 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
377 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
378 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
379 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
380 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
381 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
382 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
383 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
384 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
385 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
386 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
387 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
388 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
389 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
390 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
391 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
392 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
393 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
394 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
395 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
396 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
397 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
398 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
399 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
400 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
401 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
402 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
05849c93 | 403 | clocks = <&tegra_car TEGRA30_CLK_APBDMA>; |
3393d422 SW |
404 | resets = <&tegra_car 34>; |
405 | reset-names = "dma"; | |
034d023f | 406 | #dma-cells = <1>; |
8051b75a SW |
407 | }; |
408 | ||
0d5ccb38 | 409 | ahb: ahb@6000c000 { |
c04abb3a | 410 | compatible = "nvidia,tegra30-ahb"; |
0d5ccb38 | 411 | reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ |
c3e00a0e PDS |
412 | }; |
413 | ||
592b74b1 | 414 | actmon: actmon@6000c800 { |
1078946b DO |
415 | compatible = "nvidia,tegra30-actmon"; |
416 | reg = <0x6000c800 0x400>; | |
417 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
418 | clocks = <&tegra_car TEGRA30_CLK_ACTMON>, | |
419 | <&tegra_car TEGRA30_CLK_EMC>; | |
420 | clock-names = "actmon", "emc"; | |
421 | resets = <&tegra_car TEGRA30_CLK_ACTMON>; | |
422 | reset-names = "actmon"; | |
881741fa DO |
423 | operating-points-v2 = <&emc_bw_dfs_opp_table>; |
424 | interconnects = <&mc TEGRA30_MC_MPCORER &emc>; | |
425 | interconnect-names = "cpu-read"; | |
592b74b1 | 426 | #cooling-cells = <2>; |
1078946b DO |
427 | }; |
428 | ||
58ecb23f | 429 | gpio: gpio@6000d000 { |
35f210ec | 430 | compatible = "nvidia,tegra30-gpio"; |
95decf84 | 431 | reg = <0x6000d000 0x1000>; |
6cecf916 SW |
432 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
433 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
434 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
435 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
436 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
437 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
438 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
439 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
c3e00a0e PDS |
440 | #gpio-cells = <2>; |
441 | gpio-controller; | |
6f74dc9b SW |
442 | #interrupt-cells = <2>; |
443 | interrupt-controller; | |
4f1d8414 | 444 | /* |
17cdddf0 | 445 | gpio-ranges = <&pinmux 0 0 248>; |
4f1d8414 | 446 | */ |
c3e00a0e PDS |
447 | }; |
448 | ||
55f939c2 DO |
449 | vde@6001a000 { |
450 | compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; | |
9482a170 TR |
451 | reg = <0x6001a000 0x1000>, /* Syntax Engine */ |
452 | <0x6001b000 0x1000>, /* Video Bitstream Engine */ | |
453 | <0x6001c000 0x100>, /* Macroblock Engine */ | |
454 | <0x6001c200 0x100>, /* Post-processing Engine */ | |
455 | <0x6001c400 0x100>, /* Motion Compensation Engine */ | |
456 | <0x6001c600 0x100>, /* Transform Engine */ | |
457 | <0x6001c800 0x100>, /* Pixel prediction block */ | |
458 | <0x6001ca00 0x100>, /* Video DMA */ | |
459 | <0x6001d800 0x400>; /* Video frame controls */ | |
55f939c2 DO |
460 | reg-names = "sxe", "bsev", "mbe", "ppe", "mce", |
461 | "tfe", "ppb", "vdma", "frameid"; | |
462 | iram = <&vde_pool>; /* IRAM region */ | |
463 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ | |
464 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ | |
465 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ | |
466 | interrupt-names = "sync-token", "bsev", "sxe"; | |
467 | clocks = <&tegra_car TEGRA30_CLK_VDE>; | |
d072094b DO |
468 | reset-names = "vde", "mc"; |
469 | resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; | |
cdc233fb | 470 | iommus = <&mc TEGRA_SWGROUP_VDE>; |
55f939c2 DO |
471 | }; |
472 | ||
155dfc7b PDS |
473 | apbmisc@70000800 { |
474 | compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; | |
9482a170 TR |
475 | reg = <0x70000800 0x64>, /* Chip revision */ |
476 | <0x70000008 0x04>; /* Strapping options */ | |
155dfc7b PDS |
477 | }; |
478 | ||
58ecb23f | 479 | pinmux: pinmux@70000868 { |
c04abb3a | 480 | compatible = "nvidia,tegra30-pinmux"; |
9482a170 TR |
481 | reg = <0x70000868 0x0d4>, /* Pad control registers */ |
482 | <0x70003000 0x3e4>; /* Mux registers */ | |
c04abb3a SW |
483 | }; |
484 | ||
b6551bb9 LD |
485 | /* |
486 | * There are two serial driver i.e. 8250 based simple serial | |
487 | * driver and APB DMA based serial driver for higher baudrate | |
488 | * and performace. To enable the 8250 based driver, the compatible | |
489 | * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable | |
e1098248 | 490 | * the APB DMA based serial driver, the compatible is |
b6551bb9 LD |
491 | * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". |
492 | */ | |
493 | uarta: serial@70006000 { | |
c3e00a0e PDS |
494 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
495 | reg = <0x70006000 0x40>; | |
496 | reg-shift = <2>; | |
6cecf916 | 497 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 498 | clocks = <&tegra_car TEGRA30_CLK_UARTA>; |
3393d422 SW |
499 | resets = <&tegra_car 6>; |
500 | reset-names = "serial"; | |
034d023f SW |
501 | dmas = <&apbdma 8>, <&apbdma 8>; |
502 | dma-names = "rx", "tx"; | |
223ef78d | 503 | status = "disabled"; |
c3e00a0e PDS |
504 | }; |
505 | ||
b6551bb9 | 506 | uartb: serial@70006040 { |
c3e00a0e PDS |
507 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
508 | reg = <0x70006040 0x40>; | |
509 | reg-shift = <2>; | |
6cecf916 | 510 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 511 | clocks = <&tegra_car TEGRA30_CLK_UARTB>; |
3393d422 SW |
512 | resets = <&tegra_car 7>; |
513 | reset-names = "serial"; | |
034d023f SW |
514 | dmas = <&apbdma 9>, <&apbdma 9>; |
515 | dma-names = "rx", "tx"; | |
223ef78d | 516 | status = "disabled"; |
c3e00a0e PDS |
517 | }; |
518 | ||
b6551bb9 | 519 | uartc: serial@70006200 { |
c3e00a0e PDS |
520 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
521 | reg = <0x70006200 0x100>; | |
522 | reg-shift = <2>; | |
6cecf916 | 523 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 524 | clocks = <&tegra_car TEGRA30_CLK_UARTC>; |
3393d422 SW |
525 | resets = <&tegra_car 55>; |
526 | reset-names = "serial"; | |
034d023f SW |
527 | dmas = <&apbdma 10>, <&apbdma 10>; |
528 | dma-names = "rx", "tx"; | |
223ef78d | 529 | status = "disabled"; |
c3e00a0e PDS |
530 | }; |
531 | ||
b6551bb9 | 532 | uartd: serial@70006300 { |
c3e00a0e PDS |
533 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
534 | reg = <0x70006300 0x100>; | |
535 | reg-shift = <2>; | |
6cecf916 | 536 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 537 | clocks = <&tegra_car TEGRA30_CLK_UARTD>; |
3393d422 SW |
538 | resets = <&tegra_car 65>; |
539 | reset-names = "serial"; | |
034d023f SW |
540 | dmas = <&apbdma 19>, <&apbdma 19>; |
541 | dma-names = "rx", "tx"; | |
223ef78d | 542 | status = "disabled"; |
c3e00a0e PDS |
543 | }; |
544 | ||
b6551bb9 | 545 | uarte: serial@70006400 { |
c3e00a0e PDS |
546 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
547 | reg = <0x70006400 0x100>; | |
548 | reg-shift = <2>; | |
6cecf916 | 549 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 550 | clocks = <&tegra_car TEGRA30_CLK_UARTE>; |
3393d422 SW |
551 | resets = <&tegra_car 66>; |
552 | reset-names = "serial"; | |
034d023f SW |
553 | dmas = <&apbdma 20>, <&apbdma 20>; |
554 | dma-names = "rx", "tx"; | |
223ef78d | 555 | status = "disabled"; |
c3e00a0e PDS |
556 | }; |
557 | ||
5e35c1f0 MK |
558 | gmi@70009000 { |
559 | compatible = "nvidia,tegra30-gmi"; | |
560 | reg = <0x70009000 0x1000>; | |
561 | #address-cells = <2>; | |
562 | #size-cells = <1>; | |
563 | ranges = <0 0 0x48000000 0x7ffffff>; | |
564 | clocks = <&tegra_car TEGRA30_CLK_NOR>; | |
565 | clock-names = "gmi"; | |
566 | resets = <&tegra_car 42>; | |
567 | reset-names = "gmi"; | |
568 | status = "disabled"; | |
569 | }; | |
570 | ||
58ecb23f | 571 | pwm: pwm@7000a000 { |
140fd977 TR |
572 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
573 | reg = <0x7000a000 0x100>; | |
574 | #pwm-cells = <2>; | |
05849c93 | 575 | clocks = <&tegra_car TEGRA30_CLK_PWM>; |
3393d422 SW |
576 | resets = <&tegra_car 17>; |
577 | reset-names = "pwm"; | |
b69cd984 | 578 | status = "disabled"; |
140fd977 TR |
579 | }; |
580 | ||
58ecb23f | 581 | rtc@7000e000 { |
380e04ac SW |
582 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
583 | reg = <0x7000e000 0x100>; | |
6cecf916 | 584 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 585 | clocks = <&tegra_car TEGRA30_CLK_RTC>; |
380e04ac SW |
586 | }; |
587 | ||
c04abb3a | 588 | i2c@7000c000 { |
d8b316b2 | 589 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
c04abb3a | 590 | reg = <0x7000c000 0x100>; |
6cecf916 | 591 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
592 | #address-cells = <1>; |
593 | #size-cells = <0>; | |
05849c93 HD |
594 | clocks = <&tegra_car TEGRA30_CLK_I2C1>, |
595 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 596 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
597 | resets = <&tegra_car 12>; |
598 | reset-names = "i2c"; | |
034d023f SW |
599 | dmas = <&apbdma 21>, <&apbdma 21>; |
600 | dma-names = "rx", "tx"; | |
223ef78d | 601 | status = "disabled"; |
c3e00a0e PDS |
602 | }; |
603 | ||
c04abb3a | 604 | i2c@7000c400 { |
c04abb3a SW |
605 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
606 | reg = <0x7000c400 0x100>; | |
6cecf916 | 607 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
608 | #address-cells = <1>; |
609 | #size-cells = <0>; | |
05849c93 HD |
610 | clocks = <&tegra_car TEGRA30_CLK_I2C2>, |
611 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 612 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
613 | resets = <&tegra_car 54>; |
614 | reset-names = "i2c"; | |
034d023f SW |
615 | dmas = <&apbdma 22>, <&apbdma 22>; |
616 | dma-names = "rx", "tx"; | |
223ef78d | 617 | status = "disabled"; |
c3e00a0e PDS |
618 | }; |
619 | ||
c04abb3a | 620 | i2c@7000c500 { |
c04abb3a SW |
621 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
622 | reg = <0x7000c500 0x100>; | |
6cecf916 | 623 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
624 | #address-cells = <1>; |
625 | #size-cells = <0>; | |
05849c93 HD |
626 | clocks = <&tegra_car TEGRA30_CLK_I2C3>, |
627 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 628 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
629 | resets = <&tegra_car 67>; |
630 | reset-names = "i2c"; | |
034d023f SW |
631 | dmas = <&apbdma 23>, <&apbdma 23>; |
632 | dma-names = "rx", "tx"; | |
223ef78d | 633 | status = "disabled"; |
c3e00a0e PDS |
634 | }; |
635 | ||
c04abb3a | 636 | i2c@7000c700 { |
c04abb3a SW |
637 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
638 | reg = <0x7000c700 0x100>; | |
6cecf916 | 639 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
640 | #address-cells = <1>; |
641 | #size-cells = <0>; | |
05849c93 HD |
642 | clocks = <&tegra_car TEGRA30_CLK_I2C4>, |
643 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
3393d422 SW |
644 | resets = <&tegra_car 103>; |
645 | reset-names = "i2c"; | |
1cbc733d | 646 | clock-names = "div-clk", "fast-clk"; |
034d023f SW |
647 | dmas = <&apbdma 26>, <&apbdma 26>; |
648 | dma-names = "rx", "tx"; | |
223ef78d | 649 | status = "disabled"; |
c3e00a0e PDS |
650 | }; |
651 | ||
c04abb3a | 652 | i2c@7000d000 { |
c04abb3a SW |
653 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
654 | reg = <0x7000d000 0x100>; | |
6cecf916 | 655 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
656 | #address-cells = <1>; |
657 | #size-cells = <0>; | |
05849c93 HD |
658 | clocks = <&tegra_car TEGRA30_CLK_I2C5>, |
659 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 660 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
661 | resets = <&tegra_car 47>; |
662 | reset-names = "i2c"; | |
034d023f SW |
663 | dmas = <&apbdma 24>, <&apbdma 24>; |
664 | dma-names = "rx", "tx"; | |
223ef78d | 665 | status = "disabled"; |
c04abb3a SW |
666 | }; |
667 | ||
a86b0db3 LD |
668 | spi@7000d400 { |
669 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
670 | reg = <0x7000d400 0x200>; | |
6cecf916 | 671 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
672 | #address-cells = <1>; |
673 | #size-cells = <0>; | |
05849c93 | 674 | clocks = <&tegra_car TEGRA30_CLK_SBC1>; |
3393d422 SW |
675 | resets = <&tegra_car 41>; |
676 | reset-names = "spi"; | |
034d023f SW |
677 | dmas = <&apbdma 15>, <&apbdma 15>; |
678 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
679 | status = "disabled"; |
680 | }; | |
681 | ||
682 | spi@7000d600 { | |
683 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
684 | reg = <0x7000d600 0x200>; | |
6cecf916 | 685 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
686 | #address-cells = <1>; |
687 | #size-cells = <0>; | |
05849c93 | 688 | clocks = <&tegra_car TEGRA30_CLK_SBC2>; |
3393d422 SW |
689 | resets = <&tegra_car 44>; |
690 | reset-names = "spi"; | |
034d023f SW |
691 | dmas = <&apbdma 16>, <&apbdma 16>; |
692 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
693 | status = "disabled"; |
694 | }; | |
695 | ||
696 | spi@7000d800 { | |
697 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
57471c8d | 698 | reg = <0x7000d800 0x200>; |
6cecf916 | 699 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
700 | #address-cells = <1>; |
701 | #size-cells = <0>; | |
05849c93 | 702 | clocks = <&tegra_car TEGRA30_CLK_SBC3>; |
3393d422 SW |
703 | resets = <&tegra_car 46>; |
704 | reset-names = "spi"; | |
034d023f SW |
705 | dmas = <&apbdma 17>, <&apbdma 17>; |
706 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
707 | status = "disabled"; |
708 | }; | |
709 | ||
710 | spi@7000da00 { | |
711 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
712 | reg = <0x7000da00 0x200>; | |
6cecf916 | 713 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
714 | #address-cells = <1>; |
715 | #size-cells = <0>; | |
05849c93 | 716 | clocks = <&tegra_car TEGRA30_CLK_SBC4>; |
3393d422 SW |
717 | resets = <&tegra_car 68>; |
718 | reset-names = "spi"; | |
034d023f SW |
719 | dmas = <&apbdma 18>, <&apbdma 18>; |
720 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
721 | status = "disabled"; |
722 | }; | |
723 | ||
724 | spi@7000dc00 { | |
725 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
726 | reg = <0x7000dc00 0x200>; | |
6cecf916 | 727 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
728 | #address-cells = <1>; |
729 | #size-cells = <0>; | |
05849c93 | 730 | clocks = <&tegra_car TEGRA30_CLK_SBC5>; |
3393d422 SW |
731 | resets = <&tegra_car 104>; |
732 | reset-names = "spi"; | |
034d023f SW |
733 | dmas = <&apbdma 27>, <&apbdma 27>; |
734 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
735 | status = "disabled"; |
736 | }; | |
737 | ||
738 | spi@7000de00 { | |
739 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
740 | reg = <0x7000de00 0x200>; | |
6cecf916 | 741 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
742 | #address-cells = <1>; |
743 | #size-cells = <0>; | |
05849c93 | 744 | clocks = <&tegra_car TEGRA30_CLK_SBC6>; |
3393d422 SW |
745 | resets = <&tegra_car 106>; |
746 | reset-names = "spi"; | |
034d023f SW |
747 | dmas = <&apbdma 28>, <&apbdma 28>; |
748 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
749 | status = "disabled"; |
750 | }; | |
751 | ||
58ecb23f | 752 | kbc@7000e200 { |
699ed4b9 LD |
753 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; |
754 | reg = <0x7000e200 0x100>; | |
6cecf916 | 755 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 756 | clocks = <&tegra_car TEGRA30_CLK_KBC>; |
3393d422 SW |
757 | resets = <&tegra_car 36>; |
758 | reset-names = "kbc"; | |
699ed4b9 LD |
759 | status = "disabled"; |
760 | }; | |
761 | ||
86614b5d | 762 | tegra_pmc: pmc@7000e400 { |
2b84e53b | 763 | compatible = "nvidia,tegra30-pmc"; |
c04abb3a | 764 | reg = <0x7000e400 0x400>; |
05849c93 | 765 | clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; |
7021d122 | 766 | clock-names = "pclk", "clk32k_in"; |
86614b5d | 767 | #clock-cells = <1>; |
c04abb3a SW |
768 | }; |
769 | ||
a9fe468f | 770 | mc: memory-controller@7000f000 { |
c04abb3a | 771 | compatible = "nvidia,tegra30-mc"; |
a9fe468f TR |
772 | reg = <0x7000f000 0x400>; |
773 | clocks = <&tegra_car TEGRA30_CLK_MC>; | |
774 | clock-names = "mc"; | |
775 | ||
6cecf916 | 776 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
c04abb3a | 777 | |
a9fe468f | 778 | #iommu-cells = <1>; |
d072094b | 779 | #reset-cells = <1>; |
69ea8fa7 | 780 | #interconnect-cells = <1>; |
c3e00a0e | 781 | }; |
9ee6a5c4 | 782 | |
69ea8fa7 | 783 | emc: memory-controller@7000f400 { |
3193a063 DO |
784 | compatible = "nvidia,tegra30-emc"; |
785 | reg = <0x7000f400 0x400>; | |
786 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
787 | clocks = <&tegra_car TEGRA30_CLK_EMC>; | |
788 | ||
789 | nvidia,memory-controller = <&mc>; | |
881741fa | 790 | operating-points-v2 = <&emc_icc_dvfs_opp_table>; |
69ea8fa7 DO |
791 | |
792 | #interconnect-cells = <0>; | |
3193a063 DO |
793 | }; |
794 | ||
155dfc7b PDS |
795 | fuse@7000f800 { |
796 | compatible = "nvidia,tegra30-efuse"; | |
797 | reg = <0x7000f800 0x400>; | |
798 | clocks = <&tegra_car TEGRA30_CLK_FUSE>; | |
799 | clock-names = "fuse"; | |
800 | resets = <&tegra_car 39>; | |
801 | reset-names = "fuse"; | |
802 | }; | |
803 | ||
13a2a5ea DO |
804 | tsensor: tsensor@70014000 { |
805 | compatible = "nvidia,tegra30-tsensor"; | |
806 | reg = <0x70014000 0x500>; | |
807 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
808 | clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; | |
809 | resets = <&tegra_car TEGRA30_CLK_TSENSOR>; | |
810 | ||
811 | assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; | |
812 | assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>; | |
813 | assigned-clock-rates = <500000>; | |
814 | ||
815 | #thermal-sensor-cells = <1>; | |
816 | }; | |
817 | ||
cbee2613 MZ |
818 | hda@70030000 { |
819 | compatible = "nvidia,tegra30-hda"; | |
820 | reg = <0x70030000 0x10000>; | |
821 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
822 | clocks = <&tegra_car TEGRA30_CLK_HDA>, | |
d8b316b2 | 823 | <&tegra_car TEGRA30_CLK_HDA2HDMI>, |
cbee2613 MZ |
824 | <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; |
825 | clock-names = "hda", "hda2hdmi", "hda2codec_2x"; | |
826 | resets = <&tegra_car 125>, /* hda */ | |
827 | <&tegra_car 128>, /* hda2hdmi */ | |
828 | <&tegra_car 111>; /* hda2codec_2x */ | |
829 | reset-names = "hda", "hda2hdmi", "hda2codec_2x"; | |
830 | status = "disabled"; | |
831 | }; | |
832 | ||
58ecb23f | 833 | ahub@70080000 { |
9ee6a5c4 | 834 | compatible = "nvidia,tegra30-ahub"; |
9482a170 TR |
835 | reg = <0x70080000 0x200>, |
836 | <0x70080200 0x100>; | |
6cecf916 | 837 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 838 | clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, |
2bd541ff SW |
839 | <&tegra_car TEGRA30_CLK_APBIF>; |
840 | clock-names = "d_audio", "apbif"; | |
3393d422 SW |
841 | resets = <&tegra_car 106>, /* d_audio */ |
842 | <&tegra_car 107>, /* apbif */ | |
843 | <&tegra_car 30>, /* i2s0 */ | |
844 | <&tegra_car 11>, /* i2s1 */ | |
845 | <&tegra_car 18>, /* i2s2 */ | |
846 | <&tegra_car 101>, /* i2s3 */ | |
847 | <&tegra_car 102>, /* i2s4 */ | |
848 | <&tegra_car 108>, /* dam0 */ | |
849 | <&tegra_car 109>, /* dam1 */ | |
850 | <&tegra_car 110>, /* dam2 */ | |
851 | <&tegra_car 10>; /* spdif */ | |
852 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
853 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
854 | "spdif"; | |
034d023f SW |
855 | dmas = <&apbdma 1>, <&apbdma 1>, |
856 | <&apbdma 2>, <&apbdma 2>, | |
857 | <&apbdma 3>, <&apbdma 3>, | |
858 | <&apbdma 4>, <&apbdma 4>; | |
859 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", | |
860 | "rx3", "tx3"; | |
9ee6a5c4 SW |
861 | ranges; |
862 | #address-cells = <1>; | |
863 | #size-cells = <1>; | |
864 | ||
865 | tegra_i2s0: i2s@70080300 { | |
866 | compatible = "nvidia,tegra30-i2s"; | |
867 | reg = <0x70080300 0x100>; | |
868 | nvidia,ahub-cif-ids = <4 4>; | |
05849c93 | 869 | clocks = <&tegra_car TEGRA30_CLK_I2S0>; |
3393d422 SW |
870 | resets = <&tegra_car 30>; |
871 | reset-names = "i2s"; | |
223ef78d | 872 | status = "disabled"; |
9ee6a5c4 SW |
873 | }; |
874 | ||
875 | tegra_i2s1: i2s@70080400 { | |
876 | compatible = "nvidia,tegra30-i2s"; | |
877 | reg = <0x70080400 0x100>; | |
878 | nvidia,ahub-cif-ids = <5 5>; | |
05849c93 | 879 | clocks = <&tegra_car TEGRA30_CLK_I2S1>; |
3393d422 SW |
880 | resets = <&tegra_car 11>; |
881 | reset-names = "i2s"; | |
223ef78d | 882 | status = "disabled"; |
9ee6a5c4 SW |
883 | }; |
884 | ||
885 | tegra_i2s2: i2s@70080500 { | |
886 | compatible = "nvidia,tegra30-i2s"; | |
887 | reg = <0x70080500 0x100>; | |
888 | nvidia,ahub-cif-ids = <6 6>; | |
05849c93 | 889 | clocks = <&tegra_car TEGRA30_CLK_I2S2>; |
3393d422 SW |
890 | resets = <&tegra_car 18>; |
891 | reset-names = "i2s"; | |
223ef78d | 892 | status = "disabled"; |
9ee6a5c4 SW |
893 | }; |
894 | ||
895 | tegra_i2s3: i2s@70080600 { | |
896 | compatible = "nvidia,tegra30-i2s"; | |
897 | reg = <0x70080600 0x100>; | |
898 | nvidia,ahub-cif-ids = <7 7>; | |
05849c93 | 899 | clocks = <&tegra_car TEGRA30_CLK_I2S3>; |
3393d422 SW |
900 | resets = <&tegra_car 101>; |
901 | reset-names = "i2s"; | |
223ef78d | 902 | status = "disabled"; |
9ee6a5c4 SW |
903 | }; |
904 | ||
905 | tegra_i2s4: i2s@70080700 { | |
906 | compatible = "nvidia,tegra30-i2s"; | |
907 | reg = <0x70080700 0x100>; | |
908 | nvidia,ahub-cif-ids = <8 8>; | |
05849c93 | 909 | clocks = <&tegra_car TEGRA30_CLK_I2S4>; |
3393d422 SW |
910 | resets = <&tegra_car 102>; |
911 | reset-names = "i2s"; | |
223ef78d | 912 | status = "disabled"; |
9ee6a5c4 SW |
913 | }; |
914 | }; | |
7868a9bc | 915 | |
32c096c2 | 916 | mmc@78000000 { |
f3de06b4 | 917 | compatible = "nvidia,tegra30-sdhci"; |
c04abb3a | 918 | reg = <0x78000000 0x200>; |
6cecf916 | 919 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 920 | clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; |
f538588b | 921 | clock-names = "sdhci"; |
3393d422 SW |
922 | resets = <&tegra_car 14>; |
923 | reset-names = "sdhci"; | |
223ef78d | 924 | status = "disabled"; |
7868a9bc | 925 | }; |
ecf43742 | 926 | |
32c096c2 | 927 | mmc@78000200 { |
f3de06b4 | 928 | compatible = "nvidia,tegra30-sdhci"; |
c04abb3a | 929 | reg = <0x78000200 0x200>; |
6cecf916 | 930 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 931 | clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; |
f538588b | 932 | clock-names = "sdhci"; |
3393d422 SW |
933 | resets = <&tegra_car 9>; |
934 | reset-names = "sdhci"; | |
223ef78d | 935 | status = "disabled"; |
ecf43742 | 936 | }; |
54174a33 | 937 | |
32c096c2 | 938 | mmc@78000400 { |
f3de06b4 | 939 | compatible = "nvidia,tegra30-sdhci"; |
c04abb3a | 940 | reg = <0x78000400 0x200>; |
6cecf916 | 941 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 942 | clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; |
f538588b | 943 | clock-names = "sdhci"; |
3393d422 SW |
944 | resets = <&tegra_car 69>; |
945 | reset-names = "sdhci"; | |
223ef78d | 946 | status = "disabled"; |
c04abb3a SW |
947 | }; |
948 | ||
32c096c2 | 949 | mmc@78000600 { |
f3de06b4 | 950 | compatible = "nvidia,tegra30-sdhci"; |
c04abb3a | 951 | reg = <0x78000600 0x200>; |
6cecf916 | 952 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 953 | clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; |
f538588b | 954 | clock-names = "sdhci"; |
3393d422 SW |
955 | resets = <&tegra_car 15>; |
956 | reset-names = "sdhci"; | |
223ef78d | 957 | status = "disabled"; |
c04abb3a SW |
958 | }; |
959 | ||
cc34c9f7 TT |
960 | usb@7d000000 { |
961 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
962 | reg = <0x7d000000 0x4000>; | |
963 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
964 | phy_type = "utmi"; | |
965 | clocks = <&tegra_car TEGRA30_CLK_USBD>; | |
3393d422 SW |
966 | resets = <&tegra_car 22>; |
967 | reset-names = "usb"; | |
cc34c9f7 TT |
968 | nvidia,needs-double-reset; |
969 | nvidia,phy = <&phy1>; | |
970 | status = "disabled"; | |
971 | }; | |
972 | ||
973 | phy1: usb-phy@7d000000 { | |
974 | compatible = "nvidia,tegra30-usb-phy"; | |
9482a170 TR |
975 | reg = <0x7d000000 0x4000>, |
976 | <0x7d000000 0x4000>; | |
b460ecc0 | 977 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
cc34c9f7 TT |
978 | phy_type = "utmi"; |
979 | clocks = <&tegra_car TEGRA30_CLK_USBD>, | |
980 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
981 | <&tegra_car TEGRA30_CLK_USBD>; | |
982 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
983 | resets = <&tegra_car 22>, <&tegra_car 22>; |
984 | reset-names = "usb", "utmi-pads"; | |
4c0bb8ca | 985 | #phy-cells = <0>; |
cc34c9f7 TT |
986 | nvidia,hssync-start-delay = <9>; |
987 | nvidia,idle-wait-delay = <17>; | |
988 | nvidia,elastic-limit = <16>; | |
989 | nvidia,term-range-adj = <6>; | |
990 | nvidia,xcvr-setup = <51>; | |
564706f6 | 991 | nvidia,xcvr-setup-use-fuses; |
cc34c9f7 TT |
992 | nvidia,xcvr-lsfslew = <1>; |
993 | nvidia,xcvr-lsrslew = <1>; | |
994 | nvidia,xcvr-hsslew = <32>; | |
995 | nvidia,hssquelch-level = <2>; | |
996 | nvidia,hsdiscon-level = <5>; | |
308efde2 | 997 | nvidia,has-utmi-pad-registers; |
b460ecc0 | 998 | nvidia,pmc = <&tegra_pmc 0>; |
cc34c9f7 TT |
999 | status = "disabled"; |
1000 | }; | |
1001 | ||
1002 | usb@7d004000 { | |
1003 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
1004 | reg = <0x7d004000 0x4000>; | |
1005 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
fd6441ec | 1006 | phy_type = "utmi"; |
cc34c9f7 | 1007 | clocks = <&tegra_car TEGRA30_CLK_USB2>; |
3393d422 SW |
1008 | resets = <&tegra_car 58>; |
1009 | reset-names = "usb"; | |
cc34c9f7 TT |
1010 | nvidia,phy = <&phy2>; |
1011 | status = "disabled"; | |
1012 | }; | |
1013 | ||
1014 | phy2: usb-phy@7d004000 { | |
1015 | compatible = "nvidia,tegra30-usb-phy"; | |
9482a170 TR |
1016 | reg = <0x7d004000 0x4000>, |
1017 | <0x7d000000 0x4000>; | |
b460ecc0 | 1018 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
fd6441ec | 1019 | phy_type = "utmi"; |
cc34c9f7 TT |
1020 | clocks = <&tegra_car TEGRA30_CLK_USB2>, |
1021 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
fd6441ec EB |
1022 | <&tegra_car TEGRA30_CLK_USBD>; |
1023 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
1024 | resets = <&tegra_car 58>, <&tegra_car 22>; |
1025 | reset-names = "usb", "utmi-pads"; | |
4c0bb8ca | 1026 | #phy-cells = <0>; |
fd6441ec EB |
1027 | nvidia,hssync-start-delay = <9>; |
1028 | nvidia,idle-wait-delay = <17>; | |
1029 | nvidia,elastic-limit = <16>; | |
1030 | nvidia,term-range-adj = <6>; | |
1031 | nvidia,xcvr-setup = <51>; | |
564706f6 | 1032 | nvidia,xcvr-setup-use-fuses; |
fd6441ec EB |
1033 | nvidia,xcvr-lsfslew = <2>; |
1034 | nvidia,xcvr-lsrslew = <2>; | |
1035 | nvidia,xcvr-hsslew = <32>; | |
1036 | nvidia,hssquelch-level = <2>; | |
1037 | nvidia,hsdiscon-level = <5>; | |
b460ecc0 | 1038 | nvidia,pmc = <&tegra_pmc 2>; |
cc34c9f7 TT |
1039 | status = "disabled"; |
1040 | }; | |
1041 | ||
1042 | usb@7d008000 { | |
1043 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
1044 | reg = <0x7d008000 0x4000>; | |
1045 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
1046 | phy_type = "utmi"; | |
1047 | clocks = <&tegra_car TEGRA30_CLK_USB3>; | |
3393d422 SW |
1048 | resets = <&tegra_car 59>; |
1049 | reset-names = "usb"; | |
cc34c9f7 TT |
1050 | nvidia,phy = <&phy3>; |
1051 | status = "disabled"; | |
1052 | }; | |
1053 | ||
1054 | phy3: usb-phy@7d008000 { | |
1055 | compatible = "nvidia,tegra30-usb-phy"; | |
9482a170 TR |
1056 | reg = <0x7d008000 0x4000>, |
1057 | <0x7d000000 0x4000>; | |
b460ecc0 | 1058 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
cc34c9f7 TT |
1059 | phy_type = "utmi"; |
1060 | clocks = <&tegra_car TEGRA30_CLK_USB3>, | |
1061 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
1062 | <&tegra_car TEGRA30_CLK_USBD>; | |
1063 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
1064 | resets = <&tegra_car 59>, <&tegra_car 22>; |
1065 | reset-names = "usb", "utmi-pads"; | |
4c0bb8ca | 1066 | #phy-cells = <0>; |
cc34c9f7 TT |
1067 | nvidia,hssync-start-delay = <0>; |
1068 | nvidia,idle-wait-delay = <17>; | |
1069 | nvidia,elastic-limit = <16>; | |
1070 | nvidia,term-range-adj = <6>; | |
1071 | nvidia,xcvr-setup = <51>; | |
564706f6 | 1072 | nvidia,xcvr-setup-use-fuses; |
cc34c9f7 TT |
1073 | nvidia,xcvr-lsfslew = <2>; |
1074 | nvidia,xcvr-lsrslew = <2>; | |
1075 | nvidia,xcvr-hsslew = <32>; | |
1076 | nvidia,hssquelch-level = <2>; | |
1077 | nvidia,hsdiscon-level = <5>; | |
b460ecc0 | 1078 | nvidia,pmc = <&tegra_pmc 1>; |
cc34c9f7 TT |
1079 | status = "disabled"; |
1080 | }; | |
1081 | ||
7d19a34a HD |
1082 | cpus { |
1083 | #address-cells = <1>; | |
1084 | #size-cells = <0>; | |
1085 | ||
13a2a5ea | 1086 | cpu0: cpu@0 { |
7d19a34a HD |
1087 | device_type = "cpu"; |
1088 | compatible = "arm,cortex-a9"; | |
1089 | reg = <0>; | |
663bd487 | 1090 | clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; |
13a2a5ea | 1091 | #cooling-cells = <2>; |
7d19a34a HD |
1092 | }; |
1093 | ||
13a2a5ea | 1094 | cpu1: cpu@1 { |
7d19a34a HD |
1095 | device_type = "cpu"; |
1096 | compatible = "arm,cortex-a9"; | |
1097 | reg = <1>; | |
663bd487 | 1098 | clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; |
13a2a5ea | 1099 | #cooling-cells = <2>; |
7d19a34a HD |
1100 | }; |
1101 | ||
13a2a5ea | 1102 | cpu2: cpu@2 { |
7d19a34a HD |
1103 | device_type = "cpu"; |
1104 | compatible = "arm,cortex-a9"; | |
1105 | reg = <2>; | |
663bd487 | 1106 | clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; |
13a2a5ea | 1107 | #cooling-cells = <2>; |
7d19a34a HD |
1108 | }; |
1109 | ||
13a2a5ea | 1110 | cpu3: cpu@3 { |
7d19a34a HD |
1111 | device_type = "cpu"; |
1112 | compatible = "arm,cortex-a9"; | |
1113 | reg = <3>; | |
663bd487 | 1114 | clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; |
13a2a5ea | 1115 | #cooling-cells = <2>; |
7d19a34a HD |
1116 | }; |
1117 | }; | |
1118 | ||
c04abb3a SW |
1119 | pmu { |
1120 | compatible = "arm,cortex-a9-pmu"; | |
6cecf916 SW |
1121 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
1122 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | |
1123 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, | |
1124 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; | |
2db12b16 MZ |
1125 | interrupt-affinity = <&{/cpus/cpu@0}>, |
1126 | <&{/cpus/cpu@1}>, | |
1127 | <&{/cpus/cpu@2}>, | |
1128 | <&{/cpus/cpu@3}>; | |
54174a33 | 1129 | }; |
13a2a5ea DO |
1130 | |
1131 | thermal-zones { | |
1132 | tsensor0-thermal { | |
1133 | polling-delay-passive = <1000>; /* milliseconds */ | |
1134 | polling-delay = <5000>; /* milliseconds */ | |
1135 | ||
1136 | thermal-sensors = <&tsensor 0>; | |
1137 | ||
1138 | trips { | |
1139 | level1_trip: dvfs-alert { | |
1140 | /* throttle at 80C until temperature drops to 79.8C */ | |
1141 | temperature = <80000>; | |
1142 | hysteresis = <200>; | |
1143 | type = "passive"; | |
1144 | }; | |
1145 | ||
1146 | level2_trip: cpu-div2-throttle { | |
1147 | /* hardware CPU x2 freq throttle at 85C */ | |
1148 | temperature = <85000>; | |
1149 | hysteresis = <200>; | |
1150 | type = "hot"; | |
1151 | }; | |
1152 | ||
1153 | level3_trip: soc-critical { | |
1154 | /* hardware shut down at 90C */ | |
1155 | temperature = <90000>; | |
1156 | hysteresis = <2000>; | |
1157 | type = "critical"; | |
1158 | }; | |
1159 | }; | |
1160 | ||
1161 | cooling-maps { | |
1162 | map0 { | |
1163 | trip = <&level1_trip>; | |
1164 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1165 | <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1166 | <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1167 | <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1168 | <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1169 | }; | |
1170 | }; | |
1171 | }; | |
1172 | ||
1173 | tsensor1-thermal { | |
1174 | status = "disabled"; | |
1175 | ||
1176 | polling-delay-passive = <1000>; /* milliseconds */ | |
1177 | polling-delay = <0>; /* milliseconds */ | |
1178 | ||
1179 | thermal-sensors = <&tsensor 1>; | |
1180 | ||
1181 | trips { | |
1182 | dvfs-alert { | |
1183 | temperature = <80000>; | |
1184 | hysteresis = <200>; | |
1185 | type = "passive"; | |
1186 | }; | |
1187 | }; | |
1188 | }; | |
1189 | }; | |
c3e00a0e | 1190 | }; |