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ARM: tegra: apalis-tk1: Fix high speed UART compatible
[linux-2.6-block.git] / arch / arm / boot / dts / tegra30.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
05849c93 2#include <dt-bindings/clock/tegra30-car.h>
3325f1bc 3#include <dt-bindings/gpio/tegra-gpio.h>
6d9adf6f 4#include <dt-bindings/memory/tegra30-mc.h>
a47c662a 5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 6#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 7
1bd0bd49 8#include "skeleton.dtsi"
c3e00a0e
PDS		 9
10/ {
11 compatible = "nvidia,tegra30";
870c81a4 12 interrupt-parent = <&lic>;
c3e00a0e 13
508d690e 14 pcie@3000 {
e07e3dbd
TR		 15 compatible = "nvidia,tegra30-pcie";
16 device_type = "pci";
17 reg = <0x00003000 0x00000800 /* PADS registers */
18 0x00003800 0x00000200 /* AFI registers */
19 0x10000000 0x10000000>; /* configuration space */
20 reg-names = "pads", "afi", "cs";
21 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
22 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
23 interrupt-names = "intr", "msi";
24
97070bd4
LS		 25 #interrupt-cells = <1>;
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28
e07e3dbd
TR		 29 bus-range = <0x00 0xff>;
30 #address-cells = <3>;
31 #size-cells = <2>;
32
33 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
35 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
36 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 37 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
38 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
e07e3dbd
TR		 39
40 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
41 <&tegra_car TEGRA30_CLK_AFI>,
e07e3dbd
TR		 42 <&tegra_car TEGRA30_CLK_PLL_E>,
43 <&tegra_car TEGRA30_CLK_CML0>;
2bd541ff 44 clock-names = "pex", "afi", "pll_e", "cml";
3393d422 45 resets = <&tegra_car 70>,
d8b316b2
MZ		 46 <&tegra_car 72>,
47 <&tegra_car 74>;
3393d422 48 reset-names = "pex", "afi", "pcie_x";
e07e3dbd
TR		 49 status = "disabled";
50
51 pci@1,0 {
52 device_type = "pci";
53 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
54 reg = <0x000800 0 0 0 0>;
508d690e 55 bus-range = <0x00 0xff>;
e07e3dbd
TR		 56 status = "disabled";
57
58 #address-cells = <3>;
59 #size-cells = <2>;
60 ranges;
61
62 nvidia,num-lanes = <2>;
63 };
64
65 pci@2,0 {
66 device_type = "pci";
67 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
68 reg = <0x001000 0 0 0 0>;
508d690e 69 bus-range = <0x00 0xff>;
e07e3dbd
TR		 70 status = "disabled";
71
72 #address-cells = <3>;
73 #size-cells = <2>;
74 ranges;
75
76 nvidia,num-lanes = <2>;
77 };
78
79 pci@3,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
82 reg = <0x001800 0 0 0 0>;
508d690e 83 bus-range = <0x00 0xff>;
e07e3dbd
TR		 84 status = "disabled";
85
86 #address-cells = <3>;
87 #size-cells = <2>;
88 ranges;
89
90 nvidia,num-lanes = <2>;
91 };
92 };
93
ea857036
DO		 94 iram@40000000 {
95 compatible = "mmio-sram";
96 reg = <0x40000000 0x40000>;
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges = <0 0x40000000 0x40000>;
55f939c2
DO		 100
101 vde_pool: vde@400 {
102 reg = <0x400 0x3fc00>;
103 pool;
104 };
ea857036
DO		 105 };
106
58ecb23f 107 host1x@50000000 {
ed39097c
TR		 108 compatible = "nvidia,tegra30-host1x", "simple-bus";
109 reg = <0x50000000 0x00024000>;
6cecf916
SW		 110 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
111 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
05849c93 112 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
3393d422
SW		 113 resets = <&tegra_car 28>;
114 reset-names = "host1x";
ed39097c
TR		 115
116 #address-cells = <1>;
117 #size-cells = <1>;
118
119 ranges = <0x54000000 0x54000000 0x04000000>;
120
58ecb23f 121 mpe@54040000 {
ed39097c
TR		 122 compatible = "nvidia,tegra30-mpe";
123 reg = <0x54040000 0x00040000>;
6cecf916 124 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
05849c93 125 clocks = <&tegra_car TEGRA30_CLK_MPE>;
3393d422
SW		 126 resets = <&tegra_car 60>;
127 reset-names = "mpe";
ed39097c
TR		 128 };
129
58ecb23f 130 vi@54080000 {
ed39097c
TR		 131 compatible = "nvidia,tegra30-vi";
132 reg = <0x54080000 0x00040000>;
6cecf916 133 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
05849c93 134 clocks = <&tegra_car TEGRA30_CLK_VI>;
3393d422
SW		 135 resets = <&tegra_car 20>;
136 reset-names = "vi";
ed39097c
TR		 137 };
138
58ecb23f 139 epp@540c0000 {
ed39097c
TR		 140 compatible = "nvidia,tegra30-epp";
141 reg = <0x540c0000 0x00040000>;
6cecf916 142 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
05849c93 143 clocks = <&tegra_car TEGRA30_CLK_EPP>;
3393d422
SW		 144 resets = <&tegra_car 19>;
145 reset-names = "epp";
ed39097c
TR		 146 };
147
58ecb23f 148 isp@54100000 {
ed39097c
TR		 149 compatible = "nvidia,tegra30-isp";
150 reg = <0x54100000 0x00040000>;
6cecf916 151 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
05849c93 152 clocks = <&tegra_car TEGRA30_CLK_ISP>;
3393d422
SW		 153 resets = <&tegra_car 23>;
154 reset-names = "isp";
ed39097c
TR		 155 };
156
58ecb23f 157 gr2d@54140000 {
ed39097c
TR		 158 compatible = "nvidia,tegra30-gr2d";
159 reg = <0x54140000 0x00040000>;
6cecf916 160 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
da45d738 161 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
3393d422
SW		 162 resets = <&tegra_car 21>;
163 reset-names = "2d";
ed39097c
TR		 164 };
165
58ecb23f 166 gr3d@54180000 {
ed39097c
TR		 167 compatible = "nvidia,tegra30-gr3d";
168 reg = <0x54180000 0x00040000>;
c71d3909
TR		 169 clocks = <&tegra_car TEGRA30_CLK_GR3D
170 &tegra_car TEGRA30_CLK_GR3D2>;
1cbc733d 171 clock-names = "3d", "3d2";
3393d422 172 resets = <&tegra_car 24>,
d8b316b2 173 <&tegra_car 98>;
3393d422 174 reset-names = "3d", "3d2";
ed39097c
TR		 175 };
176
177 dc@54200000 {
05465f4e 178 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
ed39097c 179 reg = <0x54200000 0x00040000>;
6cecf916 180 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 181 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
182 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 183 clock-names = "dc", "parent";
3393d422
SW		 184 resets = <&tegra_car 27>;
185 reset-names = "dc";
ed39097c 186
6d9adf6f
TR		 187 iommus = <&mc TEGRA_SWGROUP_DC>;
188
688b56b4
TR		 189 nvidia,head = <0>;
190
ed39097c
TR		 191 rgb {
192 status = "disabled";
193 };
194 };
195
196 dc@54240000 {
197 compatible = "nvidia,tegra30-dc";
198 reg = <0x54240000 0x00040000>;
6cecf916 199 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 200 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
201 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 202 clock-names = "dc", "parent";
3393d422
SW		 203 resets = <&tegra_car 26>;
204 reset-names = "dc";
ed39097c 205
6d9adf6f
TR		 206 iommus = <&mc TEGRA_SWGROUP_DCB>;
207
688b56b4
TR		 208 nvidia,head = <1>;
209
ed39097c
TR		 210 rgb {
211 status = "disabled";
212 };
213 };
214
58ecb23f 215 hdmi@54280000 {
ed39097c
TR		 216 compatible = "nvidia,tegra30-hdmi";
217 reg = <0x54280000 0x00040000>;
6cecf916 218 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 219 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
220 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
1cbc733d 221 clock-names = "hdmi", "parent";
3393d422
SW		 222 resets = <&tegra_car 51>;
223 reset-names = "hdmi";
ed39097c
TR		 224 status = "disabled";
225 };
226
58ecb23f 227 tvo@542c0000 {
ed39097c
TR		 228 compatible = "nvidia,tegra30-tvo";
229 reg = <0x542c0000 0x00040000>;
6cecf916 230 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
05849c93 231 clocks = <&tegra_car TEGRA30_CLK_TVO>;
ed39097c
TR		 232 status = "disabled";
233 };
234
58ecb23f 235 dsi@54300000 {
ed39097c
TR		 236 compatible = "nvidia,tegra30-dsi";
237 reg = <0x54300000 0x00040000>;
05849c93 238 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
3393d422
SW		 239 resets = <&tegra_car 48>;
240 reset-names = "dsi";
ed39097c
TR		 241 status = "disabled";
242 };
243 };
244
2cda1880 245 timer@50040600 {
73368ba0
SW		 246 compatible = "arm,cortex-a9-twd-timer";
247 reg = <0x50040600 0x20>;
870c81a4 248 interrupt-parent = <&intc>;
6cecf916 249 interrupts = <GIC_PPI 13
e7d9b270 250 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
05849c93 251 clocks = <&tegra_car TEGRA30_CLK_TWD>;
73368ba0
SW		 252 };
253
58ecb23f 254 intc: interrupt-controller@50041000 {
c3e00a0e 255 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 256 reg = <0x50041000 0x1000
257 0x50040100 0x0100>;
2eaab06e
SW		 258 interrupt-controller;
259 #interrupt-cells = <3>;
870c81a4 260 interrupt-parent = <&intc>;
c3e00a0e
PDS		 261 };
262
58ecb23f 263 cache-controller@50043000 {
bb2c1de9
SW		 264 compatible = "arm,pl310-cache";
265 reg = <0x50043000 0x1000>;
266 arm,data-latency = <6 6 2>;
267 arm,tag-latency = <5 5 2>;
268 cache-unified;
269 cache-level = <2>;
270 };
271
870c81a4
MZ		 272 lic: interrupt-controller@60004000 {
273 compatible = "nvidia,tegra30-ictlr";
274 reg = <0x60004000 0x100>,
275 <0x60004100 0x50>,
276 <0x60004200 0x50>,
277 <0x60004300 0x50>,
278 <0x60004400 0x50>;
279 interrupt-controller;
280 #interrupt-cells = <3>;
281 interrupt-parent = <&intc>;
282 };
283
2f2b7fb2
SW		 284 timer@60005000 {
285 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
286 reg = <0x60005000 0x400>;
6cecf916
SW		 287 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
05849c93 293 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
2f2b7fb2
SW		 294 };
295
58ecb23f 296 tegra_car: clock@60006000 {
95985667
PG		 297 compatible = "nvidia,tegra30-car";
298 reg = <0x60006000 0x1000>;
299 #clock-cells = <1>;
3393d422 300 #reset-cells = <1>;
95985667
PG		 301 };
302
b1023134
TR		 303 flow-controller@60007000 {
304 compatible = "nvidia,tegra30-flowctrl";
305 reg = <0x60007000 0x1000>;
306 };
307
58ecb23f 308 apbdma: dma@6000a000 {
8051b75a
SW		 309 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
310 reg = <0x6000a000 0x1400>;
6cecf916
SW		 311 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
05849c93 343 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
3393d422
SW		 344 resets = <&tegra_car 34>;
345 reset-names = "dma";
034d023f 346 #dma-cells = <1>;
8051b75a
SW		 347 };
348
0d5ccb38 349 ahb: ahb@6000c000 {
c04abb3a 350 compatible = "nvidia,tegra30-ahb";
0d5ccb38 351 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e
PDS		 352 };
353
58ecb23f 354 gpio: gpio@6000d000 {
35f210ec 355 compatible = "nvidia,tegra30-gpio";
95decf84 356 reg = <0x6000d000 0x1000>;
6cecf916
SW		 357 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e
PDS		 365 #gpio-cells = <2>;
366 gpio-controller;
6f74dc9b
SW		 367 #interrupt-cells = <2>;
368 interrupt-controller;
4f1d8414 369 /*
17cdddf0 370 gpio-ranges = <&pinmux 0 0 248>;
4f1d8414 371 */
c3e00a0e
PDS		 372 };
373
55f939c2
DO		 374 vde@6001a000 {
375 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
376 reg = <0x6001a000 0x1000 /* Syntax Engine */
377 0x6001b000 0x1000 /* Video Bitstream Engine */
378 0x6001c000 0x100 /* Macroblock Engine */
379 0x6001c200 0x100 /* Post-processing Engine */
380 0x6001c400 0x100 /* Motion Compensation Engine */
381 0x6001c600 0x100 /* Transform Engine */
382 0x6001c800 0x100 /* Pixel prediction block */
383 0x6001ca00 0x100 /* Video DMA */
384 0x6001d800 0x400>; /* Video frame controls */
385 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
386 "tfe", "ppb", "vdma", "frameid";
387 iram = <&vde_pool>; /* IRAM region */
388 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
389 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
390 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
391 interrupt-names = "sync-token", "bsev", "sxe";
392 clocks = <&tegra_car TEGRA30_CLK_VDE>;
393 resets = <&tegra_car 61>;
394 };
395
155dfc7b
PDS		 396 apbmisc@70000800 {
397 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
398 reg = <0x70000800 0x64 /* Chip revision */
399 0x70000008 0x04>; /* Strapping options */
400 };
401
58ecb23f 402 pinmux: pinmux@70000868 {
c04abb3a 403 compatible = "nvidia,tegra30-pinmux";
322337b8
PR		 404 reg = <0x70000868 0xd4 /* Pad control registers */
405 0x70003000 0x3e4>; /* Mux registers */
c04abb3a
SW		 406 };
407
b6551bb9
LD		 408 /*
409 * There are two serial driver i.e. 8250 based simple serial
410 * driver and APB DMA based serial driver for higher baudrate
411 * and performace. To enable the 8250 based driver, the compatible
412 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
e1098248 413 * the APB DMA based serial driver, the compatible is
b6551bb9
LD		 414 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
415 */
416 uarta: serial@70006000 {
c3e00a0e
PDS		 417 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
418 reg = <0x70006000 0x40>;
419 reg-shift = <2>;
6cecf916 420 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
05849c93 421 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
3393d422
SW		 422 resets = <&tegra_car 6>;
423 reset-names = "serial";
034d023f
SW		 424 dmas = <&apbdma 8>, <&apbdma 8>;
425 dma-names = "rx", "tx";
223ef78d 426 status = "disabled";
c3e00a0e
PDS		 427 };
428
b6551bb9 429 uartb: serial@70006040 {
c3e00a0e
PDS		 430 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
431 reg = <0x70006040 0x40>;
432 reg-shift = <2>;
6cecf916 433 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
05849c93 434 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
3393d422
SW		 435 resets = <&tegra_car 7>;
436 reset-names = "serial";
034d023f
SW		 437 dmas = <&apbdma 9>, <&apbdma 9>;
438 dma-names = "rx", "tx";
223ef78d 439 status = "disabled";
c3e00a0e
PDS		 440 };
441
b6551bb9 442 uartc: serial@70006200 {
c3e00a0e
PDS		 443 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
444 reg = <0x70006200 0x100>;
445 reg-shift = <2>;
6cecf916 446 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
05849c93 447 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
3393d422
SW		 448 resets = <&tegra_car 55>;
449 reset-names = "serial";
034d023f
SW		 450 dmas = <&apbdma 10>, <&apbdma 10>;
451 dma-names = "rx", "tx";
223ef78d 452 status = "disabled";
c3e00a0e
PDS		 453 };
454
b6551bb9 455 uartd: serial@70006300 {
c3e00a0e
PDS		 456 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
457 reg = <0x70006300 0x100>;
458 reg-shift = <2>;
6cecf916 459 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
05849c93 460 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
3393d422
SW		 461 resets = <&tegra_car 65>;
462 reset-names = "serial";
034d023f
SW		 463 dmas = <&apbdma 19>, <&apbdma 19>;
464 dma-names = "rx", "tx";
223ef78d 465 status = "disabled";
c3e00a0e
PDS		 466 };
467
b6551bb9 468 uarte: serial@70006400 {
c3e00a0e
PDS		 469 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
470 reg = <0x70006400 0x100>;
471 reg-shift = <2>;
6cecf916 472 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
05849c93 473 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
3393d422
SW		 474 resets = <&tegra_car 66>;
475 reset-names = "serial";
034d023f
SW		 476 dmas = <&apbdma 20>, <&apbdma 20>;
477 dma-names = "rx", "tx";
223ef78d 478 status = "disabled";
c3e00a0e
PDS		 479 };
480
5e35c1f0
MK		 481 gmi@70009000 {
482 compatible = "nvidia,tegra30-gmi";
483 reg = <0x70009000 0x1000>;
484 #address-cells = <2>;
485 #size-cells = <1>;
486 ranges = <0 0 0x48000000 0x7ffffff>;
487 clocks = <&tegra_car TEGRA30_CLK_NOR>;
488 clock-names = "gmi";
489 resets = <&tegra_car 42>;
490 reset-names = "gmi";
491 status = "disabled";
492 };
493
58ecb23f 494 pwm: pwm@7000a000 {
140fd977
TR		 495 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
496 reg = <0x7000a000 0x100>;
497 #pwm-cells = <2>;
05849c93 498 clocks = <&tegra_car TEGRA30_CLK_PWM>;
3393d422
SW		 499 resets = <&tegra_car 17>;
500 reset-names = "pwm";
b69cd984 501 status = "disabled";
140fd977
TR		 502 };
503
58ecb23f 504 rtc@7000e000 {
380e04ac
SW		 505 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
506 reg = <0x7000e000 0x100>;
6cecf916 507 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
05849c93 508 clocks = <&tegra_car TEGRA30_CLK_RTC>;
380e04ac
SW		 509 };
510
c04abb3a 511 i2c@7000c000 {
d8b316b2 512 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a 513 reg = <0x7000c000 0x100>;
6cecf916 514 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 515 #address-cells = <1>;
516 #size-cells = <0>;
05849c93
HD		 517 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
518 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 519 clock-names = "div-clk", "fast-clk";
3393d422
SW		 520 resets = <&tegra_car 12>;
521 reset-names = "i2c";
034d023f
SW		 522 dmas = <&apbdma 21>, <&apbdma 21>;
523 dma-names = "rx", "tx";
223ef78d 524 status = "disabled";
c3e00a0e
PDS		 525 };
526
c04abb3a 527 i2c@7000c400 {
c04abb3a
SW		 528 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
529 reg = <0x7000c400 0x100>;
6cecf916 530 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 531 #address-cells = <1>;
532 #size-cells = <0>;
05849c93
HD		 533 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
534 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 535 clock-names = "div-clk", "fast-clk";
3393d422
SW		 536 resets = <&tegra_car 54>;
537 reset-names = "i2c";
034d023f
SW		 538 dmas = <&apbdma 22>, <&apbdma 22>;
539 dma-names = "rx", "tx";
223ef78d 540 status = "disabled";
c3e00a0e
PDS		 541 };
542
c04abb3a 543 i2c@7000c500 {
c04abb3a
SW		 544 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
545 reg = <0x7000c500 0x100>;
6cecf916 546 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 547 #address-cells = <1>;
548 #size-cells = <0>;
05849c93
HD		 549 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
550 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 551 clock-names = "div-clk", "fast-clk";
3393d422
SW		 552 resets = <&tegra_car 67>;
553 reset-names = "i2c";
034d023f
SW		 554 dmas = <&apbdma 23>, <&apbdma 23>;
555 dma-names = "rx", "tx";
223ef78d 556 status = "disabled";
c3e00a0e
PDS		 557 };
558
c04abb3a 559 i2c@7000c700 {
c04abb3a
SW		 560 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
561 reg = <0x7000c700 0x100>;
6cecf916 562 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 563 #address-cells = <1>;
564 #size-cells = <0>;
05849c93
HD		 565 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
566 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
3393d422
SW		 567 resets = <&tegra_car 103>;
568 reset-names = "i2c";
1cbc733d 569 clock-names = "div-clk", "fast-clk";
034d023f
SW		 570 dmas = <&apbdma 26>, <&apbdma 26>;
571 dma-names = "rx", "tx";
223ef78d 572 status = "disabled";
c3e00a0e
PDS		 573 };
574
c04abb3a 575 i2c@7000d000 {
c04abb3a
SW		 576 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
577 reg = <0x7000d000 0x100>;
6cecf916 578 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 579 #address-cells = <1>;
580 #size-cells = <0>;
05849c93
HD		 581 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
582 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 583 clock-names = "div-clk", "fast-clk";
3393d422
SW		 584 resets = <&tegra_car 47>;
585 reset-names = "i2c";
034d023f
SW		 586 dmas = <&apbdma 24>, <&apbdma 24>;
587 dma-names = "rx", "tx";
223ef78d 588 status = "disabled";
c04abb3a
SW		 589 };
590
a86b0db3
LD		 591 spi@7000d400 {
592 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
593 reg = <0x7000d400 0x200>;
6cecf916 594 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 595 #address-cells = <1>;
596 #size-cells = <0>;
05849c93 597 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
3393d422
SW		 598 resets = <&tegra_car 41>;
599 reset-names = "spi";
034d023f
SW		 600 dmas = <&apbdma 15>, <&apbdma 15>;
601 dma-names = "rx", "tx";
a86b0db3
LD		 602 status = "disabled";
603 };
604
605 spi@7000d600 {
606 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
607 reg = <0x7000d600 0x200>;
6cecf916 608 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 609 #address-cells = <1>;
610 #size-cells = <0>;
05849c93 611 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
3393d422
SW		 612 resets = <&tegra_car 44>;
613 reset-names = "spi";
034d023f
SW		 614 dmas = <&apbdma 16>, <&apbdma 16>;
615 dma-names = "rx", "tx";
a86b0db3
LD		 616 status = "disabled";
617 };
618
619 spi@7000d800 {
620 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d 621 reg = <0x7000d800 0x200>;
6cecf916 622 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 623 #address-cells = <1>;
624 #size-cells = <0>;
05849c93 625 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
3393d422
SW		 626 resets = <&tegra_car 46>;
627 reset-names = "spi";
034d023f
SW		 628 dmas = <&apbdma 17>, <&apbdma 17>;
629 dma-names = "rx", "tx";
a86b0db3
LD		 630 status = "disabled";
631 };
632
633 spi@7000da00 {
634 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
635 reg = <0x7000da00 0x200>;
6cecf916 636 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 637 #address-cells = <1>;
638 #size-cells = <0>;
05849c93 639 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
3393d422
SW		 640 resets = <&tegra_car 68>;
641 reset-names = "spi";
034d023f
SW		 642 dmas = <&apbdma 18>, <&apbdma 18>;
643 dma-names = "rx", "tx";
a86b0db3
LD		 644 status = "disabled";
645 };
646
647 spi@7000dc00 {
648 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
649 reg = <0x7000dc00 0x200>;
6cecf916 650 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 651 #address-cells = <1>;
652 #size-cells = <0>;
05849c93 653 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
3393d422
SW		 654 resets = <&tegra_car 104>;
655 reset-names = "spi";
034d023f
SW		 656 dmas = <&apbdma 27>, <&apbdma 27>;
657 dma-names = "rx", "tx";
a86b0db3
LD		 658 status = "disabled";
659 };
660
661 spi@7000de00 {
662 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
663 reg = <0x7000de00 0x200>;
6cecf916 664 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 665 #address-cells = <1>;
666 #size-cells = <0>;
05849c93 667 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
3393d422
SW		 668 resets = <&tegra_car 106>;
669 reset-names = "spi";
034d023f
SW		 670 dmas = <&apbdma 28>, <&apbdma 28>;
671 dma-names = "rx", "tx";
a86b0db3
LD		 672 status = "disabled";
673 };
674
58ecb23f 675 kbc@7000e200 {
699ed4b9
LD		 676 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
677 reg = <0x7000e200 0x100>;
6cecf916 678 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
05849c93 679 clocks = <&tegra_car TEGRA30_CLK_KBC>;
3393d422
SW		 680 resets = <&tegra_car 36>;
681 reset-names = "kbc";
699ed4b9
LD		 682 status = "disabled";
683 };
684
58ecb23f 685 pmc@7000e400 {
2b84e53b 686 compatible = "nvidia,tegra30-pmc";
c04abb3a 687 reg = <0x7000e400 0x400>;
05849c93 688 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
7021d122 689 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 690 };
691
a9fe468f 692 mc: memory-controller@7000f000 {
c04abb3a 693 compatible = "nvidia,tegra30-mc";
a9fe468f
TR		 694 reg = <0x7000f000 0x400>;
695 clocks = <&tegra_car TEGRA30_CLK_MC>;
696 clock-names = "mc";
697
6cecf916 698 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a 699
a9fe468f 700 #iommu-cells = <1>;
c3e00a0e 701 };
9ee6a5c4 702
155dfc7b
PDS		 703 fuse@7000f800 {
704 compatible = "nvidia,tegra30-efuse";
705 reg = <0x7000f800 0x400>;
706 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
707 clock-names = "fuse";
708 resets = <&tegra_car 39>;
709 reset-names = "fuse";
710 };
711
cbee2613
MZ		 712 hda@70030000 {
713 compatible = "nvidia,tegra30-hda";
714 reg = <0x70030000 0x10000>;
715 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&tegra_car TEGRA30_CLK_HDA>,
d8b316b2 717 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
cbee2613
MZ		 718 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
719 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
720 resets = <&tegra_car 125>, /* hda */
721 <&tegra_car 128>, /* hda2hdmi */
722 <&tegra_car 111>; /* hda2codec_2x */
723 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
724 status = "disabled";
725 };
726
58ecb23f 727 ahub@70080000 {
9ee6a5c4 728 compatible = "nvidia,tegra30-ahub";
5ff48887
SW		 729 reg = <0x70080000 0x200
730 0x70080200 0x100>;
6cecf916 731 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
05849c93 732 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
2bd541ff
SW		 733 <&tegra_car TEGRA30_CLK_APBIF>;
734 clock-names = "d_audio", "apbif";
3393d422
SW		 735 resets = <&tegra_car 106>, /* d_audio */
736 <&tegra_car 107>, /* apbif */
737 <&tegra_car 30>, /* i2s0 */
738 <&tegra_car 11>, /* i2s1 */
739 <&tegra_car 18>, /* i2s2 */
740 <&tegra_car 101>, /* i2s3 */
741 <&tegra_car 102>, /* i2s4 */
742 <&tegra_car 108>, /* dam0 */
743 <&tegra_car 109>, /* dam1 */
744 <&tegra_car 110>, /* dam2 */
745 <&tegra_car 10>; /* spdif */
746 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
747 "i2s3", "i2s4", "dam0", "dam1", "dam2",
748 "spdif";
034d023f
SW		 749 dmas = <&apbdma 1>, <&apbdma 1>,
750 <&apbdma 2>, <&apbdma 2>,
751 <&apbdma 3>, <&apbdma 3>,
752 <&apbdma 4>, <&apbdma 4>;
753 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
754 "rx3", "tx3";
9ee6a5c4
SW		 755 ranges;
756 #address-cells = <1>;
757 #size-cells = <1>;
758
759 tegra_i2s0: i2s@70080300 {
760 compatible = "nvidia,tegra30-i2s";
761 reg = <0x70080300 0x100>;
762 nvidia,ahub-cif-ids = <4 4>;
05849c93 763 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
3393d422
SW		 764 resets = <&tegra_car 30>;
765 reset-names = "i2s";
223ef78d 766 status = "disabled";
9ee6a5c4
SW		 767 };
768
769 tegra_i2s1: i2s@70080400 {
770 compatible = "nvidia,tegra30-i2s";
771 reg = <0x70080400 0x100>;
772 nvidia,ahub-cif-ids = <5 5>;
05849c93 773 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
3393d422
SW		 774 resets = <&tegra_car 11>;
775 reset-names = "i2s";
223ef78d 776 status = "disabled";
9ee6a5c4
SW		 777 };
778
779 tegra_i2s2: i2s@70080500 {
780 compatible = "nvidia,tegra30-i2s";
781 reg = <0x70080500 0x100>;
782 nvidia,ahub-cif-ids = <6 6>;
05849c93 783 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
3393d422
SW		 784 resets = <&tegra_car 18>;
785 reset-names = "i2s";
223ef78d 786 status = "disabled";
9ee6a5c4
SW		 787 };
788
789 tegra_i2s3: i2s@70080600 {
790 compatible = "nvidia,tegra30-i2s";
791 reg = <0x70080600 0x100>;
792 nvidia,ahub-cif-ids = <7 7>;
05849c93 793 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
3393d422
SW		 794 resets = <&tegra_car 101>;
795 reset-names = "i2s";
223ef78d 796 status = "disabled";
9ee6a5c4
SW		 797 };
798
799 tegra_i2s4: i2s@70080700 {
800 compatible = "nvidia,tegra30-i2s";
801 reg = <0x70080700 0x100>;
802 nvidia,ahub-cif-ids = <8 8>;
05849c93 803 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
3393d422
SW		 804 resets = <&tegra_car 102>;
805 reset-names = "i2s";
223ef78d 806 status = "disabled";
9ee6a5c4
SW		 807 };
808 };
7868a9bc 809
c04abb3a
SW		 810 sdhci@78000000 {
811 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
812 reg = <0x78000000 0x200>;
6cecf916 813 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
05849c93 814 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
3393d422
SW		 815 resets = <&tegra_car 14>;
816 reset-names = "sdhci";
223ef78d 817 status = "disabled";
7868a9bc 818 };
ecf43742 819
c04abb3a
SW		 820 sdhci@78000200 {
821 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
822 reg = <0x78000200 0x200>;
6cecf916 823 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
05849c93 824 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
3393d422
SW		 825 resets = <&tegra_car 9>;
826 reset-names = "sdhci";
223ef78d 827 status = "disabled";
ecf43742 828 };
54174a33 829
c04abb3a
SW		 830 sdhci@78000400 {
831 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
832 reg = <0x78000400 0x200>;
6cecf916 833 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
05849c93 834 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
3393d422
SW		 835 resets = <&tegra_car 69>;
836 reset-names = "sdhci";
223ef78d 837 status = "disabled";
c04abb3a
SW		 838 };
839
840 sdhci@78000600 {
841 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
842 reg = <0x78000600 0x200>;
6cecf916 843 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
05849c93 844 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
3393d422
SW		 845 resets = <&tegra_car 15>;
846 reset-names = "sdhci";
223ef78d 847 status = "disabled";
c04abb3a
SW		 848 };
849
cc34c9f7
TT		 850 usb@7d000000 {
851 compatible = "nvidia,tegra30-ehci", "usb-ehci";
852 reg = <0x7d000000 0x4000>;
853 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
854 phy_type = "utmi";
855 clocks = <&tegra_car TEGRA30_CLK_USBD>;
3393d422
SW		 856 resets = <&tegra_car 22>;
857 reset-names = "usb";
cc34c9f7
TT		 858 nvidia,needs-double-reset;
859 nvidia,phy = <&phy1>;
860 status = "disabled";
861 };
862
863 phy1: usb-phy@7d000000 {
864 compatible = "nvidia,tegra30-usb-phy";
865 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
866 phy_type = "utmi";
867 clocks = <&tegra_car TEGRA30_CLK_USBD>,
868 <&tegra_car TEGRA30_CLK_PLL_U>,
869 <&tegra_car TEGRA30_CLK_USBD>;
870 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 871 resets = <&tegra_car 22>, <&tegra_car 22>;
872 reset-names = "usb", "utmi-pads";
cc34c9f7
TT		 873 nvidia,hssync-start-delay = <9>;
874 nvidia,idle-wait-delay = <17>;
875 nvidia,elastic-limit = <16>;
876 nvidia,term-range-adj = <6>;
877 nvidia,xcvr-setup = <51>;
878 nvidia.xcvr-setup-use-fuses;
879 nvidia,xcvr-lsfslew = <1>;
880 nvidia,xcvr-lsrslew = <1>;
881 nvidia,xcvr-hsslew = <32>;
882 nvidia,hssquelch-level = <2>;
883 nvidia,hsdiscon-level = <5>;
308efde2 884 nvidia,has-utmi-pad-registers;
cc34c9f7
TT		 885 status = "disabled";
886 };
887
888 usb@7d004000 {
889 compatible = "nvidia,tegra30-ehci", "usb-ehci";
890 reg = <0x7d004000 0x4000>;
891 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
fd6441ec 892 phy_type = "utmi";
cc34c9f7 893 clocks = <&tegra_car TEGRA30_CLK_USB2>;
3393d422
SW		 894 resets = <&tegra_car 58>;
895 reset-names = "usb";
cc34c9f7
TT		 896 nvidia,phy = <&phy2>;
897 status = "disabled";
898 };
899
900 phy2: usb-phy@7d004000 {
901 compatible = "nvidia,tegra30-usb-phy";
fd6441ec
EB		 902 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
903 phy_type = "utmi";
cc34c9f7
TT		 904 clocks = <&tegra_car TEGRA30_CLK_USB2>,
905 <&tegra_car TEGRA30_CLK_PLL_U>,
fd6441ec
EB		 906 <&tegra_car TEGRA30_CLK_USBD>;
907 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 908 resets = <&tegra_car 58>, <&tegra_car 22>;
909 reset-names = "usb", "utmi-pads";
fd6441ec
EB		 910 nvidia,hssync-start-delay = <9>;
911 nvidia,idle-wait-delay = <17>;
912 nvidia,elastic-limit = <16>;
913 nvidia,term-range-adj = <6>;
914 nvidia,xcvr-setup = <51>;
915 nvidia.xcvr-setup-use-fuses;
916 nvidia,xcvr-lsfslew = <2>;
917 nvidia,xcvr-lsrslew = <2>;
918 nvidia,xcvr-hsslew = <32>;
919 nvidia,hssquelch-level = <2>;
920 nvidia,hsdiscon-level = <5>;
cc34c9f7
TT		 921 status = "disabled";
922 };
923
924 usb@7d008000 {
925 compatible = "nvidia,tegra30-ehci", "usb-ehci";
926 reg = <0x7d008000 0x4000>;
927 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
928 phy_type = "utmi";
929 clocks = <&tegra_car TEGRA30_CLK_USB3>;
3393d422
SW		 930 resets = <&tegra_car 59>;
931 reset-names = "usb";
cc34c9f7
TT		 932 nvidia,phy = <&phy3>;
933 status = "disabled";
934 };
935
936 phy3: usb-phy@7d008000 {
937 compatible = "nvidia,tegra30-usb-phy";
938 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
939 phy_type = "utmi";
940 clocks = <&tegra_car TEGRA30_CLK_USB3>,
941 <&tegra_car TEGRA30_CLK_PLL_U>,
942 <&tegra_car TEGRA30_CLK_USBD>;
943 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 944 resets = <&tegra_car 59>, <&tegra_car 22>;
945 reset-names = "usb", "utmi-pads";
cc34c9f7
TT		 946 nvidia,hssync-start-delay = <0>;
947 nvidia,idle-wait-delay = <17>;
948 nvidia,elastic-limit = <16>;
949 nvidia,term-range-adj = <6>;
950 nvidia,xcvr-setup = <51>;
951 nvidia.xcvr-setup-use-fuses;
952 nvidia,xcvr-lsfslew = <2>;
953 nvidia,xcvr-lsrslew = <2>;
954 nvidia,xcvr-hsslew = <32>;
955 nvidia,hssquelch-level = <2>;
956 nvidia,hsdiscon-level = <5>;
957 status = "disabled";
958 };
959
7d19a34a
HD		 960 cpus {
961 #address-cells = <1>;
962 #size-cells = <0>;
963
964 cpu@0 {
965 device_type = "cpu";
966 compatible = "arm,cortex-a9";
967 reg = <0>;
968 };
969
970 cpu@1 {
971 device_type = "cpu";
972 compatible = "arm,cortex-a9";
973 reg = <1>;
974 };
975
976 cpu@2 {
977 device_type = "cpu";
978 compatible = "arm,cortex-a9";
979 reg = <2>;
980 };
981
982 cpu@3 {
983 device_type = "cpu";
984 compatible = "arm,cortex-a9";
985 reg = <3>;
986 };
987 };
988
c04abb3a
SW		 989 pmu {
990 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 991 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
54174a33 995 };
c3e00a0e 996};
Linux 6.x block layer and io_uring tree(s)