[linux-2.6-block.git] / arch / arm / boot / dts / tegra30.dtsi

#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra30";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
		serial4 = &uarte;
	};

	host1x {
		compatible = "nvidia,tegra30-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
		clocks = <&tegra_car 28>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra30-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car 60>;
		};

		vi {
			compatible = "nvidia,tegra30-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car 164>;
		};

		epp {
			compatible = "nvidia,tegra30-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car 19>;
		};

		isp {
			compatible = "nvidia,tegra30-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car 23>;
		};

		gr2d {
			compatible = "nvidia,tegra30-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car 21>;
		};

		gr3d {
			compatible = "nvidia,tegra30-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car 24 &tegra_car 98>;
			clock-names = "3d", "3d2";
		};

		dc@54200000 {
			compatible = "nvidia,tegra30-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car 27>, <&tegra_car 179>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra30-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car 26>, <&tegra_car 179>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra30-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car 51>, <&tegra_car 189>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra30-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car 169>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra30-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car 48>;
			status = "disabled";
		};
	};

	timer@50004600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clocks = <&tegra_car 214>;
	};

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <6 6 2>;
		arm,tag-latency = <5 5 2>;
		cache-unified;
		cache-level = <2>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
		reg = <0x60005000 0x400>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 5>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra30-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1400>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 34>;
	};

	ahb: ahb {
		compatible = "nvidia,tegra30-ahb";
		reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra30-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra30-pinmux";
		reg = <0x70000868 0xd4    /* Pad control registers */
		       0x70003000 0x3e4>; /* Mux registers */
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
	 * the APB DMA based serial driver, the comptible is
	 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 8>;
		clocks = <&tegra_car 6>;
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 9>;
		clocks = <&tegra_car 160>;
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 10>;
		clocks = <&tegra_car 55>;
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 19>;
		clocks = <&tegra_car 65>;
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 20>;
		clocks = <&tegra_car 66>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
		status = "disabled";
	};

	rtc {
		compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 4>;
	};

	i2c@7000c000 {
		compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c700 0x100>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 103>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000d000 0x100>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d800 0x200>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		status = "disabled";
	};

	spi@7000dc00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000dc00 0x200>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 27>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 104>;
		status = "disabled";
	};

	spi@7000de00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000de00 0x200>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 28>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 105>;
		status = "disabled";
	};

	kbc {
		compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
		reg = <0x7000e200 0x100>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 36>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra30-pmc";
		reg = <0x7000e400 0x400>;
		clocks = <&tegra_car 218>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
	};

	memory-controller {
		compatible = "nvidia,tegra30-mc";
		reg = <0x7000f000 0x010
		       0x7000f03c 0x1b4
		       0x7000f200 0x028
		       0x7000f284 0x17c>;
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu {
		compatible = "nvidia,tegra30-smmu";
		reg = <0x7000f010 0x02c
		       0x7000f1f0 0x010
		       0x7000f228 0x05c>;
		nvidia,#asids = <4>;		/* # of ASIDs */
		dma-window = <0 0x40000000>;	/* IOVA start & length */
		nvidia,ahb = <&ahb>;
	};

	ahub {
		compatible = "nvidia,tegra30-ahub";
		reg = <0x70080000 0x200
		       0x70080200 0x100>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
			 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
			 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
			 <&tegra_car 110>, <&tegra_car 162>;
		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
			      "spdif_in";
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		tegra_i2s0: i2s@70080300 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080300 0x100>;
			nvidia,ahub-cif-ids = <4 4>;
			clocks = <&tegra_car 30>;
			status = "disabled";
		};

		tegra_i2s1: i2s@70080400 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080400 0x100>;
			nvidia,ahub-cif-ids = <5 5>;
			clocks = <&tegra_car 11>;
			status = "disabled";
		};

		tegra_i2s2: i2s@70080500 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080500 0x100>;
			nvidia,ahub-cif-ids = <6 6>;
			clocks = <&tegra_car 18>;
			status = "disabled";
		};

		tegra_i2s3: i2s@70080600 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080600 0x100>;
			nvidia,ahub-cif-ids = <7 7>;
			clocks = <&tegra_car 101>;
			status = "disabled";
		};

		tegra_i2s4: i2s@70080700 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080700 0x100>;
			nvidia,ahub-cif-ids = <8 8>;
			clocks = <&tegra_car 102>;
			status = "disabled";
		};
	};

	sdhci@78000000 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000000 0x200>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 14>;
		status = "disabled";
	};

	sdhci@78000200 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000200 0x200>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 9>;
		status = "disabled";
	};

	sdhci@78000400 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000400 0x200>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 69>;
		status = "disabled";
	};

	sdhci@78000600 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000600 0x200>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 15>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
	};
};
Commit	Line	Data
3325f1bc	1	#include <dt-bindings/gpio/tegra-gpio.h>
6cecf916	2	#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc	3
1bd0bd49	4	#include "skeleton.dtsi"
c3e00a0e PDS	5
	6	/ {
	7	compatible = "nvidia,tegra30";
	8	interrupt-parent = <&intc>;
	9
b6551bb9 LD	10	aliases {
	11	serial0 = &uarta;
	12	serial1 = &uartb;
	13	serial2 = &uartc;
	14	serial3 = &uartd;
	15	serial4 = &uarte;
	16	};
	17
ed39097c TR	18	host1x {
	19	compatible = "nvidia,tegra30-host1x", "simple-bus";
	20	reg = <0x50000000 0x00024000>;
6cecf916 SW	21	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
6cecf916 SW	22	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
1cbc733d	23	clocks = <&tegra_car 28>;
ed39097c TR	24
	25	#address-cells = <1>;
	26	#size-cells = <1>;
	27
	28	ranges = <0x54000000 0x54000000 0x04000000>;
	29
	30	mpe {
	31	compatible = "nvidia,tegra30-mpe";
	32	reg = <0x54040000 0x00040000>;
6cecf916	33	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d	34	clocks = <&tegra_car 60>;
ed39097c TR	35	};
	36
	37	vi {
	38	compatible = "nvidia,tegra30-vi";
	39	reg = <0x54080000 0x00040000>;
6cecf916	40	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d	41	clocks = <&tegra_car 164>;
ed39097c TR	42	};
	43
	44	epp {
	45	compatible = "nvidia,tegra30-epp";
	46	reg = <0x540c0000 0x00040000>;
6cecf916	47	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d	48	clocks = <&tegra_car 19>;
ed39097c TR	49	};
	50
	51	isp {
	52	compatible = "nvidia,tegra30-isp";
	53	reg = <0x54100000 0x00040000>;
6cecf916	54	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d	55	clocks = <&tegra_car 23>;
ed39097c TR	56	};
	57
	58	gr2d {
	59	compatible = "nvidia,tegra30-gr2d";
	60	reg = <0x54140000 0x00040000>;
6cecf916	61	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d	62	clocks = <&tegra_car 21>;
ed39097c TR	63	};
	64
	65	gr3d {
	66	compatible = "nvidia,tegra30-gr3d";
	67	reg = <0x54180000 0x00040000>;
1cbc733d PG	68	clocks = <&tegra_car 24 &tegra_car 98>;
1cbc733d PG	69	clock-names = "3d", "3d2";
ed39097c TR	70	};
	71
	72	dc@54200000 {
	73	compatible = "nvidia,tegra30-dc";
	74	reg = <0x54200000 0x00040000>;
6cecf916	75	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d PG	76	clocks = <&tegra_car 27>, <&tegra_car 179>;
1cbc733d PG	77	clock-names = "disp1", "parent";
ed39097c TR	78
	79	rgb {
	80	status = "disabled";
	81	};
	82	};
	83
	84	dc@54240000 {
	85	compatible = "nvidia,tegra30-dc";
	86	reg = <0x54240000 0x00040000>;
6cecf916	87	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d PG	88	clocks = <&tegra_car 26>, <&tegra_car 179>;
1cbc733d PG	89	clock-names = "disp2", "parent";
ed39097c TR	90
	91	rgb {
	92	status = "disabled";
	93	};
	94	};
	95
	96	hdmi {
	97	compatible = "nvidia,tegra30-hdmi";
	98	reg = <0x54280000 0x00040000>;
6cecf916	99	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d PG	100	clocks = <&tegra_car 51>, <&tegra_car 189>;
1cbc733d PG	101	clock-names = "hdmi", "parent";
ed39097c TR	102	status = "disabled";
	103	};
	104
	105	tvo {
	106	compatible = "nvidia,tegra30-tvo";
	107	reg = <0x542c0000 0x00040000>;
6cecf916	108	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d	109	clocks = <&tegra_car 169>;
ed39097c TR	110	status = "disabled";
	111	};
	112
	113	dsi {
	114	compatible = "nvidia,tegra30-dsi";
	115	reg = <0x54300000 0x00040000>;
1cbc733d	116	clocks = <&tegra_car 48>;
ed39097c TR	117	status = "disabled";
	118	};
	119	};
	120
73368ba0 SW	121	timer@50004600 {
	122	compatible = "arm,cortex-a9-twd-timer";
	123	reg = <0x50040600 0x20>;
6cecf916 SW	124	interrupts = <GIC_PPI 13
6cecf916 SW	125	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
ed3ced37	126	clocks = <&tegra_car 214>;
73368ba0 SW	127	};
73368ba0 SW	128
f9eb26a4	129	intc: interrupt-controller {
c3e00a0e	130	compatible = "arm,cortex-a9-gic";
5ff48887 SW	131	reg = <0x50041000 0x1000
5ff48887 SW	132	0x50040100 0x0100>;
2eaab06e SW	133	interrupt-controller;
2eaab06e SW	134	#interrupt-cells = <3>;
c3e00a0e PDS	135	};
c3e00a0e PDS	136
bb2c1de9 SW	137	cache-controller {
	138	compatible = "arm,pl310-cache";
	139	reg = <0x50043000 0x1000>;
	140	arm,data-latency = <6 6 2>;
	141	arm,tag-latency = <5 5 2>;
	142	cache-unified;
	143	cache-level = <2>;
	144	};
	145
2f2b7fb2 SW	146	timer@60005000 {
	147	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
	148	reg = <0x60005000 0x400>;
6cecf916 SW	149	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	150	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	151	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	152	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	153	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	154	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
6f88fb8a	155	clocks = <&tegra_car 5>;
2f2b7fb2 SW	156	};
2f2b7fb2 SW	157
95985667 PG	158	tegra_car: clock {
	159	compatible = "nvidia,tegra30-car";
	160	reg = <0x60006000 0x1000>;
	161	#clock-cells = <1>;
	162	};
	163
f9eb26a4	164	apbdma: dma {
8051b75a SW	165	compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
8051b75a SW	166	reg = <0x6000a000 0x1400>;
6cecf916 SW	167	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	168	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	169	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	170	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	171	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	172	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	173	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	174	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	175	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	176	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	177	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	178	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	179	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	180	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	181	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	182	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	183	<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	184	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	185	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	186	<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	187	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	188	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	189	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	190	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	191	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	192	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	193	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	194	<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
	195	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	196	<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	197	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d	199	clocks = <&tegra_car 34>;
8051b75a SW	200	};
8051b75a SW	201
c04abb3a SW	202	ahb: ahb {
	203	compatible = "nvidia,tegra30-ahb";
	204	reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e PDS	205	};
c3e00a0e PDS	206
f9eb26a4	207	gpio: gpio {
35f210ec	208	compatible = "nvidia,tegra30-gpio";
95decf84	209	reg = <0x6000d000 0x1000>;
6cecf916 SW	210	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	211	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	212	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	213	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	214	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	215	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	216	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	217	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e PDS	218	#gpio-cells = <2>;
c3e00a0e PDS	219	gpio-controller;
6f74dc9b SW	220	#interrupt-cells = <2>;
6f74dc9b SW	221	interrupt-controller;
c3e00a0e PDS	222	};
c3e00a0e PDS	223
c04abb3a SW	224	pinmux: pinmux {
c04abb3a SW	225	compatible = "nvidia,tegra30-pinmux";
322337b8 PR	226	reg = <0x70000868 0xd4 /* Pad control registers */
322337b8 PR	227	0x70003000 0x3e4>; /* Mux registers */
c04abb3a SW	228	};
c04abb3a SW	229
b6551bb9 LD	230	/*
	231	* There are two serial driver i.e. 8250 based simple serial
	232	* driver and APB DMA based serial driver for higher baudrate
	233	* and performace. To enable the 8250 based driver, the compatible
	234	* is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
	235	* the APB DMA based serial driver, the comptible is
	236	* "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
	237	*/
	238	uarta: serial@70006000 {
c3e00a0e PDS	239	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	240	reg = <0x70006000 0x40>;
	241	reg-shift = <2>;
6cecf916	242	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	243	nvidia,dma-request-selector = <&apbdma 8>;
1cbc733d	244	clocks = <&tegra_car 6>;
223ef78d	245	status = "disabled";
c3e00a0e PDS	246	};
c3e00a0e PDS	247
b6551bb9	248	uartb: serial@70006040 {
c3e00a0e PDS	249	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	250	reg = <0x70006040 0x40>;
	251	reg-shift = <2>;
6cecf916	252	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	253	nvidia,dma-request-selector = <&apbdma 9>;
1cbc733d	254	clocks = <&tegra_car 160>;
223ef78d	255	status = "disabled";
c3e00a0e PDS	256	};
c3e00a0e PDS	257
b6551bb9	258	uartc: serial@70006200 {
c3e00a0e PDS	259	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	260	reg = <0x70006200 0x100>;
	261	reg-shift = <2>;
6cecf916	262	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	263	nvidia,dma-request-selector = <&apbdma 10>;
1cbc733d	264	clocks = <&tegra_car 55>;
223ef78d	265	status = "disabled";
c3e00a0e PDS	266	};
c3e00a0e PDS	267
b6551bb9	268	uartd: serial@70006300 {
c3e00a0e PDS	269	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	270	reg = <0x70006300 0x100>;
	271	reg-shift = <2>;
6cecf916	272	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	273	nvidia,dma-request-selector = <&apbdma 19>;
1cbc733d	274	clocks = <&tegra_car 65>;
223ef78d	275	status = "disabled";
c3e00a0e PDS	276	};
c3e00a0e PDS	277
b6551bb9	278	uarte: serial@70006400 {
c3e00a0e PDS	279	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	280	reg = <0x70006400 0x100>;
	281	reg-shift = <2>;
6cecf916	282	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	283	nvidia,dma-request-selector = <&apbdma 20>;
1cbc733d	284	clocks = <&tegra_car 66>;
223ef78d	285	status = "disabled";
c3e00a0e PDS	286	};
c3e00a0e PDS	287
2b8b15da	288	pwm: pwm {
140fd977 TR	289	compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
	290	reg = <0x7000a000 0x100>;
	291	#pwm-cells = <2>;
1cbc733d	292	clocks = <&tegra_car 17>;
b69cd984	293	status = "disabled";
140fd977 TR	294	};
140fd977 TR	295
380e04ac SW	296	rtc {
	297	compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
	298	reg = <0x7000e000 0x100>;
6cecf916	299	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
6f88fb8a	300	clocks = <&tegra_car 4>;
380e04ac SW	301	};
380e04ac SW	302
c04abb3a	303	i2c@7000c000 {
c04abb3a SW	304	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a SW	305	reg = <0x7000c000 0x100>;
6cecf916	306	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	307	#address-cells = <1>;
2eaab06e SW	308	#size-cells = <0>;
1cbc733d PG	309	clocks = <&tegra_car 12>, <&tegra_car 182>;
1cbc733d PG	310	clock-names = "div-clk", "fast-clk";
223ef78d	311	status = "disabled";
c3e00a0e PDS	312	};
c3e00a0e PDS	313
c04abb3a	314	i2c@7000c400 {
c04abb3a SW	315	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a SW	316	reg = <0x7000c400 0x100>;
6cecf916	317	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	318	#address-cells = <1>;
2eaab06e SW	319	#size-cells = <0>;
1cbc733d PG	320	clocks = <&tegra_car 54>, <&tegra_car 182>;
1cbc733d PG	321	clock-names = "div-clk", "fast-clk";
223ef78d	322	status = "disabled";
c3e00a0e PDS	323	};
c3e00a0e PDS	324
c04abb3a	325	i2c@7000c500 {
c04abb3a SW	326	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a SW	327	reg = <0x7000c500 0x100>;
6cecf916	328	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	329	#address-cells = <1>;
2eaab06e SW	330	#size-cells = <0>;
1cbc733d PG	331	clocks = <&tegra_car 67>, <&tegra_car 182>;
1cbc733d PG	332	clock-names = "div-clk", "fast-clk";
223ef78d	333	status = "disabled";
c3e00a0e PDS	334	};
c3e00a0e PDS	335
c04abb3a	336	i2c@7000c700 {
c04abb3a SW	337	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a SW	338	reg = <0x7000c700 0x100>;
6cecf916	339	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	340	#address-cells = <1>;
2eaab06e SW	341	#size-cells = <0>;
1cbc733d PG	342	clocks = <&tegra_car 103>, <&tegra_car 182>;
1cbc733d PG	343	clock-names = "div-clk", "fast-clk";
223ef78d	344	status = "disabled";
c3e00a0e PDS	345	};
c3e00a0e PDS	346
c04abb3a	347	i2c@7000d000 {
c04abb3a SW	348	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a SW	349	reg = <0x7000d000 0x100>;
6cecf916	350	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	351	#address-cells = <1>;
2eaab06e SW	352	#size-cells = <0>;
1cbc733d PG	353	clocks = <&tegra_car 47>, <&tegra_car 182>;
1cbc733d PG	354	clock-names = "div-clk", "fast-clk";
223ef78d	355	status = "disabled";
c04abb3a SW	356	};
c04abb3a SW	357
a86b0db3 LD	358	spi@7000d400 {
	359	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	360	reg = <0x7000d400 0x200>;
6cecf916	361	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	362	nvidia,dma-request-selector = <&apbdma 15>;
	363	#address-cells = <1>;
	364	#size-cells = <0>;
1cbc733d	365	clocks = <&tegra_car 41>;
a86b0db3 LD	366	status = "disabled";
	367	};
	368
	369	spi@7000d600 {
	370	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	371	reg = <0x7000d600 0x200>;
6cecf916	372	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	373	nvidia,dma-request-selector = <&apbdma 16>;
	374	#address-cells = <1>;
	375	#size-cells = <0>;
1cbc733d	376	clocks = <&tegra_car 44>;
a86b0db3 LD	377	status = "disabled";
	378	};
	379
	380	spi@7000d800 {
	381	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d	382	reg = <0x7000d800 0x200>;
6cecf916	383	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	384	nvidia,dma-request-selector = <&apbdma 17>;
	385	#address-cells = <1>;
	386	#size-cells = <0>;
1cbc733d	387	clocks = <&tegra_car 46>;
a86b0db3 LD	388	status = "disabled";
	389	};
	390
	391	spi@7000da00 {
	392	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	393	reg = <0x7000da00 0x200>;
6cecf916	394	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	395	nvidia,dma-request-selector = <&apbdma 18>;
	396	#address-cells = <1>;
	397	#size-cells = <0>;
1cbc733d	398	clocks = <&tegra_car 68>;
a86b0db3 LD	399	status = "disabled";
	400	};
	401
	402	spi@7000dc00 {
	403	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	404	reg = <0x7000dc00 0x200>;
6cecf916	405	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	406	nvidia,dma-request-selector = <&apbdma 27>;
	407	#address-cells = <1>;
	408	#size-cells = <0>;
1cbc733d	409	clocks = <&tegra_car 104>;
a86b0db3 LD	410	status = "disabled";
	411	};
	412
	413	spi@7000de00 {
	414	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	415	reg = <0x7000de00 0x200>;
6cecf916	416	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	417	nvidia,dma-request-selector = <&apbdma 28>;
	418	#address-cells = <1>;
	419	#size-cells = <0>;
1cbc733d	420	clocks = <&tegra_car 105>;
a86b0db3 LD	421	status = "disabled";
	422	};
	423
699ed4b9 LD	424	kbc {
	425	compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
	426	reg = <0x7000e200 0x100>;
6cecf916	427	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
699ed4b9 LD	428	clocks = <&tegra_car 36>;
	429	status = "disabled";
	430	};
	431
c04abb3a	432	pmc {
2b84e53b	433	compatible = "nvidia,tegra30-pmc";
c04abb3a	434	reg = <0x7000e400 0x400>;
7021d122 JL	435	clocks = <&tegra_car 218>, <&clk32k_in>;
7021d122 JL	436	clock-names = "pclk", "clk32k_in";
c04abb3a SW	437	};
c04abb3a SW	438
a9140aa5	439	memory-controller {
c04abb3a SW	440	compatible = "nvidia,tegra30-mc";
	441	reg = <0x7000f000 0x010
	442	0x7000f03c 0x1b4
	443	0x7000f200 0x028
	444	0x7000f284 0x17c>;
6cecf916	445	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a SW	446	};
c04abb3a SW	447
3fbf07d8	448	iommu {
c04abb3a SW	449	compatible = "nvidia,tegra30-smmu";
	450	reg = <0x7000f010 0x02c
	451	0x7000f1f0 0x010
	452	0x7000f228 0x05c>;
	453	nvidia,#asids = <4>; /* # of ASIDs */
	454	dma-window = <0 0x40000000>; /* IOVA start & length */
	455	nvidia,ahb = <&ahb>;
c3e00a0e	456	};
9ee6a5c4 SW	457
	458	ahub {
	459	compatible = "nvidia,tegra30-ahub";
5ff48887 SW	460	reg = <0x70080000 0x200
5ff48887 SW	461	0x70080200 0x100>;
6cecf916	462	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9ee6a5c4	463	nvidia,dma-request-selector = <&apbdma 1>;
1cbc733d PG	464	clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
	465	<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
	466	<&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
	467	<&tegra_car 110>, <&tegra_car 162>;
	468	clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
	469	"i2s3", "i2s4", "dam0", "dam1", "dam2",
	470	"spdif_in";
9ee6a5c4 SW	471	ranges;
	472	#address-cells = <1>;
	473	#size-cells = <1>;
	474
	475	tegra_i2s0: i2s@70080300 {
	476	compatible = "nvidia,tegra30-i2s";
	477	reg = <0x70080300 0x100>;
	478	nvidia,ahub-cif-ids = <4 4>;
1cbc733d	479	clocks = <&tegra_car 30>;
223ef78d	480	status = "disabled";
9ee6a5c4 SW	481	};
	482
	483	tegra_i2s1: i2s@70080400 {
	484	compatible = "nvidia,tegra30-i2s";
	485	reg = <0x70080400 0x100>;
	486	nvidia,ahub-cif-ids = <5 5>;
1cbc733d	487	clocks = <&tegra_car 11>;
223ef78d	488	status = "disabled";
9ee6a5c4 SW	489	};
	490
	491	tegra_i2s2: i2s@70080500 {
	492	compatible = "nvidia,tegra30-i2s";
	493	reg = <0x70080500 0x100>;
	494	nvidia,ahub-cif-ids = <6 6>;
1cbc733d	495	clocks = <&tegra_car 18>;
223ef78d	496	status = "disabled";
9ee6a5c4 SW	497	};
	498
	499	tegra_i2s3: i2s@70080600 {
	500	compatible = "nvidia,tegra30-i2s";
	501	reg = <0x70080600 0x100>;
	502	nvidia,ahub-cif-ids = <7 7>;
1cbc733d	503	clocks = <&tegra_car 101>;
223ef78d	504	status = "disabled";
9ee6a5c4 SW	505	};
	506
	507	tegra_i2s4: i2s@70080700 {
	508	compatible = "nvidia,tegra30-i2s";
	509	reg = <0x70080700 0x100>;
	510	nvidia,ahub-cif-ids = <8 8>;
1cbc733d	511	clocks = <&tegra_car 102>;
223ef78d	512	status = "disabled";
9ee6a5c4 SW	513	};
9ee6a5c4 SW	514	};
7868a9bc	515
c04abb3a SW	516	sdhci@78000000 {
	517	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	518	reg = <0x78000000 0x200>;
6cecf916	519	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d	520	clocks = <&tegra_car 14>;
223ef78d	521	status = "disabled";
7868a9bc	522	};
ecf43742	523
c04abb3a SW	524	sdhci@78000200 {
	525	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	526	reg = <0x78000200 0x200>;
6cecf916	527	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d	528	clocks = <&tegra_car 9>;
223ef78d	529	status = "disabled";
ecf43742	530	};
54174a33	531
c04abb3a SW	532	sdhci@78000400 {
	533	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	534	reg = <0x78000400 0x200>;
6cecf916	535	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d	536	clocks = <&tegra_car 69>;
223ef78d	537	status = "disabled";
c04abb3a SW	538	};
	539
	540	sdhci@78000600 {
	541	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	542	reg = <0x78000600 0x200>;
6cecf916	543	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1cbc733d	544	clocks = <&tegra_car 15>;
223ef78d	545	status = "disabled";
c04abb3a SW	546	};
c04abb3a SW	547
7d19a34a HD	548	cpus {
	549	#address-cells = <1>;
	550	#size-cells = <0>;
	551
	552	cpu@0 {
	553	device_type = "cpu";
	554	compatible = "arm,cortex-a9";
	555	reg = <0>;
	556	};
	557
	558	cpu@1 {
	559	device_type = "cpu";
	560	compatible = "arm,cortex-a9";
	561	reg = <1>;
	562	};
	563
	564	cpu@2 {
	565	device_type = "cpu";
	566	compatible = "arm,cortex-a9";
	567	reg = <2>;
	568	};
	569
	570	cpu@3 {
	571	device_type = "cpu";
	572	compatible = "arm,cortex-a9";
	573	reg = <3>;
	574	};
	575	};
	576
c04abb3a SW	577	pmu {
c04abb3a SW	578	compatible = "arm,cortex-a9-pmu";
6cecf916 SW	579	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
	580	<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
	581	<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
	582	<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
54174a33	583	};
c3e00a0e	584	};