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ARM: tegra: update DT files to add reset properties
[linux-2.6-block.git] / arch / arm / boot / dts / tegra30.dtsi
CommitLineData
05849c93 1#include <dt-bindings/clock/tegra30-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
6cecf916 3#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 4
1bd0bd49 5#include "skeleton.dtsi"
c3e00a0e
PDS		 6
7/ {
8 compatible = "nvidia,tegra30";
9 interrupt-parent = <&intc>;
10
b6551bb9
LD		 11 aliases {
12 serial0 = &uarta;
13 serial1 = &uartb;
14 serial2 = &uartc;
15 serial3 = &uartd;
16 serial4 = &uarte;
17 };
18
e07e3dbd
TR		 19 pcie-controller {
20 compatible = "nvidia,tegra30-pcie";
21 device_type = "pci";
22 reg = <0x00003000 0x00000800 /* PADS registers */
23 0x00003800 0x00000200 /* AFI registers */
24 0x10000000 0x10000000>; /* configuration space */
25 reg-names = "pads", "afi", "cs";
26 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
27 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
28 interrupt-names = "intr", "msi";
29
30 bus-range = <0x00 0xff>;
31 #address-cells = <3>;
32 #size-cells = <2>;
33
34 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
35 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
36 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
37 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 38 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
39 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
e07e3dbd
TR		 40
41 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
42 <&tegra_car TEGRA30_CLK_AFI>,
43 <&tegra_car TEGRA30_CLK_PCIEX>,
44 <&tegra_car TEGRA30_CLK_PLL_E>,
45 <&tegra_car TEGRA30_CLK_CML0>;
46 clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
3393d422
SW		 47 resets = <&tegra_car 70>,
48 <&tegra_car 72>,
49 <&tegra_car 74>;
50 reset-names = "pex", "afi", "pcie_x";
e07e3dbd
TR		 51 status = "disabled";
52
53 pci@1,0 {
54 device_type = "pci";
55 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
57 status = "disabled";
58
59 #address-cells = <3>;
60 #size-cells = <2>;
61 ranges;
62
63 nvidia,num-lanes = <2>;
64 };
65
66 pci@2,0 {
67 device_type = "pci";
68 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
69 reg = <0x001000 0 0 0 0>;
70 status = "disabled";
71
72 #address-cells = <3>;
73 #size-cells = <2>;
74 ranges;
75
76 nvidia,num-lanes = <2>;
77 };
78
79 pci@3,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
82 reg = <0x001800 0 0 0 0>;
83 status = "disabled";
84
85 #address-cells = <3>;
86 #size-cells = <2>;
87 ranges;
88
89 nvidia,num-lanes = <2>;
90 };
91 };
92
ed39097c
TR		 93 host1x {
94 compatible = "nvidia,tegra30-host1x", "simple-bus";
95 reg = <0x50000000 0x00024000>;
6cecf916
SW		 96 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
97 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
05849c93 98 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
3393d422
SW		 99 resets = <&tegra_car 28>;
100 reset-names = "host1x";
ed39097c
TR		 101
102 #address-cells = <1>;
103 #size-cells = <1>;
104
105 ranges = <0x54000000 0x54000000 0x04000000>;
106
107 mpe {
108 compatible = "nvidia,tegra30-mpe";
109 reg = <0x54040000 0x00040000>;
6cecf916 110 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
05849c93 111 clocks = <&tegra_car TEGRA30_CLK_MPE>;
3393d422
SW		 112 resets = <&tegra_car 60>;
113 reset-names = "mpe";
ed39097c
TR		 114 };
115
116 vi {
117 compatible = "nvidia,tegra30-vi";
118 reg = <0x54080000 0x00040000>;
6cecf916 119 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
05849c93 120 clocks = <&tegra_car TEGRA30_CLK_VI>;
3393d422
SW		 121 resets = <&tegra_car 20>;
122 reset-names = "vi";
ed39097c
TR		 123 };
124
125 epp {
126 compatible = "nvidia,tegra30-epp";
127 reg = <0x540c0000 0x00040000>;
6cecf916 128 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
05849c93 129 clocks = <&tegra_car TEGRA30_CLK_EPP>;
3393d422
SW		 130 resets = <&tegra_car 19>;
131 reset-names = "epp";
ed39097c
TR		 132 };
133
134 isp {
135 compatible = "nvidia,tegra30-isp";
136 reg = <0x54100000 0x00040000>;
6cecf916 137 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
05849c93 138 clocks = <&tegra_car TEGRA30_CLK_ISP>;
3393d422
SW		 139 resets = <&tegra_car 23>;
140 reset-names = "isp";
ed39097c
TR		 141 };
142
143 gr2d {
144 compatible = "nvidia,tegra30-gr2d";
145 reg = <0x54140000 0x00040000>;
6cecf916 146 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3393d422
SW		 147 resets = <&tegra_car 21>;
148 reset-names = "2d";
05849c93 149 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
ed39097c
TR		 150 };
151
152 gr3d {
153 compatible = "nvidia,tegra30-gr3d";
154 reg = <0x54180000 0x00040000>;
c71d3909
TR		 155 clocks = <&tegra_car TEGRA30_CLK_GR3D
156 &tegra_car TEGRA30_CLK_GR3D2>;
1cbc733d 157 clock-names = "3d", "3d2";
3393d422
SW		 158 resets = <&tegra_car 24>,
159 <&tegra_car 98>;
160 reset-names = "3d", "3d2";
ed39097c
TR		 161 };
162
163 dc@54200000 {
05465f4e 164 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
ed39097c 165 reg = <0x54200000 0x00040000>;
6cecf916 166 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 167 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
168 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 169 clock-names = "dc", "parent";
3393d422
SW		 170 resets = <&tegra_car 27>;
171 reset-names = "dc";
ed39097c
TR		 172
173 rgb {
174 status = "disabled";
175 };
176 };
177
178 dc@54240000 {
179 compatible = "nvidia,tegra30-dc";
180 reg = <0x54240000 0x00040000>;
6cecf916 181 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 182 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
183 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 184 clock-names = "dc", "parent";
3393d422
SW		 185 resets = <&tegra_car 26>;
186 reset-names = "dc";
ed39097c
TR		 187
188 rgb {
189 status = "disabled";
190 };
191 };
192
193 hdmi {
194 compatible = "nvidia,tegra30-hdmi";
195 reg = <0x54280000 0x00040000>;
6cecf916 196 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 197 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
198 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
1cbc733d 199 clock-names = "hdmi", "parent";
3393d422
SW		 200 resets = <&tegra_car 51>;
201 reset-names = "hdmi";
ed39097c
TR		 202 status = "disabled";
203 };
204
205 tvo {
206 compatible = "nvidia,tegra30-tvo";
207 reg = <0x542c0000 0x00040000>;
6cecf916 208 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
05849c93 209 clocks = <&tegra_car TEGRA30_CLK_TVO>;
ed39097c
TR		 210 status = "disabled";
211 };
212
213 dsi {
214 compatible = "nvidia,tegra30-dsi";
215 reg = <0x54300000 0x00040000>;
05849c93 216 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
3393d422
SW		 217 resets = <&tegra_car 48>;
218 reset-names = "dsi";
ed39097c
TR		 219 status = "disabled";
220 };
221 };
222
73368ba0
SW		 223 timer@50004600 {
224 compatible = "arm,cortex-a9-twd-timer";
225 reg = <0x50040600 0x20>;
6cecf916
SW		 226 interrupts = <GIC_PPI 13
227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
05849c93 228 clocks = <&tegra_car TEGRA30_CLK_TWD>;
73368ba0
SW		 229 };
230
f9eb26a4 231 intc: interrupt-controller {
c3e00a0e 232 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 233 reg = <0x50041000 0x1000
234 0x50040100 0x0100>;
2eaab06e
SW		 235 interrupt-controller;
236 #interrupt-cells = <3>;
c3e00a0e
PDS		 237 };
238
bb2c1de9
SW		 239 cache-controller {
240 compatible = "arm,pl310-cache";
241 reg = <0x50043000 0x1000>;
242 arm,data-latency = <6 6 2>;
243 arm,tag-latency = <5 5 2>;
244 cache-unified;
245 cache-level = <2>;
246 };
247
2f2b7fb2
SW		 248 timer@60005000 {
249 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
250 reg = <0x60005000 0x400>;
6cecf916
SW		 251 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
05849c93 257 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
2f2b7fb2
SW		 258 };
259
95985667
PG		 260 tegra_car: clock {
261 compatible = "nvidia,tegra30-car";
262 reg = <0x60006000 0x1000>;
263 #clock-cells = <1>;
3393d422 264 #reset-cells = <1>;
95985667
PG		 265 };
266
f9eb26a4 267 apbdma: dma {
8051b75a
SW		 268 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
269 reg = <0x6000a000 0x1400>;
6cecf916
SW		 270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
05849c93 302 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
3393d422
SW		 303 resets = <&tegra_car 34>;
304 reset-names = "dma";
8051b75a
SW		 305 };
306
c04abb3a
SW		 307 ahb: ahb {
308 compatible = "nvidia,tegra30-ahb";
309 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e
PDS		 310 };
311
f9eb26a4 312 gpio: gpio {
35f210ec 313 compatible = "nvidia,tegra30-gpio";
95decf84 314 reg = <0x6000d000 0x1000>;
6cecf916
SW		 315 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e
PDS		 323 #gpio-cells = <2>;
324 gpio-controller;
6f74dc9b
SW		 325 #interrupt-cells = <2>;
326 interrupt-controller;
c3e00a0e
PDS		 327 };
328
c04abb3a
SW		 329 pinmux: pinmux {
330 compatible = "nvidia,tegra30-pinmux";
322337b8
PR		 331 reg = <0x70000868 0xd4 /* Pad control registers */
332 0x70003000 0x3e4>; /* Mux registers */
c04abb3a
SW		 333 };
334
b6551bb9
LD		 335 /*
336 * There are two serial driver i.e. 8250 based simple serial
337 * driver and APB DMA based serial driver for higher baudrate
338 * and performace. To enable the 8250 based driver, the compatible
339 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
340 * the APB DMA based serial driver, the comptible is
341 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
342 */
343 uarta: serial@70006000 {
c3e00a0e
PDS		 344 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
345 reg = <0x70006000 0x40>;
346 reg-shift = <2>;
6cecf916 347 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 348 nvidia,dma-request-selector = <&apbdma 8>;
05849c93 349 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
3393d422
SW		 350 resets = <&tegra_car 6>;
351 reset-names = "serial";
223ef78d 352 status = "disabled";
c3e00a0e
PDS		 353 };
354
b6551bb9 355 uartb: serial@70006040 {
c3e00a0e
PDS		 356 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
357 reg = <0x70006040 0x40>;
358 reg-shift = <2>;
6cecf916 359 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 360 nvidia,dma-request-selector = <&apbdma 9>;
05849c93 361 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
3393d422
SW		 362 resets = <&tegra_car 7>;
363 reset-names = "serial";
223ef78d 364 status = "disabled";
c3e00a0e
PDS		 365 };
366
b6551bb9 367 uartc: serial@70006200 {
c3e00a0e
PDS		 368 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
369 reg = <0x70006200 0x100>;
370 reg-shift = <2>;
6cecf916 371 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 372 nvidia,dma-request-selector = <&apbdma 10>;
05849c93 373 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
3393d422
SW		 374 resets = <&tegra_car 55>;
375 reset-names = "serial";
223ef78d 376 status = "disabled";
c3e00a0e
PDS		 377 };
378
b6551bb9 379 uartd: serial@70006300 {
c3e00a0e
PDS		 380 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
381 reg = <0x70006300 0x100>;
382 reg-shift = <2>;
6cecf916 383 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 384 nvidia,dma-request-selector = <&apbdma 19>;
05849c93 385 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
3393d422
SW		 386 resets = <&tegra_car 65>;
387 reset-names = "serial";
223ef78d 388 status = "disabled";
c3e00a0e
PDS		 389 };
390
b6551bb9 391 uarte: serial@70006400 {
c3e00a0e
PDS		 392 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
393 reg = <0x70006400 0x100>;
394 reg-shift = <2>;
6cecf916 395 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9 396 nvidia,dma-request-selector = <&apbdma 20>;
05849c93 397 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
3393d422
SW		 398 resets = <&tegra_car 66>;
399 reset-names = "serial";
223ef78d 400 status = "disabled";
c3e00a0e
PDS		 401 };
402
2b8b15da 403 pwm: pwm {
140fd977
TR		 404 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
405 reg = <0x7000a000 0x100>;
406 #pwm-cells = <2>;
05849c93 407 clocks = <&tegra_car TEGRA30_CLK_PWM>;
3393d422
SW		 408 resets = <&tegra_car 17>;
409 reset-names = "pwm";
b69cd984 410 status = "disabled";
140fd977
TR		 411 };
412
380e04ac
SW		 413 rtc {
414 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
415 reg = <0x7000e000 0x100>;
6cecf916 416 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
05849c93 417 clocks = <&tegra_car TEGRA30_CLK_RTC>;
380e04ac
SW		 418 };
419
c04abb3a 420 i2c@7000c000 {
c04abb3a
SW		 421 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
422 reg = <0x7000c000 0x100>;
6cecf916 423 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 424 #address-cells = <1>;
425 #size-cells = <0>;
05849c93
HD		 426 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
427 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 428 clock-names = "div-clk", "fast-clk";
3393d422
SW		 429 resets = <&tegra_car 12>;
430 reset-names = "i2c";
223ef78d 431 status = "disabled";
c3e00a0e
PDS		 432 };
433
c04abb3a 434 i2c@7000c400 {
c04abb3a
SW		 435 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
436 reg = <0x7000c400 0x100>;
6cecf916 437 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 438 #address-cells = <1>;
439 #size-cells = <0>;
05849c93
HD		 440 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
441 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 442 clock-names = "div-clk", "fast-clk";
3393d422
SW		 443 resets = <&tegra_car 54>;
444 reset-names = "i2c";
223ef78d 445 status = "disabled";
c3e00a0e
PDS		 446 };
447
c04abb3a 448 i2c@7000c500 {
c04abb3a
SW		 449 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
450 reg = <0x7000c500 0x100>;
6cecf916 451 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 452 #address-cells = <1>;
453 #size-cells = <0>;
05849c93
HD		 454 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
455 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 456 clock-names = "div-clk", "fast-clk";
3393d422
SW		 457 resets = <&tegra_car 67>;
458 reset-names = "i2c";
223ef78d 459 status = "disabled";
c3e00a0e
PDS		 460 };
461
c04abb3a 462 i2c@7000c700 {
c04abb3a
SW		 463 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
464 reg = <0x7000c700 0x100>;
6cecf916 465 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 466 #address-cells = <1>;
467 #size-cells = <0>;
05849c93
HD		 468 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
469 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
3393d422
SW		 470 resets = <&tegra_car 103>;
471 reset-names = "i2c";
1cbc733d 472 clock-names = "div-clk", "fast-clk";
223ef78d 473 status = "disabled";
c3e00a0e
PDS		 474 };
475
c04abb3a 476 i2c@7000d000 {
c04abb3a
SW		 477 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
478 reg = <0x7000d000 0x100>;
6cecf916 479 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 480 #address-cells = <1>;
481 #size-cells = <0>;
05849c93
HD		 482 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
483 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 484 clock-names = "div-clk", "fast-clk";
3393d422
SW		 485 resets = <&tegra_car 47>;
486 reset-names = "i2c";
223ef78d 487 status = "disabled";
c04abb3a
SW		 488 };
489
a86b0db3
LD		 490 spi@7000d400 {
491 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
492 reg = <0x7000d400 0x200>;
6cecf916 493 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 494 nvidia,dma-request-selector = <&apbdma 15>;
495 #address-cells = <1>;
496 #size-cells = <0>;
05849c93 497 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
3393d422
SW		 498 resets = <&tegra_car 41>;
499 reset-names = "spi";
a86b0db3
LD		 500 status = "disabled";
501 };
502
503 spi@7000d600 {
504 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
505 reg = <0x7000d600 0x200>;
6cecf916 506 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 507 nvidia,dma-request-selector = <&apbdma 16>;
508 #address-cells = <1>;
509 #size-cells = <0>;
05849c93 510 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
3393d422
SW		 511 resets = <&tegra_car 44>;
512 reset-names = "spi";
a86b0db3
LD		 513 status = "disabled";
514 };
515
516 spi@7000d800 {
517 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d 518 reg = <0x7000d800 0x200>;
6cecf916 519 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 520 nvidia,dma-request-selector = <&apbdma 17>;
521 #address-cells = <1>;
522 #size-cells = <0>;
05849c93 523 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
3393d422
SW		 524 resets = <&tegra_car 46>;
525 reset-names = "spi";
a86b0db3
LD		 526 status = "disabled";
527 };
528
529 spi@7000da00 {
530 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
531 reg = <0x7000da00 0x200>;
6cecf916 532 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 533 nvidia,dma-request-selector = <&apbdma 18>;
534 #address-cells = <1>;
535 #size-cells = <0>;
05849c93 536 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
3393d422
SW		 537 resets = <&tegra_car 68>;
538 reset-names = "spi";
a86b0db3
LD		 539 status = "disabled";
540 };
541
542 spi@7000dc00 {
543 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
544 reg = <0x7000dc00 0x200>;
6cecf916 545 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 546 nvidia,dma-request-selector = <&apbdma 27>;
547 #address-cells = <1>;
548 #size-cells = <0>;
05849c93 549 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
3393d422
SW		 550 resets = <&tegra_car 104>;
551 reset-names = "spi";
a86b0db3
LD		 552 status = "disabled";
553 };
554
555 spi@7000de00 {
556 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
557 reg = <0x7000de00 0x200>;
6cecf916 558 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 559 nvidia,dma-request-selector = <&apbdma 28>;
560 #address-cells = <1>;
561 #size-cells = <0>;
05849c93 562 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
3393d422
SW		 563 resets = <&tegra_car 106>;
564 reset-names = "spi";
a86b0db3
LD		 565 status = "disabled";
566 };
567
699ed4b9
LD		 568 kbc {
569 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
570 reg = <0x7000e200 0x100>;
6cecf916 571 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
05849c93 572 clocks = <&tegra_car TEGRA30_CLK_KBC>;
3393d422
SW		 573 resets = <&tegra_car 36>;
574 reset-names = "kbc";
699ed4b9
LD		 575 status = "disabled";
576 };
577
c04abb3a 578 pmc {
2b84e53b 579 compatible = "nvidia,tegra30-pmc";
c04abb3a 580 reg = <0x7000e400 0x400>;
05849c93 581 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
7021d122 582 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 583 };
584
a9140aa5 585 memory-controller {
c04abb3a
SW		 586 compatible = "nvidia,tegra30-mc";
587 reg = <0x7000f000 0x010
588 0x7000f03c 0x1b4
589 0x7000f200 0x028
590 0x7000f284 0x17c>;
6cecf916 591 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a
SW		 592 };
593
3fbf07d8 594 iommu {
c04abb3a
SW		 595 compatible = "nvidia,tegra30-smmu";
596 reg = <0x7000f010 0x02c
597 0x7000f1f0 0x010
598 0x7000f228 0x05c>;
599 nvidia,#asids = <4>; /* # of ASIDs */
600 dma-window = <0 0x40000000>; /* IOVA start & length */
601 nvidia,ahb = <&ahb>;
c3e00a0e 602 };
9ee6a5c4
SW		 603
604 ahub {
605 compatible = "nvidia,tegra30-ahub";
5ff48887
SW		 606 reg = <0x70080000 0x200
607 0x70080200 0x100>;
6cecf916 608 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9ee6a5c4 609 nvidia,dma-request-selector = <&apbdma 1>;
05849c93
HD		 610 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
611 <&tegra_car TEGRA30_CLK_APBIF>,
612 <&tegra_car TEGRA30_CLK_I2S0>,
613 <&tegra_car TEGRA30_CLK_I2S1>,
614 <&tegra_car TEGRA30_CLK_I2S2>,
615 <&tegra_car TEGRA30_CLK_I2S3>,
616 <&tegra_car TEGRA30_CLK_I2S4>,
617 <&tegra_car TEGRA30_CLK_DAM0>,
618 <&tegra_car TEGRA30_CLK_DAM1>,
619 <&tegra_car TEGRA30_CLK_DAM2>,
620 <&tegra_car TEGRA30_CLK_SPDIF_IN>;
1cbc733d
PG		 621 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
622 "i2s3", "i2s4", "dam0", "dam1", "dam2",
623 "spdif_in";
3393d422
SW		 624 resets = <&tegra_car 106>, /* d_audio */
625 <&tegra_car 107>, /* apbif */
626 <&tegra_car 30>, /* i2s0 */
627 <&tegra_car 11>, /* i2s1 */
628 <&tegra_car 18>, /* i2s2 */
629 <&tegra_car 101>, /* i2s3 */
630 <&tegra_car 102>, /* i2s4 */
631 <&tegra_car 108>, /* dam0 */
632 <&tegra_car 109>, /* dam1 */
633 <&tegra_car 110>, /* dam2 */
634 <&tegra_car 10>; /* spdif */
635 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
636 "i2s3", "i2s4", "dam0", "dam1", "dam2",
637 "spdif";
9ee6a5c4
SW		 638 ranges;
639 #address-cells = <1>;
640 #size-cells = <1>;
641
642 tegra_i2s0: i2s@70080300 {
643 compatible = "nvidia,tegra30-i2s";
644 reg = <0x70080300 0x100>;
645 nvidia,ahub-cif-ids = <4 4>;
05849c93 646 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
3393d422
SW		 647 resets = <&tegra_car 30>;
648 reset-names = "i2s";
223ef78d 649 status = "disabled";
9ee6a5c4
SW		 650 };
651
652 tegra_i2s1: i2s@70080400 {
653 compatible = "nvidia,tegra30-i2s";
654 reg = <0x70080400 0x100>;
655 nvidia,ahub-cif-ids = <5 5>;
05849c93 656 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
3393d422
SW		 657 resets = <&tegra_car 11>;
658 reset-names = "i2s";
223ef78d 659 status = "disabled";
9ee6a5c4
SW		 660 };
661
662 tegra_i2s2: i2s@70080500 {
663 compatible = "nvidia,tegra30-i2s";
664 reg = <0x70080500 0x100>;
665 nvidia,ahub-cif-ids = <6 6>;
05849c93 666 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
3393d422
SW		 667 resets = <&tegra_car 18>;
668 reset-names = "i2s";
223ef78d 669 status = "disabled";
9ee6a5c4
SW		 670 };
671
672 tegra_i2s3: i2s@70080600 {
673 compatible = "nvidia,tegra30-i2s";
674 reg = <0x70080600 0x100>;
675 nvidia,ahub-cif-ids = <7 7>;
05849c93 676 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
3393d422
SW		 677 resets = <&tegra_car 101>;
678 reset-names = "i2s";
223ef78d 679 status = "disabled";
9ee6a5c4
SW		 680 };
681
682 tegra_i2s4: i2s@70080700 {
683 compatible = "nvidia,tegra30-i2s";
684 reg = <0x70080700 0x100>;
685 nvidia,ahub-cif-ids = <8 8>;
05849c93 686 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
3393d422
SW		 687 resets = <&tegra_car 102>;
688 reset-names = "i2s";
223ef78d 689 status = "disabled";
9ee6a5c4
SW		 690 };
691 };
7868a9bc 692
c04abb3a
SW		 693 sdhci@78000000 {
694 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
695 reg = <0x78000000 0x200>;
6cecf916 696 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
05849c93 697 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
3393d422
SW		 698 resets = <&tegra_car 14>;
699 reset-names = "sdhci";
223ef78d 700 status = "disabled";
7868a9bc 701 };
ecf43742 702
c04abb3a
SW		 703 sdhci@78000200 {
704 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
705 reg = <0x78000200 0x200>;
6cecf916 706 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
05849c93 707 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
3393d422
SW		 708 resets = <&tegra_car 9>;
709 reset-names = "sdhci";
223ef78d 710 status = "disabled";
ecf43742 711 };
54174a33 712
c04abb3a
SW		 713 sdhci@78000400 {
714 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
715 reg = <0x78000400 0x200>;
6cecf916 716 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
05849c93 717 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
3393d422
SW		 718 resets = <&tegra_car 69>;
719 reset-names = "sdhci";
223ef78d 720 status = "disabled";
c04abb3a
SW		 721 };
722
723 sdhci@78000600 {
724 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
725 reg = <0x78000600 0x200>;
6cecf916 726 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
05849c93 727 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
3393d422
SW		 728 resets = <&tegra_car 15>;
729 reset-names = "sdhci";
223ef78d 730 status = "disabled";
c04abb3a
SW		 731 };
732
cc34c9f7
TT		 733 usb@7d000000 {
734 compatible = "nvidia,tegra30-ehci", "usb-ehci";
735 reg = <0x7d000000 0x4000>;
736 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
737 phy_type = "utmi";
738 clocks = <&tegra_car TEGRA30_CLK_USBD>;
3393d422
SW		 739 resets = <&tegra_car 22>;
740 reset-names = "usb";
cc34c9f7
TT		 741 nvidia,needs-double-reset;
742 nvidia,phy = <&phy1>;
743 status = "disabled";
744 };
745
746 phy1: usb-phy@7d000000 {
747 compatible = "nvidia,tegra30-usb-phy";
748 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
749 phy_type = "utmi";
750 clocks = <&tegra_car TEGRA30_CLK_USBD>,
751 <&tegra_car TEGRA30_CLK_PLL_U>,
752 <&tegra_car TEGRA30_CLK_USBD>;
753 clock-names = "reg", "pll_u", "utmi-pads";
754 nvidia,hssync-start-delay = <9>;
755 nvidia,idle-wait-delay = <17>;
756 nvidia,elastic-limit = <16>;
757 nvidia,term-range-adj = <6>;
758 nvidia,xcvr-setup = <51>;
759 nvidia.xcvr-setup-use-fuses;
760 nvidia,xcvr-lsfslew = <1>;
761 nvidia,xcvr-lsrslew = <1>;
762 nvidia,xcvr-hsslew = <32>;
763 nvidia,hssquelch-level = <2>;
764 nvidia,hsdiscon-level = <5>;
765 status = "disabled";
766 };
767
768 usb@7d004000 {
769 compatible = "nvidia,tegra30-ehci", "usb-ehci";
770 reg = <0x7d004000 0x4000>;
771 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
772 phy_type = "ulpi";
773 clocks = <&tegra_car TEGRA30_CLK_USB2>;
3393d422
SW		 774 resets = <&tegra_car 58>;
775 reset-names = "usb";
cc34c9f7
TT		 776 nvidia,phy = <&phy2>;
777 status = "disabled";
778 };
779
780 phy2: usb-phy@7d004000 {
781 compatible = "nvidia,tegra30-usb-phy";
782 reg = <0x7d004000 0x4000>;
783 phy_type = "ulpi";
784 clocks = <&tegra_car TEGRA30_CLK_USB2>,
785 <&tegra_car TEGRA30_CLK_PLL_U>,
786 <&tegra_car TEGRA30_CLK_CDEV2>;
787 clock-names = "reg", "pll_u", "ulpi-link";
788 status = "disabled";
789 };
790
791 usb@7d008000 {
792 compatible = "nvidia,tegra30-ehci", "usb-ehci";
793 reg = <0x7d008000 0x4000>;
794 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
795 phy_type = "utmi";
796 clocks = <&tegra_car TEGRA30_CLK_USB3>;
3393d422
SW		 797 resets = <&tegra_car 59>;
798 reset-names = "usb";
cc34c9f7
TT		 799 nvidia,phy = <&phy3>;
800 status = "disabled";
801 };
802
803 phy3: usb-phy@7d008000 {
804 compatible = "nvidia,tegra30-usb-phy";
805 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
806 phy_type = "utmi";
807 clocks = <&tegra_car TEGRA30_CLK_USB3>,
808 <&tegra_car TEGRA30_CLK_PLL_U>,
809 <&tegra_car TEGRA30_CLK_USBD>;
810 clock-names = "reg", "pll_u", "utmi-pads";
811 nvidia,hssync-start-delay = <0>;
812 nvidia,idle-wait-delay = <17>;
813 nvidia,elastic-limit = <16>;
814 nvidia,term-range-adj = <6>;
815 nvidia,xcvr-setup = <51>;
816 nvidia.xcvr-setup-use-fuses;
817 nvidia,xcvr-lsfslew = <2>;
818 nvidia,xcvr-lsrslew = <2>;
819 nvidia,xcvr-hsslew = <32>;
820 nvidia,hssquelch-level = <2>;
821 nvidia,hsdiscon-level = <5>;
822 status = "disabled";
823 };
824
7d19a34a
HD		 825 cpus {
826 #address-cells = <1>;
827 #size-cells = <0>;
828
829 cpu@0 {
830 device_type = "cpu";
831 compatible = "arm,cortex-a9";
832 reg = <0>;
833 };
834
835 cpu@1 {
836 device_type = "cpu";
837 compatible = "arm,cortex-a9";
838 reg = <1>;
839 };
840
841 cpu@2 {
842 device_type = "cpu";
843 compatible = "arm,cortex-a9";
844 reg = <2>;
845 };
846
847 cpu@3 {
848 device_type = "cpu";
849 compatible = "arm,cortex-a9";
850 reg = <3>;
851 };
852 };
853
c04abb3a
SW		 854 pmu {
855 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 856 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
858 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
859 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
54174a33 860 };
c3e00a0e 861};
Linux 6.x block layer and io_uring tree(s)