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ARM: tegra: use 2 address cells for Tegra124 DT
[linux-2.6-block.git] / arch / arm / boot / dts / tegra20.dtsi
CommitLineData
885a8cfa 1#include <dt-bindings/clock/tegra20-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
ba4104e7 3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 4#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 5
1bd0bd49 6#include "skeleton.dtsi"
8e267f3d
GL		 7
8/ {
9 compatible = "nvidia,tegra20";
10 interrupt-parent = <&intc>;
11
b6551bb9
LD		 12 aliases {
13 serial0 = &uarta;
14 serial1 = &uartb;
15 serial2 = &uartc;
16 serial3 = &uartd;
17 serial4 = &uarte;
18 };
19
58ecb23f 20 host1x@50000000 {
ed821f07
TR		 21 compatible = "nvidia,tegra20-host1x", "simple-bus";
22 reg = <0x50000000 0x00024000>;
6cecf916
SW		 23 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
24 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
885a8cfa 25 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
3393d422
SW		 26 resets = <&tegra_car 28>;
27 reset-names = "host1x";
ed821f07
TR		 28
29 #address-cells = <1>;
30 #size-cells = <1>;
31
32 ranges = <0x54000000 0x54000000 0x04000000>;
33
58ecb23f 34 mpe@54040000 {
ed821f07
TR		 35 compatible = "nvidia,tegra20-mpe";
36 reg = <0x54040000 0x00040000>;
6cecf916 37 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 38 clocks = <&tegra_car TEGRA20_CLK_MPE>;
3393d422
SW		 39 resets = <&tegra_car 60>;
40 reset-names = "mpe";
ed821f07
TR		 41 };
42
58ecb23f 43 vi@54080000 {
ed821f07
TR		 44 compatible = "nvidia,tegra20-vi";
45 reg = <0x54080000 0x00040000>;
6cecf916 46 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 47 clocks = <&tegra_car TEGRA20_CLK_VI>;
3393d422
SW		 48 resets = <&tegra_car 20>;
49 reset-names = "vi";
ed821f07
TR		 50 };
51
58ecb23f 52 epp@540c0000 {
ed821f07
TR		 53 compatible = "nvidia,tegra20-epp";
54 reg = <0x540c0000 0x00040000>;
6cecf916 55 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 56 clocks = <&tegra_car TEGRA20_CLK_EPP>;
3393d422
SW		 57 resets = <&tegra_car 19>;
58 reset-names = "epp";
ed821f07
TR		 59 };
60
58ecb23f 61 isp@54100000 {
ed821f07
TR		 62 compatible = "nvidia,tegra20-isp";
63 reg = <0x54100000 0x00040000>;
6cecf916 64 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 65 clocks = <&tegra_car TEGRA20_CLK_ISP>;
3393d422
SW		 66 resets = <&tegra_car 23>;
67 reset-names = "isp";
ed821f07
TR		 68 };
69
58ecb23f 70 gr2d@54140000 {
ed821f07
TR		 71 compatible = "nvidia,tegra20-gr2d";
72 reg = <0x54140000 0x00040000>;
6cecf916 73 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 74 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
3393d422
SW		 75 resets = <&tegra_car 21>;
76 reset-names = "2d";
ed821f07
TR		 77 };
78
58ecb23f 79 gr3d@54140000 {
ed821f07 80 compatible = "nvidia,tegra20-gr3d";
58ecb23f 81 reg = <0x54140000 0x00040000>;
885a8cfa 82 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
3393d422
SW		 83 resets = <&tegra_car 24>;
84 reset-names = "3d";
ed821f07
TR		 85 };
86
87 dc@54200000 {
88 compatible = "nvidia,tegra20-dc";
89 reg = <0x54200000 0x00040000>;
6cecf916 90 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 91 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
92 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 93 clock-names = "dc", "parent";
3393d422
SW		 94 resets = <&tegra_car 27>;
95 reset-names = "dc";
ed821f07
TR		 96
97 rgb {
98 status = "disabled";
99 };
100 };
101
102 dc@54240000 {
103 compatible = "nvidia,tegra20-dc";
104 reg = <0x54240000 0x00040000>;
6cecf916 105 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 106 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
107 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 108 clock-names = "dc", "parent";
3393d422
SW		 109 resets = <&tegra_car 26>;
110 reset-names = "dc";
ed821f07
TR		 111
112 rgb {
113 status = "disabled";
114 };
115 };
116
58ecb23f 117 hdmi@54280000 {
ed821f07
TR		 118 compatible = "nvidia,tegra20-hdmi";
119 reg = <0x54280000 0x00040000>;
6cecf916 120 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 121 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
122 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
8d8b43da 123 clock-names = "hdmi", "parent";
3393d422
SW		 124 resets = <&tegra_car 51>;
125 reset-names = "hdmi";
ed821f07
TR		 126 status = "disabled";
127 };
128
58ecb23f 129 tvo@542c0000 {
ed821f07
TR		 130 compatible = "nvidia,tegra20-tvo";
131 reg = <0x542c0000 0x00040000>;
6cecf916 132 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 133 clocks = <&tegra_car TEGRA20_CLK_TVO>;
ed821f07
TR		 134 status = "disabled";
135 };
136
58ecb23f 137 dsi@542c0000 {
ed821f07 138 compatible = "nvidia,tegra20-dsi";
58ecb23f 139 reg = <0x542c0000 0x00040000>;
885a8cfa 140 clocks = <&tegra_car TEGRA20_CLK_DSI>;
3393d422
SW		 141 resets = <&tegra_car 48>;
142 reset-names = "dsi";
ed821f07
TR		 143 status = "disabled";
144 };
145 };
146
73368ba0
SW		 147 timer@50004600 {
148 compatible = "arm,cortex-a9-twd-timer";
149 reg = <0x50040600 0x20>;
6cecf916
SW		 150 interrupts = <GIC_PPI 13
151 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
885a8cfa 152 clocks = <&tegra_car TEGRA20_CLK_TWD>;
73368ba0
SW		 153 };
154
58ecb23f 155 intc: interrupt-controller@50041000 {
0d4f7479 156 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 157 reg = <0x50041000 0x1000
158 0x50040100 0x0100>;
2eaab06e
SW		 159 interrupt-controller;
160 #interrupt-cells = <3>;
8e267f3d
GL		 161 };
162
58ecb23f 163 cache-controller@50043000 {
bb2c1de9
SW		 164 compatible = "arm,pl310-cache";
165 reg = <0x50043000 0x1000>;
166 arm,data-latency = <5 5 2>;
167 arm,tag-latency = <4 4 2>;
168 cache-unified;
169 cache-level = <2>;
170 };
171
2f2b7fb2
SW		 172 timer@60005000 {
173 compatible = "nvidia,tegra20-timer";
174 reg = <0x60005000 0x60>;
6cecf916
SW		 175 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 179 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
2f2b7fb2
SW		 180 };
181
58ecb23f 182 tegra_car: clock@60006000 {
270f8ce3
SW		 183 compatible = "nvidia,tegra20-car";
184 reg = <0x60006000 0x1000>;
185 #clock-cells = <1>;
3393d422 186 #reset-cells = <1>;
270f8ce3
SW		 187 };
188
58ecb23f 189 apbdma: dma@6000a000 {
8051b75a
SW		 190 compatible = "nvidia,tegra20-apbdma";
191 reg = <0x6000a000 0x1200>;
6cecf916
SW		 192 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 208 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
3393d422
SW		 209 resets = <&tegra_car 34>;
210 reset-names = "dma";
034d023f 211 #dma-cells = <1>;
8051b75a
SW		 212 };
213
58ecb23f 214 ahb@6000c004 {
c04abb3a
SW		 215 compatible = "nvidia,tegra20-ahb";
216 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d
GL		 217 };
218
58ecb23f 219 gpio: gpio@6000d000 {
8e267f3d 220 compatible = "nvidia,tegra20-gpio";
95decf84 221 reg = <0x6000d000 0x1000>;
6cecf916
SW		 222 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
8e267f3d
GL		 229 #gpio-cells = <2>;
230 gpio-controller;
6f74dc9b
SW		 231 #interrupt-cells = <2>;
232 interrupt-controller;
8e267f3d
GL		 233 };
234
58ecb23f 235 pinmux: pinmux@70000014 {
f62f548c 236 compatible = "nvidia,tegra20-pinmux";
95decf84
SW		 237 reg = <0x70000014 0x10 /* Tri-state registers */
238 0x70000080 0x20 /* Mux registers */
239 0x700000a0 0x14 /* Pull-up/down registers */
240 0x70000868 0xa8>; /* Pad control registers */
f62f548c
SW		 241 };
242
58ecb23f 243 das@70000c00 {
c04abb3a
SW		 244 compatible = "nvidia,tegra20-das";
245 reg = <0x70000c00 0x80>;
246 };
fc5c306b 247
58ecb23f 248 tegra_ac97: ac97@70002000 {
0698ed19
LS		 249 compatible = "nvidia,tegra20-ac97";
250 reg = <0x70002000 0x200>;
6cecf916 251 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 252 clocks = <&tegra_car TEGRA20_CLK_AC97>;
3393d422
SW		 253 resets = <&tegra_car 3>;
254 reset-names = "ac97";
034d023f
SW		 255 dmas = <&apbdma 12>, <&apbdma 12>;
256 dma-names = "rx", "tx";
0698ed19
LS		 257 status = "disabled";
258 };
c04abb3a
SW		 259
260 tegra_i2s1: i2s@70002800 {
261 compatible = "nvidia,tegra20-i2s";
262 reg = <0x70002800 0x200>;
6cecf916 263 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 264 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
3393d422
SW		 265 resets = <&tegra_car 11>;
266 reset-names = "i2s";
034d023f
SW		 267 dmas = <&apbdma 2>, <&apbdma 2>;
268 dma-names = "rx", "tx";
223ef78d 269 status = "disabled";
c04abb3a
SW		 270 };
271
272 tegra_i2s2: i2s@70002a00 {
273 compatible = "nvidia,tegra20-i2s";
274 reg = <0x70002a00 0x200>;
6cecf916 275 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 276 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
3393d422
SW		 277 resets = <&tegra_car 18>;
278 reset-names = "i2s";
034d023f
SW		 279 dmas = <&apbdma 1>, <&apbdma 1>;
280 dma-names = "rx", "tx";
223ef78d 281 status = "disabled";
c04abb3a
SW		 282 };
283
b6551bb9
LD		 284 /*
285 * There are two serial driver i.e. 8250 based simple serial
286 * driver and APB DMA based serial driver for higher baudrate
287 * and performace. To enable the 8250 based driver, the compatible
288 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
289 * driver, the comptible is "nvidia,tegra20-hsuart".
290 */
291 uarta: serial@70006000 {
8e267f3d
GL		 292 compatible = "nvidia,tegra20-uart";
293 reg = <0x70006000 0x40>;
294 reg-shift = <2>;
6cecf916 295 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 296 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
3393d422
SW		 297 resets = <&tegra_car 6>;
298 reset-names = "serial";
034d023f
SW		 299 dmas = <&apbdma 8>, <&apbdma 8>;
300 dma-names = "rx", "tx";
223ef78d 301 status = "disabled";
8e267f3d
GL		 302 };
303
b6551bb9 304 uartb: serial@70006040 {
8e267f3d
GL		 305 compatible = "nvidia,tegra20-uart";
306 reg = <0x70006040 0x40>;
307 reg-shift = <2>;
6cecf916 308 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 309 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
3393d422
SW		 310 resets = <&tegra_car 7>;
311 reset-names = "serial";
034d023f
SW		 312 dmas = <&apbdma 9>, <&apbdma 9>;
313 dma-names = "rx", "tx";
223ef78d 314 status = "disabled";
8e267f3d
GL		 315 };
316
b6551bb9 317 uartc: serial@70006200 {
8e267f3d
GL		 318 compatible = "nvidia,tegra20-uart";
319 reg = <0x70006200 0x100>;
320 reg-shift = <2>;
6cecf916 321 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 322 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
3393d422
SW		 323 resets = <&tegra_car 55>;
324 reset-names = "serial";
034d023f
SW		 325 dmas = <&apbdma 10>, <&apbdma 10>;
326 dma-names = "rx", "tx";
223ef78d 327 status = "disabled";
8e267f3d
GL		 328 };
329
b6551bb9 330 uartd: serial@70006300 {
8e267f3d
GL		 331 compatible = "nvidia,tegra20-uart";
332 reg = <0x70006300 0x100>;
333 reg-shift = <2>;
6cecf916 334 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 335 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
3393d422
SW		 336 resets = <&tegra_car 65>;
337 reset-names = "serial";
034d023f
SW		 338 dmas = <&apbdma 19>, <&apbdma 19>;
339 dma-names = "rx", "tx";
223ef78d 340 status = "disabled";
8e267f3d
GL		 341 };
342
b6551bb9 343 uarte: serial@70006400 {
8e267f3d
GL		 344 compatible = "nvidia,tegra20-uart";
345 reg = <0x70006400 0x100>;
346 reg-shift = <2>;
6cecf916 347 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 348 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
3393d422
SW		 349 resets = <&tegra_car 66>;
350 reset-names = "serial";
034d023f
SW		 351 dmas = <&apbdma 20>, <&apbdma 20>;
352 dma-names = "rx", "tx";
223ef78d 353 status = "disabled";
8e267f3d
GL		 354 };
355
58ecb23f 356 pwm: pwm@7000a000 {
140fd977
TR		 357 compatible = "nvidia,tegra20-pwm";
358 reg = <0x7000a000 0x100>;
359 #pwm-cells = <2>;
885a8cfa 360 clocks = <&tegra_car TEGRA20_CLK_PWM>;
3393d422
SW		 361 resets = <&tegra_car 17>;
362 reset-names = "pwm";
b69cd984 363 status = "disabled";
140fd977
TR		 364 };
365
58ecb23f 366 rtc@7000e000 {
380e04ac
SW		 367 compatible = "nvidia,tegra20-rtc";
368 reg = <0x7000e000 0x100>;
6cecf916 369 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 370 clocks = <&tegra_car TEGRA20_CLK_RTC>;
380e04ac
SW		 371 };
372
c04abb3a 373 i2c@7000c000 {
c04abb3a
SW		 374 compatible = "nvidia,tegra20-i2c";
375 reg = <0x7000c000 0x100>;
6cecf916 376 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 377 #address-cells = <1>;
378 #size-cells = <0>;
885a8cfa
HD		 379 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
380 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 381 clock-names = "div-clk", "fast-clk";
3393d422
SW		 382 resets = <&tegra_car 12>;
383 reset-names = "i2c";
034d023f
SW		 384 dmas = <&apbdma 21>, <&apbdma 21>;
385 dma-names = "rx", "tx";
223ef78d 386 status = "disabled";
0c6700ab
OJ		 387 };
388
fa98a114
LD		 389 spi@7000c380 {
390 compatible = "nvidia,tegra20-sflash";
391 reg = <0x7000c380 0x80>;
6cecf916 392 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
fa98a114
LD		 393 #address-cells = <1>;
394 #size-cells = <0>;
885a8cfa 395 clocks = <&tegra_car TEGRA20_CLK_SPI>;
3393d422
SW		 396 resets = <&tegra_car 43>;
397 reset-names = "spi";
034d023f
SW		 398 dmas = <&apbdma 11>, <&apbdma 11>;
399 dma-names = "rx", "tx";
fa98a114
LD		 400 status = "disabled";
401 };
402
c04abb3a 403 i2c@7000c400 {
c04abb3a
SW		 404 compatible = "nvidia,tegra20-i2c";
405 reg = <0x7000c400 0x100>;
6cecf916 406 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 407 #address-cells = <1>;
408 #size-cells = <0>;
885a8cfa
HD		 409 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
410 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 411 clock-names = "div-clk", "fast-clk";
3393d422
SW		 412 resets = <&tegra_car 54>;
413 reset-names = "i2c";
034d023f
SW		 414 dmas = <&apbdma 22>, <&apbdma 22>;
415 dma-names = "rx", "tx";
223ef78d 416 status = "disabled";
8e267f3d
GL		 417 };
418
c04abb3a 419 i2c@7000c500 {
c04abb3a
SW		 420 compatible = "nvidia,tegra20-i2c";
421 reg = <0x7000c500 0x100>;
6cecf916 422 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 423 #address-cells = <1>;
424 #size-cells = <0>;
885a8cfa
HD		 425 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
426 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 427 clock-names = "div-clk", "fast-clk";
3393d422
SW		 428 resets = <&tegra_car 67>;
429 reset-names = "i2c";
034d023f
SW		 430 dmas = <&apbdma 23>, <&apbdma 23>;
431 dma-names = "rx", "tx";
223ef78d 432 status = "disabled";
8e267f3d
GL		 433 };
434
c04abb3a 435 i2c@7000d000 {
c04abb3a
SW		 436 compatible = "nvidia,tegra20-i2c-dvc";
437 reg = <0x7000d000 0x200>;
6cecf916 438 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 439 #address-cells = <1>;
440 #size-cells = <0>;
885a8cfa
HD		 441 clocks = <&tegra_car TEGRA20_CLK_DVC>,
442 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 443 clock-names = "div-clk", "fast-clk";
3393d422
SW		 444 resets = <&tegra_car 47>;
445 reset-names = "i2c";
034d023f
SW		 446 dmas = <&apbdma 24>, <&apbdma 24>;
447 dma-names = "rx", "tx";
223ef78d 448 status = "disabled";
8e267f3d
GL		 449 };
450
a86b0db3
LD		 451 spi@7000d400 {
452 compatible = "nvidia,tegra20-slink";
453 reg = <0x7000d400 0x200>;
6cecf916 454 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 455 #address-cells = <1>;
456 #size-cells = <0>;
885a8cfa 457 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
3393d422
SW		 458 resets = <&tegra_car 41>;
459 reset-names = "spi";
034d023f
SW		 460 dmas = <&apbdma 15>, <&apbdma 15>;
461 dma-names = "rx", "tx";
a86b0db3
LD		 462 status = "disabled";
463 };
464
465 spi@7000d600 {
466 compatible = "nvidia,tegra20-slink";
467 reg = <0x7000d600 0x200>;
6cecf916 468 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 469 #address-cells = <1>;
470 #size-cells = <0>;
885a8cfa 471 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
3393d422
SW		 472 resets = <&tegra_car 44>;
473 reset-names = "spi";
034d023f
SW		 474 dmas = <&apbdma 16>, <&apbdma 16>;
475 dma-names = "rx", "tx";
a86b0db3
LD		 476 status = "disabled";
477 };
478
479 spi@7000d800 {
480 compatible = "nvidia,tegra20-slink";
57471c8d 481 reg = <0x7000d800 0x200>;
6cecf916 482 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 483 #address-cells = <1>;
484 #size-cells = <0>;
885a8cfa 485 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
3393d422
SW		 486 resets = <&tegra_car 46>;
487 reset-names = "spi";
034d023f
SW		 488 dmas = <&apbdma 17>, <&apbdma 17>;
489 dma-names = "rx", "tx";
a86b0db3
LD		 490 status = "disabled";
491 };
492
493 spi@7000da00 {
494 compatible = "nvidia,tegra20-slink";
495 reg = <0x7000da00 0x200>;
6cecf916 496 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 497 #address-cells = <1>;
498 #size-cells = <0>;
885a8cfa 499 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
3393d422
SW		 500 resets = <&tegra_car 68>;
501 reset-names = "spi";
034d023f
SW		 502 dmas = <&apbdma 18>, <&apbdma 18>;
503 dma-names = "rx", "tx";
a86b0db3
LD		 504 status = "disabled";
505 };
506
58ecb23f 507 kbc@7000e200 {
699ed4b9
LD		 508 compatible = "nvidia,tegra20-kbc";
509 reg = <0x7000e200 0x100>;
6cecf916 510 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 511 clocks = <&tegra_car TEGRA20_CLK_KBC>;
3393d422
SW		 512 resets = <&tegra_car 36>;
513 reset-names = "kbc";
699ed4b9
LD		 514 status = "disabled";
515 };
516
58ecb23f 517 pmc@7000e400 {
c04abb3a
SW		 518 compatible = "nvidia,tegra20-pmc";
519 reg = <0x7000e400 0x400>;
885a8cfa 520 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
7021d122 521 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 522 };
523
bbfc33bd 524 memory-controller@7000f000 {
c04abb3a
SW		 525 compatible = "nvidia,tegra20-mc";
526 reg = <0x7000f000 0x024
527 0x7000f03c 0x3c4>;
6cecf916 528 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a
SW		 529 };
530
58ecb23f 531 iommu@7000f024 {
c04abb3a
SW		 532 compatible = "nvidia,tegra20-gart";
533 reg = <0x7000f024 0x00000018 /* controller registers */
534 0x58000000 0x02000000>; /* GART aperture */
535 };
536
bbfc33bd 537 memory-controller@7000f400 {
c04abb3a
SW		 538 compatible = "nvidia,tegra20-emc";
539 reg = <0x7000f400 0x200>;
2eaab06e
SW		 540 #address-cells = <1>;
541 #size-cells = <0>;
8e267f3d 542 };
c27317c0 543
58ecb23f 544 pcie-controller@80003000 {
1b62b611
TR		 545 compatible = "nvidia,tegra20-pcie";
546 device_type = "pci";
547 reg = <0x80003000 0x00000800 /* PADS registers */
548 0x80003800 0x00000200 /* AFI registers */
549 0x90000000 0x10000000>; /* configuration space */
550 reg-names = "pads", "afi", "cs";
551 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
552 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
553 interrupt-names = "intr", "msi";
554
555 bus-range = <0x00 0xff>;
556 #address-cells = <3>;
557 #size-cells = <2>;
558
559 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
560 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
561 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 562 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
563 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
1b62b611
TR		 564
565 clocks = <&tegra_car TEGRA20_CLK_PEX>,
566 <&tegra_car TEGRA20_CLK_AFI>,
1b62b611 567 <&tegra_car TEGRA20_CLK_PLL_E>;
2bd541ff 568 clock-names = "pex", "afi", "pll_e";
3393d422
SW		 569 resets = <&tegra_car 70>,
570 <&tegra_car 72>,
571 <&tegra_car 74>;
572 reset-names = "pex", "afi", "pcie_x";
1b62b611
TR		 573 status = "disabled";
574
575 pci@1,0 {
576 device_type = "pci";
577 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
578 reg = <0x000800 0 0 0 0>;
579 status = "disabled";
580
581 #address-cells = <3>;
582 #size-cells = <2>;
583 ranges;
584
585 nvidia,num-lanes = <2>;
586 };
587
588 pci@2,0 {
589 device_type = "pci";
590 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
591 reg = <0x001000 0 0 0 0>;
592 status = "disabled";
593
594 #address-cells = <3>;
595 #size-cells = <2>;
596 ranges;
597
598 nvidia,num-lanes = <2>;
599 };
600 };
601
c27317c0
OJ		 602 usb@c5000000 {
603 compatible = "nvidia,tegra20-ehci", "usb-ehci";
604 reg = <0xc5000000 0x4000>;
6cecf916 605 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 606 phy_type = "utmi";
ba202f15 607 nvidia,has-legacy-mode;
885a8cfa 608 clocks = <&tegra_car TEGRA20_CLK_USBD>;
3393d422
SW		 609 resets = <&tegra_car 22>;
610 reset-names = "usb";
b4e07478 611 nvidia,needs-double-reset;
e374b65c 612 nvidia,phy = <&phy1>;
223ef78d 613 status = "disabled";
c27317c0
OJ		 614 };
615
4c94c8b5 616 phy1: usb-phy@c5000000 {
5d324410 617 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 618 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
5d324410 619 phy_type = "utmi";
885a8cfa
HD		 620 clocks = <&tegra_car TEGRA20_CLK_USBD>,
621 <&tegra_car TEGRA20_CLK_PLL_U>,
622 <&tegra_car TEGRA20_CLK_CLK_M>,
623 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 624 clock-names = "reg", "pll_u", "timer", "utmi-pads";
5d324410 625 nvidia,has-legacy-mode;
c49667e5
MP		 626 nvidia,hssync-start-delay = <9>;
627 nvidia,idle-wait-delay = <17>;
628 nvidia,elastic-limit = <16>;
629 nvidia,term-range-adj = <6>;
630 nvidia,xcvr-setup = <9>;
631 nvidia,xcvr-lsfslew = <1>;
632 nvidia,xcvr-lsrslew = <1>;
4c94c8b5 633 status = "disabled";
5d324410
SW		 634 };
635
c27317c0
OJ		 636 usb@c5004000 {
637 compatible = "nvidia,tegra20-ehci", "usb-ehci";
638 reg = <0xc5004000 0x4000>;
6cecf916 639 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 640 phy_type = "ulpi";
885a8cfa 641 clocks = <&tegra_car TEGRA20_CLK_USB2>;
3393d422
SW		 642 resets = <&tegra_car 58>;
643 reset-names = "usb";
e374b65c 644 nvidia,phy = <&phy2>;
223ef78d 645 status = "disabled";
c27317c0
OJ		 646 };
647
4c94c8b5 648 phy2: usb-phy@c5004000 {
5d324410 649 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 650 reg = <0xc5004000 0x4000>;
5d324410 651 phy_type = "ulpi";
885a8cfa
HD		 652 clocks = <&tegra_car TEGRA20_CLK_USB2>,
653 <&tegra_car TEGRA20_CLK_PLL_U>,
654 <&tegra_car TEGRA20_CLK_CDEV2>;
4c94c8b5
VB		 655 clock-names = "reg", "pll_u", "ulpi-link";
656 status = "disabled";
5d324410
SW		 657 };
658
c27317c0
OJ		 659 usb@c5008000 {
660 compatible = "nvidia,tegra20-ehci", "usb-ehci";
661 reg = <0xc5008000 0x4000>;
6cecf916 662 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 663 phy_type = "utmi";
885a8cfa 664 clocks = <&tegra_car TEGRA20_CLK_USB3>;
3393d422
SW		 665 resets = <&tegra_car 59>;
666 reset-names = "usb";
e374b65c 667 nvidia,phy = <&phy3>;
223ef78d 668 status = "disabled";
c27317c0 669 };
7868a9bc 670
4c94c8b5 671 phy3: usb-phy@c5008000 {
5d324410 672 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 673 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
5d324410 674 phy_type = "utmi";
885a8cfa
HD		 675 clocks = <&tegra_car TEGRA20_CLK_USB3>,
676 <&tegra_car TEGRA20_CLK_PLL_U>,
677 <&tegra_car TEGRA20_CLK_CLK_M>,
678 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 679 clock-names = "reg", "pll_u", "timer", "utmi-pads";
c49667e5
MP		 680 nvidia,hssync-start-delay = <9>;
681 nvidia,idle-wait-delay = <17>;
682 nvidia,elastic-limit = <16>;
683 nvidia,term-range-adj = <6>;
684 nvidia,xcvr-setup = <9>;
685 nvidia,xcvr-lsfslew = <2>;
686 nvidia,xcvr-lsrslew = <2>;
4c94c8b5 687 status = "disabled";
5d324410
SW		 688 };
689
c04abb3a
SW		 690 sdhci@c8000000 {
691 compatible = "nvidia,tegra20-sdhci";
692 reg = <0xc8000000 0x200>;
6cecf916 693 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 694 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
3393d422
SW		 695 resets = <&tegra_car 14>;
696 reset-names = "sdhci";
223ef78d 697 status = "disabled";
7868a9bc 698 };
4a82f2b3 699
c04abb3a
SW		 700 sdhci@c8000200 {
701 compatible = "nvidia,tegra20-sdhci";
702 reg = <0xc8000200 0x200>;
6cecf916 703 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 704 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
3393d422
SW		 705 resets = <&tegra_car 9>;
706 reset-names = "sdhci";
223ef78d 707 status = "disabled";
4a82f2b3 708 };
6a943e0e 709
c04abb3a
SW		 710 sdhci@c8000400 {
711 compatible = "nvidia,tegra20-sdhci";
712 reg = <0xc8000400 0x200>;
6cecf916 713 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 714 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
3393d422
SW		 715 resets = <&tegra_car 69>;
716 reset-names = "sdhci";
223ef78d 717 status = "disabled";
c04abb3a
SW		 718 };
719
720 sdhci@c8000600 {
721 compatible = "nvidia,tegra20-sdhci";
722 reg = <0xc8000600 0x200>;
6cecf916 723 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 724 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
3393d422
SW		 725 resets = <&tegra_car 15>;
726 reset-names = "sdhci";
223ef78d 727 status = "disabled";
c04abb3a
SW		 728 };
729
4dd2bd37
HD		 730 cpus {
731 #address-cells = <1>;
732 #size-cells = <0>;
733
734 cpu@0 {
735 device_type = "cpu";
736 compatible = "arm,cortex-a9";
737 reg = <0>;
738 };
739
740 cpu@1 {
741 device_type = "cpu";
742 compatible = "arm,cortex-a9";
743 reg = <1>;
744 };
745 };
746
c04abb3a
SW		 747 pmu {
748 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 749 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6a943e0e 751 };
8e267f3d 752};
Linux 6.x block layer and io_uring tree(s)