[linux-2.6-block.git] / arch / arm / boot / dts / tegra20.dtsi

#include <dt-bindings/gpio/tegra-gpio.h>

#include "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
		serial4 = &uarte;
	};

	host1x {
		compatible = "nvidia,tegra20-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <0 65 0x04   /* mpcore syncpt */
			      0 67 0x04>; /* mpcore general */
		clocks = <&tegra_car 28>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra20-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <0 68 0x04>;
			clocks = <&tegra_car 60>;
		};

		vi {
			compatible = "nvidia,tegra20-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <0 69 0x04>;
			clocks = <&tegra_car 100>;
		};

		epp {
			compatible = "nvidia,tegra20-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <0 70 0x04>;
			clocks = <&tegra_car 19>;
		};

		isp {
			compatible = "nvidia,tegra20-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <0 71 0x04>;
			clocks = <&tegra_car 23>;
		};

		gr2d {
			compatible = "nvidia,tegra20-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <0 72 0x04>;
			clocks = <&tegra_car 21>;
		};

		gr3d {
			compatible = "nvidia,tegra20-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car 24>;
		};

		dc@54200000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <0 73 0x04>;
			clocks = <&tegra_car 27>, <&tegra_car 121>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <0 74 0x04>;
			clocks = <&tegra_car 26>, <&tegra_car 121>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra20-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <0 75 0x04>;
			clocks = <&tegra_car 51>, <&tegra_car 117>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra20-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <0 76 0x04>;
			clocks = <&tegra_car 102>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra20-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car 48>;
			status = "disabled";
		};
	};

	timer@50004600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupts = <1 13 0x304>;
		clocks = <&tegra_car 132>;
	};

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <5 5 2>;
		arm,tag-latency = <4 4 2>;
		cache-unified;
		cache-level = <2>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra20-timer";
		reg = <0x60005000 0x60>;
		interrupts = <0 0 0x04
			      0 1 0x04
			      0 41 0x04
			      0 42 0x04>;
		clocks = <&tegra_car 5>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra20-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1200>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04>;
		clocks = <&tegra_car 34>;
	};

	ahb {
		compatible = "nvidia,tegra20-ahb";
		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra20-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra20-pinmux";
		reg = <0x70000014 0x10   /* Tri-state registers */
		       0x70000080 0x20   /* Mux registers */
		       0x700000a0 0x14   /* Pull-up/down registers */
		       0x70000868 0xa8>; /* Pad control registers */
	};

	das {
		compatible = "nvidia,tegra20-das";
		reg = <0x70000c00 0x80>;
	};

	tegra_ac97: ac97 {
		compatible = "nvidia,tegra20-ac97";
		reg = <0x70002000 0x200>;
		interrupts = <0 81 0x04>;
		nvidia,dma-request-selector = <&apbdma 12>;
		clocks = <&tegra_car 3>;
		status = "disabled";
	};

	tegra_i2s1: i2s@70002800 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002800 0x200>;
		interrupts = <0 13 0x04>;
		nvidia,dma-request-selector = <&apbdma 2>;
		clocks = <&tegra_car 11>;
		status = "disabled";
	};

	tegra_i2s2: i2s@70002a00 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002a00 0x200>;
		interrupts = <0 3 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car 18>;
		status = "disabled";
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	 * driver, the comptible is "nvidia,tegra20-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
		nvidia,dma-request-selector = <&apbdma 8>;
		clocks = <&tegra_car 6>;
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
		nvidia,dma-request-selector = <&apbdma 9>;
		clocks = <&tegra_car 96>;
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
		nvidia,dma-request-selector = <&apbdma 10>;
		clocks = <&tegra_car 55>;
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
		nvidia,dma-request-selector = <&apbdma 19>;
		clocks = <&tegra_car 65>;
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
		nvidia,dma-request-selector = <&apbdma 20>;
		clocks = <&tegra_car 66>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
		status = "disabled";
	};

	rtc {
		compatible = "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <0 2 0x04>;
		clocks = <&tegra_car 4>;
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000c380 {
		compatible = "nvidia,tegra20-sflash";
		reg = <0x7000c380 0x80>;
		interrupts = <0 39 0x04>;
		nvidia,dma-request-selector = <&apbdma 11>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 43>;
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra20-i2c-dvc";
		reg = <0x7000d000 0x200>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <0 59 0x04>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <0 82 0x04>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d800 0x200>;
		interrupts = <0 83 0x04>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <0 93 0x04>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		status = "disabled";
	};

	kbc {
		compatible = "nvidia,tegra20-kbc";
		reg = <0x7000e200 0x100>;
		interrupts = <0 85 0x04>;
		clocks = <&tegra_car 36>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra20-pmc";
		reg = <0x7000e400 0x400>;
		clocks = <&tegra_car 110>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
	};

	memory-controller@7000f000 {
		compatible = "nvidia,tegra20-mc";
		reg = <0x7000f000 0x024
		       0x7000f03c 0x3c4>;
		interrupts = <0 77 0x04>;
	};

	iommu {
		compatible = "nvidia,tegra20-gart";
		reg = <0x7000f024 0x00000018	/* controller registers */
		       0x58000000 0x02000000>;	/* GART aperture */
	};

	memory-controller@7000f400 {
		compatible = "nvidia,tegra20-emc";
		reg = <0x7000f400 0x200>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	usb@c5000000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5000000 0x4000>;
		interrupts = <0 20 0x04>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>;
		nvidia,needs-double-reset;
		nvidia,phy = <&phy1>;
		status = "disabled";
	};

	phy1: usb-phy@c5000000 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
		phy_type = "utmi";
		clocks = <&tegra_car 22>,
			 <&tegra_car 127>,
			 <&tegra_car 106>,
			 <&tegra_car 22>;
		clock-names = "reg", "pll_u", "timer", "utmi-pads";
		nvidia,has-legacy-mode;
		hssync_start_delay = <9>;
		idle_wait_delay = <17>;
		elastic_limit = <16>;
		term_range_adj = <6>;
		xcvr_setup = <9>;
		xcvr_lsfslew = <1>;
		xcvr_lsrslew = <1>;
		status = "disabled";
	};

	usb@c5004000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5004000 0x4000>;
		interrupts = <0 21 0x04>;
		phy_type = "ulpi";
		clocks = <&tegra_car 58>;
		nvidia,phy = <&phy2>;
		status = "disabled";
	};

	phy2: usb-phy@c5004000 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5004000 0x4000>;
		phy_type = "ulpi";
		clocks = <&tegra_car 58>,
			 <&tegra_car 127>,
			 <&tegra_car 93>;
		clock-names = "reg", "pll_u", "ulpi-link";
		status = "disabled";
	};

	usb@c5008000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5008000 0x4000>;
		interrupts = <0 97 0x04>;
		phy_type = "utmi";
		clocks = <&tegra_car 59>;
		nvidia,phy = <&phy3>;
		status = "disabled";
	};

	phy3: usb-phy@c5008000 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
		phy_type = "utmi";
		clocks = <&tegra_car 59>,
			 <&tegra_car 127>,
			 <&tegra_car 106>,
			 <&tegra_car 22>;
		clock-names = "reg", "pll_u", "timer", "utmi-pads";
		hssync_start_delay = <9>;
		idle_wait_delay = <17>;
		elastic_limit = <16>;
		term_range_adj = <6>;
		xcvr_setup = <9>;
		xcvr_lsfslew = <2>;
		xcvr_lsrslew = <2>;
		status = "disabled";
	};

	sdhci@c8000000 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000000 0x200>;
		interrupts = <0 14 0x04>;
		clocks = <&tegra_car 14>;
		status = "disabled";
	};

	sdhci@c8000200 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000200 0x200>;
		interrupts = <0 15 0x04>;
		clocks = <&tegra_car 9>;
		status = "disabled";
	};

	sdhci@c8000400 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000400 0x200>;
		interrupts = <0 19 0x04>;
		clocks = <&tegra_car 69>;
		status = "disabled";
	};

	sdhci@c8000600 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000600 0x200>;
		interrupts = <0 31 0x04>;
		clocks = <&tegra_car 15>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 56 0x04
			      0 57 0x04>;
	};
};
Commit	Line	Data
3325f1bc SW	1	#include <dt-bindings/gpio/tegra-gpio.h>
3325f1bc SW	2
1bd0bd49	3	#include "skeleton.dtsi"
8e267f3d GL	4
	5	/ {
	6	compatible = "nvidia,tegra20";
	7	interrupt-parent = <&intc>;
	8
b6551bb9 LD	9	aliases {
	10	serial0 = &uarta;
	11	serial1 = &uartb;
	12	serial2 = &uartc;
	13	serial3 = &uartd;
	14	serial4 = &uarte;
	15	};
	16
ed821f07 TR	17	host1x {
	18	compatible = "nvidia,tegra20-host1x", "simple-bus";
	19	reg = <0x50000000 0x00024000>;
	20	interrupts = <0 65 0x04 /* mpcore syncpt */
	21	0 67 0x04>; /* mpcore general */
8d8b43da	22	clocks = <&tegra_car 28>;
ed821f07 TR	23
	24	#address-cells = <1>;
	25	#size-cells = <1>;
	26
	27	ranges = <0x54000000 0x54000000 0x04000000>;
	28
	29	mpe {
	30	compatible = "nvidia,tegra20-mpe";
	31	reg = <0x54040000 0x00040000>;
	32	interrupts = <0 68 0x04>;
8d8b43da	33	clocks = <&tegra_car 60>;
ed821f07 TR	34	};
	35
	36	vi {
	37	compatible = "nvidia,tegra20-vi";
	38	reg = <0x54080000 0x00040000>;
	39	interrupts = <0 69 0x04>;
8d8b43da	40	clocks = <&tegra_car 100>;
ed821f07 TR	41	};
	42
	43	epp {
	44	compatible = "nvidia,tegra20-epp";
	45	reg = <0x540c0000 0x00040000>;
	46	interrupts = <0 70 0x04>;
8d8b43da	47	clocks = <&tegra_car 19>;
ed821f07 TR	48	};
	49
	50	isp {
	51	compatible = "nvidia,tegra20-isp";
	52	reg = <0x54100000 0x00040000>;
	53	interrupts = <0 71 0x04>;
8d8b43da	54	clocks = <&tegra_car 23>;
ed821f07 TR	55	};
	56
	57	gr2d {
	58	compatible = "nvidia,tegra20-gr2d";
	59	reg = <0x54140000 0x00040000>;
	60	interrupts = <0 72 0x04>;
8d8b43da	61	clocks = <&tegra_car 21>;
ed821f07 TR	62	};
	63
	64	gr3d {
	65	compatible = "nvidia,tegra20-gr3d";
	66	reg = <0x54180000 0x00040000>;
8d8b43da	67	clocks = <&tegra_car 24>;
ed821f07 TR	68	};
	69
	70	dc@54200000 {
	71	compatible = "nvidia,tegra20-dc";
	72	reg = <0x54200000 0x00040000>;
	73	interrupts = <0 73 0x04>;
8d8b43da PG	74	clocks = <&tegra_car 27>, <&tegra_car 121>;
8d8b43da PG	75	clock-names = "disp1", "parent";
ed821f07 TR	76
	77	rgb {
	78	status = "disabled";
	79	};
	80	};
	81
	82	dc@54240000 {
	83	compatible = "nvidia,tegra20-dc";
	84	reg = <0x54240000 0x00040000>;
	85	interrupts = <0 74 0x04>;
8d8b43da PG	86	clocks = <&tegra_car 26>, <&tegra_car 121>;
8d8b43da PG	87	clock-names = "disp2", "parent";
ed821f07 TR	88
	89	rgb {
	90	status = "disabled";
	91	};
	92	};
	93
	94	hdmi {
	95	compatible = "nvidia,tegra20-hdmi";
	96	reg = <0x54280000 0x00040000>;
	97	interrupts = <0 75 0x04>;
8d8b43da PG	98	clocks = <&tegra_car 51>, <&tegra_car 117>;
8d8b43da PG	99	clock-names = "hdmi", "parent";
ed821f07 TR	100	status = "disabled";
	101	};
	102
	103	tvo {
	104	compatible = "nvidia,tegra20-tvo";
	105	reg = <0x542c0000 0x00040000>;
	106	interrupts = <0 76 0x04>;
8d8b43da	107	clocks = <&tegra_car 102>;
ed821f07 TR	108	status = "disabled";
	109	};
	110
	111	dsi {
	112	compatible = "nvidia,tegra20-dsi";
	113	reg = <0x54300000 0x00040000>;
8d8b43da	114	clocks = <&tegra_car 48>;
ed821f07 TR	115	status = "disabled";
	116	};
	117	};
	118
73368ba0 SW	119	timer@50004600 {
	120	compatible = "arm,cortex-a9-twd-timer";
	121	reg = <0x50040600 0x20>;
	122	interrupts = <1 13 0x304>;
ed3ced37	123	clocks = <&tegra_car 132>;
73368ba0 SW	124	};
73368ba0 SW	125
f9eb26a4	126	intc: interrupt-controller {
0d4f7479	127	compatible = "arm,cortex-a9-gic";
5ff48887 SW	128	reg = <0x50041000 0x1000
5ff48887 SW	129	0x50040100 0x0100>;
2eaab06e SW	130	interrupt-controller;
2eaab06e SW	131	#interrupt-cells = <3>;
8e267f3d GL	132	};
8e267f3d GL	133
bb2c1de9 SW	134	cache-controller {
	135	compatible = "arm,pl310-cache";
	136	reg = <0x50043000 0x1000>;
	137	arm,data-latency = <5 5 2>;
	138	arm,tag-latency = <4 4 2>;
	139	cache-unified;
	140	cache-level = <2>;
	141	};
	142
2f2b7fb2 SW	143	timer@60005000 {
	144	compatible = "nvidia,tegra20-timer";
	145	reg = <0x60005000 0x60>;
	146	interrupts = <0 0 0x04
	147	0 1 0x04
	148	0 41 0x04
	149	0 42 0x04>;
6f88fb8a	150	clocks = <&tegra_car 5>;
2f2b7fb2 SW	151	};
2f2b7fb2 SW	152
270f8ce3 SW	153	tegra_car: clock {
	154	compatible = "nvidia,tegra20-car";
	155	reg = <0x60006000 0x1000>;
	156	#clock-cells = <1>;
	157	};
	158
f9eb26a4	159	apbdma: dma {
8051b75a SW	160	compatible = "nvidia,tegra20-apbdma";
8051b75a SW	161	reg = <0x6000a000 0x1200>;
95decf84 SW	162	interrupts = <0 104 0x04
	163	0 105 0x04
	164	0 106 0x04
	165	0 107 0x04
	166	0 108 0x04
	167	0 109 0x04
	168	0 110 0x04
	169	0 111 0x04
	170	0 112 0x04
	171	0 113 0x04
	172	0 114 0x04
	173	0 115 0x04
	174	0 116 0x04
	175	0 117 0x04
	176	0 118 0x04
	177	0 119 0x04>;
8d8b43da	178	clocks = <&tegra_car 34>;
8051b75a SW	179	};
8051b75a SW	180
c04abb3a SW	181	ahb {
	182	compatible = "nvidia,tegra20-ahb";
	183	reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d GL	184	};
8e267f3d GL	185
f9eb26a4	186	gpio: gpio {
8e267f3d	187	compatible = "nvidia,tegra20-gpio";
95decf84 SW	188	reg = <0x6000d000 0x1000>;
	189	interrupts = <0 32 0x04
	190	0 33 0x04
	191	0 34 0x04
	192	0 35 0x04
	193	0 55 0x04
	194	0 87 0x04
	195	0 89 0x04>;
8e267f3d GL	196	#gpio-cells = <2>;
8e267f3d GL	197	gpio-controller;
6f74dc9b SW	198	#interrupt-cells = <2>;
6f74dc9b SW	199	interrupt-controller;
8e267f3d GL	200	};
8e267f3d GL	201
f9eb26a4	202	pinmux: pinmux {
f62f548c	203	compatible = "nvidia,tegra20-pinmux";
95decf84 SW	204	reg = <0x70000014 0x10 /* Tri-state registers */
	205	0x70000080 0x20 /* Mux registers */
	206	0x700000a0 0x14 /* Pull-up/down registers */
	207	0x70000868 0xa8>; /* Pad control registers */
f62f548c SW	208	};
f62f548c SW	209
c04abb3a SW	210	das {
	211	compatible = "nvidia,tegra20-das";
	212	reg = <0x70000c00 0x80>;
	213	};
fc5c306b	214
0698ed19 LS	215	tegra_ac97: ac97 {
	216	compatible = "nvidia,tegra20-ac97";
	217	reg = <0x70002000 0x200>;
	218	interrupts = <0 81 0x04>;
	219	nvidia,dma-request-selector = <&apbdma 12>;
	220	clocks = <&tegra_car 3>;
	221	status = "disabled";
	222	};
c04abb3a SW	223
	224	tegra_i2s1: i2s@70002800 {
	225	compatible = "nvidia,tegra20-i2s";
	226	reg = <0x70002800 0x200>;
	227	interrupts = <0 13 0x04>;
	228	nvidia,dma-request-selector = <&apbdma 2>;
8d8b43da	229	clocks = <&tegra_car 11>;
223ef78d	230	status = "disabled";
c04abb3a SW	231	};
	232
	233	tegra_i2s2: i2s@70002a00 {
	234	compatible = "nvidia,tegra20-i2s";
	235	reg = <0x70002a00 0x200>;
	236	interrupts = <0 3 0x04>;
	237	nvidia,dma-request-selector = <&apbdma 1>;
8d8b43da	238	clocks = <&tegra_car 18>;
223ef78d	239	status = "disabled";
c04abb3a SW	240	};
c04abb3a SW	241
b6551bb9 LD	242	/*
	243	* There are two serial driver i.e. 8250 based simple serial
	244	* driver and APB DMA based serial driver for higher baudrate
	245	* and performace. To enable the 8250 based driver, the compatible
	246	* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	247	* driver, the comptible is "nvidia,tegra20-hsuart".
	248	*/
	249	uarta: serial@70006000 {
8e267f3d GL	250	compatible = "nvidia,tegra20-uart";
	251	reg = <0x70006000 0x40>;
	252	reg-shift = <2>;
95decf84	253	interrupts = <0 36 0x04>;
b6551bb9	254	nvidia,dma-request-selector = <&apbdma 8>;
8d8b43da	255	clocks = <&tegra_car 6>;
223ef78d	256	status = "disabled";
8e267f3d GL	257	};
8e267f3d GL	258
b6551bb9	259	uartb: serial@70006040 {
8e267f3d GL	260	compatible = "nvidia,tegra20-uart";
	261	reg = <0x70006040 0x40>;
	262	reg-shift = <2>;
95decf84	263	interrupts = <0 37 0x04>;
b6551bb9	264	nvidia,dma-request-selector = <&apbdma 9>;
8d8b43da	265	clocks = <&tegra_car 96>;
223ef78d	266	status = "disabled";
8e267f3d GL	267	};
8e267f3d GL	268
b6551bb9	269	uartc: serial@70006200 {
8e267f3d GL	270	compatible = "nvidia,tegra20-uart";
	271	reg = <0x70006200 0x100>;
	272	reg-shift = <2>;
95decf84	273	interrupts = <0 46 0x04>;
b6551bb9	274	nvidia,dma-request-selector = <&apbdma 10>;
8d8b43da	275	clocks = <&tegra_car 55>;
223ef78d	276	status = "disabled";
8e267f3d GL	277	};
8e267f3d GL	278
b6551bb9	279	uartd: serial@70006300 {
8e267f3d GL	280	compatible = "nvidia,tegra20-uart";
	281	reg = <0x70006300 0x100>;
	282	reg-shift = <2>;
95decf84	283	interrupts = <0 90 0x04>;
b6551bb9	284	nvidia,dma-request-selector = <&apbdma 19>;
8d8b43da	285	clocks = <&tegra_car 65>;
223ef78d	286	status = "disabled";
8e267f3d GL	287	};
8e267f3d GL	288
b6551bb9	289	uarte: serial@70006400 {
8e267f3d GL	290	compatible = "nvidia,tegra20-uart";
	291	reg = <0x70006400 0x100>;
	292	reg-shift = <2>;
95decf84	293	interrupts = <0 91 0x04>;
b6551bb9	294	nvidia,dma-request-selector = <&apbdma 20>;
8d8b43da	295	clocks = <&tegra_car 66>;
223ef78d	296	status = "disabled";
8e267f3d GL	297	};
8e267f3d GL	298
2b8b15da	299	pwm: pwm {
140fd977 TR	300	compatible = "nvidia,tegra20-pwm";
	301	reg = <0x7000a000 0x100>;
	302	#pwm-cells = <2>;
8d8b43da	303	clocks = <&tegra_car 17>;
b69cd984	304	status = "disabled";
140fd977 TR	305	};
140fd977 TR	306
380e04ac SW	307	rtc {
	308	compatible = "nvidia,tegra20-rtc";
	309	reg = <0x7000e000 0x100>;
	310	interrupts = <0 2 0x04>;
6f88fb8a	311	clocks = <&tegra_car 4>;
380e04ac SW	312	};
380e04ac SW	313
c04abb3a	314	i2c@7000c000 {
c04abb3a SW	315	compatible = "nvidia,tegra20-i2c";
	316	reg = <0x7000c000 0x100>;
	317	interrupts = <0 38 0x04>;
2eaab06e SW	318	#address-cells = <1>;
2eaab06e SW	319	#size-cells = <0>;
8d8b43da PG	320	clocks = <&tegra_car 12>, <&tegra_car 124>;
8d8b43da PG	321	clock-names = "div-clk", "fast-clk";
223ef78d	322	status = "disabled";
0c6700ab OJ	323	};
0c6700ab OJ	324
fa98a114 LD	325	spi@7000c380 {
	326	compatible = "nvidia,tegra20-sflash";
	327	reg = <0x7000c380 0x80>;
	328	interrupts = <0 39 0x04>;
	329	nvidia,dma-request-selector = <&apbdma 11>;
	330	#address-cells = <1>;
	331	#size-cells = <0>;
8d8b43da	332	clocks = <&tegra_car 43>;
fa98a114 LD	333	status = "disabled";
	334	};
	335
c04abb3a	336	i2c@7000c400 {
c04abb3a SW	337	compatible = "nvidia,tegra20-i2c";
	338	reg = <0x7000c400 0x100>;
	339	interrupts = <0 84 0x04>;
2eaab06e SW	340	#address-cells = <1>;
2eaab06e SW	341	#size-cells = <0>;
8d8b43da PG	342	clocks = <&tegra_car 54>, <&tegra_car 124>;
8d8b43da PG	343	clock-names = "div-clk", "fast-clk";
223ef78d	344	status = "disabled";
8e267f3d GL	345	};
8e267f3d GL	346
c04abb3a	347	i2c@7000c500 {
c04abb3a SW	348	compatible = "nvidia,tegra20-i2c";
	349	reg = <0x7000c500 0x100>;
	350	interrupts = <0 92 0x04>;
2eaab06e SW	351	#address-cells = <1>;
2eaab06e SW	352	#size-cells = <0>;
8d8b43da PG	353	clocks = <&tegra_car 67>, <&tegra_car 124>;
8d8b43da PG	354	clock-names = "div-clk", "fast-clk";
223ef78d	355	status = "disabled";
8e267f3d GL	356	};
8e267f3d GL	357
c04abb3a	358	i2c@7000d000 {
c04abb3a SW	359	compatible = "nvidia,tegra20-i2c-dvc";
	360	reg = <0x7000d000 0x200>;
	361	interrupts = <0 53 0x04>;
2eaab06e SW	362	#address-cells = <1>;
2eaab06e SW	363	#size-cells = <0>;
8d8b43da PG	364	clocks = <&tegra_car 47>, <&tegra_car 124>;
8d8b43da PG	365	clock-names = "div-clk", "fast-clk";
223ef78d	366	status = "disabled";
8e267f3d GL	367	};
8e267f3d GL	368
a86b0db3 LD	369	spi@7000d400 {
	370	compatible = "nvidia,tegra20-slink";
	371	reg = <0x7000d400 0x200>;
	372	interrupts = <0 59 0x04>;
	373	nvidia,dma-request-selector = <&apbdma 15>;
	374	#address-cells = <1>;
	375	#size-cells = <0>;
8d8b43da	376	clocks = <&tegra_car 41>;
a86b0db3 LD	377	status = "disabled";
	378	};
	379
	380	spi@7000d600 {
	381	compatible = "nvidia,tegra20-slink";
	382	reg = <0x7000d600 0x200>;
	383	interrupts = <0 82 0x04>;
	384	nvidia,dma-request-selector = <&apbdma 16>;
	385	#address-cells = <1>;
	386	#size-cells = <0>;
8d8b43da	387	clocks = <&tegra_car 44>;
a86b0db3 LD	388	status = "disabled";
	389	};
	390
	391	spi@7000d800 {
	392	compatible = "nvidia,tegra20-slink";
57471c8d	393	reg = <0x7000d800 0x200>;
a86b0db3 LD	394	interrupts = <0 83 0x04>;
	395	nvidia,dma-request-selector = <&apbdma 17>;
	396	#address-cells = <1>;
	397	#size-cells = <0>;
8d8b43da	398	clocks = <&tegra_car 46>;
a86b0db3 LD	399	status = "disabled";
	400	};
	401
	402	spi@7000da00 {
	403	compatible = "nvidia,tegra20-slink";
	404	reg = <0x7000da00 0x200>;
	405	interrupts = <0 93 0x04>;
	406	nvidia,dma-request-selector = <&apbdma 18>;
	407	#address-cells = <1>;
	408	#size-cells = <0>;
8d8b43da	409	clocks = <&tegra_car 68>;
a86b0db3 LD	410	status = "disabled";
	411	};
	412
699ed4b9 LD	413	kbc {
	414	compatible = "nvidia,tegra20-kbc";
	415	reg = <0x7000e200 0x100>;
	416	interrupts = <0 85 0x04>;
	417	clocks = <&tegra_car 36>;
	418	status = "disabled";
	419	};
	420
c04abb3a SW	421	pmc {
	422	compatible = "nvidia,tegra20-pmc";
	423	reg = <0x7000e400 0x400>;
7021d122 JL	424	clocks = <&tegra_car 110>, <&clk32k_in>;
7021d122 JL	425	clock-names = "pclk", "clk32k_in";
c04abb3a SW	426	};
c04abb3a SW	427
bbfc33bd	428	memory-controller@7000f000 {
c04abb3a SW	429	compatible = "nvidia,tegra20-mc";
	430	reg = <0x7000f000 0x024
	431	0x7000f03c 0x3c4>;
	432	interrupts = <0 77 0x04>;
	433	};
	434
109269e8	435	iommu {
c04abb3a SW	436	compatible = "nvidia,tegra20-gart";
	437	reg = <0x7000f024 0x00000018 /* controller registers */
	438	0x58000000 0x02000000>; /* GART aperture */
	439	};
	440
bbfc33bd	441	memory-controller@7000f400 {
c04abb3a SW	442	compatible = "nvidia,tegra20-emc";
c04abb3a SW	443	reg = <0x7000f400 0x200>;
2eaab06e SW	444	#address-cells = <1>;
2eaab06e SW	445	#size-cells = <0>;
8e267f3d	446	};
c27317c0 OJ	447
	448	usb@c5000000 {
	449	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	450	reg = <0xc5000000 0x4000>;
95decf84	451	interrupts = <0 20 0x04>;
c27317c0	452	phy_type = "utmi";
ba202f15	453	nvidia,has-legacy-mode;
8d8b43da	454	clocks = <&tegra_car 22>;
b4e07478	455	nvidia,needs-double-reset;
e374b65c	456	nvidia,phy = <&phy1>;
223ef78d	457	status = "disabled";
c27317c0 OJ	458	};
c27317c0 OJ	459
4c94c8b5	460	phy1: usb-phy@c5000000 {
5d324410	461	compatible = "nvidia,tegra20-usb-phy";
4c94c8b5	462	reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
5d324410	463	phy_type = "utmi";
4c94c8b5 VB	464	clocks = <&tegra_car 22>,
	465	<&tegra_car 127>,
	466	<&tegra_car 106>,
	467	<&tegra_car 22>;
	468	clock-names = "reg", "pll_u", "timer", "utmi-pads";
5d324410	469	nvidia,has-legacy-mode;
4c94c8b5 VB	470	hssync_start_delay = <9>;
	471	idle_wait_delay = <17>;
	472	elastic_limit = <16>;
	473	term_range_adj = <6>;
	474	xcvr_setup = <9>;
	475	xcvr_lsfslew = <1>;
	476	xcvr_lsrslew = <1>;
	477	status = "disabled";
5d324410 SW	478	};
5d324410 SW	479
c27317c0 OJ	480	usb@c5004000 {
	481	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	482	reg = <0xc5004000 0x4000>;
95decf84	483	interrupts = <0 21 0x04>;
c27317c0	484	phy_type = "ulpi";
8d8b43da	485	clocks = <&tegra_car 58>;
e374b65c	486	nvidia,phy = <&phy2>;
223ef78d	487	status = "disabled";
c27317c0 OJ	488	};
c27317c0 OJ	489
4c94c8b5	490	phy2: usb-phy@c5004000 {
5d324410	491	compatible = "nvidia,tegra20-usb-phy";
4c94c8b5	492	reg = <0xc5004000 0x4000>;
5d324410	493	phy_type = "ulpi";
4c94c8b5 VB	494	clocks = <&tegra_car 58>,
	495	<&tegra_car 127>,
	496	<&tegra_car 93>;
	497	clock-names = "reg", "pll_u", "ulpi-link";
	498	status = "disabled";
5d324410 SW	499	};
5d324410 SW	500
c27317c0 OJ	501	usb@c5008000 {
	502	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	503	reg = <0xc5008000 0x4000>;
95decf84	504	interrupts = <0 97 0x04>;
c27317c0	505	phy_type = "utmi";
8d8b43da	506	clocks = <&tegra_car 59>;
e374b65c	507	nvidia,phy = <&phy3>;
223ef78d	508	status = "disabled";
c27317c0	509	};
7868a9bc	510
4c94c8b5	511	phy3: usb-phy@c5008000 {
5d324410	512	compatible = "nvidia,tegra20-usb-phy";
4c94c8b5	513	reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
5d324410	514	phy_type = "utmi";
4c94c8b5 VB	515	clocks = <&tegra_car 59>,
	516	<&tegra_car 127>,
	517	<&tegra_car 106>,
	518	<&tegra_car 22>;
	519	clock-names = "reg", "pll_u", "timer", "utmi-pads";
	520	hssync_start_delay = <9>;
	521	idle_wait_delay = <17>;
	522	elastic_limit = <16>;
	523	term_range_adj = <6>;
	524	xcvr_setup = <9>;
	525	xcvr_lsfslew = <2>;
	526	xcvr_lsrslew = <2>;
	527	status = "disabled";
5d324410 SW	528	};
5d324410 SW	529
c04abb3a SW	530	sdhci@c8000000 {
	531	compatible = "nvidia,tegra20-sdhci";
	532	reg = <0xc8000000 0x200>;
	533	interrupts = <0 14 0x04>;
8d8b43da	534	clocks = <&tegra_car 14>;
223ef78d	535	status = "disabled";
7868a9bc	536	};
4a82f2b3	537
c04abb3a SW	538	sdhci@c8000200 {
	539	compatible = "nvidia,tegra20-sdhci";
	540	reg = <0xc8000200 0x200>;
	541	interrupts = <0 15 0x04>;
8d8b43da	542	clocks = <&tegra_car 9>;
223ef78d	543	status = "disabled";
4a82f2b3	544	};
6a943e0e	545
c04abb3a SW	546	sdhci@c8000400 {
	547	compatible = "nvidia,tegra20-sdhci";
	548	reg = <0xc8000400 0x200>;
	549	interrupts = <0 19 0x04>;
8d8b43da	550	clocks = <&tegra_car 69>;
223ef78d	551	status = "disabled";
c04abb3a SW	552	};
	553
	554	sdhci@c8000600 {
	555	compatible = "nvidia,tegra20-sdhci";
	556	reg = <0xc8000600 0x200>;
	557	interrupts = <0 31 0x04>;
8d8b43da	558	clocks = <&tegra_car 15>;
223ef78d	559	status = "disabled";
c04abb3a SW	560	};
c04abb3a SW	561
4dd2bd37 HD	562	cpus {
	563	#address-cells = <1>;
	564	#size-cells = <0>;
	565
	566	cpu@0 {
	567	device_type = "cpu";
	568	compatible = "arm,cortex-a9";
	569	reg = <0>;
	570	};
	571
	572	cpu@1 {
	573	device_type = "cpu";
	574	compatible = "arm,cortex-a9";
	575	reg = <1>;
	576	};
	577	};
	578
c04abb3a SW	579	pmu {
	580	compatible = "arm,cortex-a9-pmu";
	581	interrupts = <0 56 0x04
	582	0 57 0x04>;
6a943e0e	583	};
8e267f3d	584	};