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Merge branch 'for-linus' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jikos...
[linux-2.6-block.git] / arch / arm / boot / dts / tegra20.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
885a8cfa 2#include <dt-bindings/clock/tegra20-car.h>
3325f1bc 3#include <dt-bindings/gpio/tegra-gpio.h>
ba4104e7 4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 5#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 6
1bd0bd49 7#include "skeleton.dtsi"
8e267f3d
GL		 8
9/ {
10 compatible = "nvidia,tegra20";
870c81a4 11 interrupt-parent = <&lic>;
8e267f3d 12
58ecb23f 13 host1x@50000000 {
ed821f07
TR		 14 compatible = "nvidia,tegra20-host1x", "simple-bus";
15 reg = <0x50000000 0x00024000>;
6cecf916
SW		 16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
885a8cfa 18 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
3393d422
SW		 19 resets = <&tegra_car 28>;
20 reset-names = "host1x";
ed821f07
TR		 21
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x54000000 0x54000000 0x04000000>;
26
58ecb23f 27 mpe@54040000 {
ed821f07
TR		 28 compatible = "nvidia,tegra20-mpe";
29 reg = <0x54040000 0x00040000>;
6cecf916 30 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 31 clocks = <&tegra_car TEGRA20_CLK_MPE>;
3393d422
SW		 32 resets = <&tegra_car 60>;
33 reset-names = "mpe";
ed821f07
TR		 34 };
35
58ecb23f 36 vi@54080000 {
ed821f07
TR		 37 compatible = "nvidia,tegra20-vi";
38 reg = <0x54080000 0x00040000>;
6cecf916 39 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 40 clocks = <&tegra_car TEGRA20_CLK_VI>;
3393d422
SW		 41 resets = <&tegra_car 20>;
42 reset-names = "vi";
ed821f07
TR		 43 };
44
58ecb23f 45 epp@540c0000 {
ed821f07
TR		 46 compatible = "nvidia,tegra20-epp";
47 reg = <0x540c0000 0x00040000>;
6cecf916 48 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 49 clocks = <&tegra_car TEGRA20_CLK_EPP>;
3393d422
SW		 50 resets = <&tegra_car 19>;
51 reset-names = "epp";
ed821f07
TR		 52 };
53
58ecb23f 54 isp@54100000 {
ed821f07
TR		 55 compatible = "nvidia,tegra20-isp";
56 reg = <0x54100000 0x00040000>;
6cecf916 57 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 58 clocks = <&tegra_car TEGRA20_CLK_ISP>;
3393d422
SW		 59 resets = <&tegra_car 23>;
60 reset-names = "isp";
ed821f07
TR		 61 };
62
58ecb23f 63 gr2d@54140000 {
ed821f07
TR		 64 compatible = "nvidia,tegra20-gr2d";
65 reg = <0x54140000 0x00040000>;
6cecf916 66 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 67 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
3393d422
SW		 68 resets = <&tegra_car 21>;
69 reset-names = "2d";
ed821f07
TR		 70 };
71
de47699d 72 gr3d@54180000 {
ed821f07 73 compatible = "nvidia,tegra20-gr3d";
de47699d 74 reg = <0x54180000 0x00040000>;
885a8cfa 75 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
3393d422
SW		 76 resets = <&tegra_car 24>;
77 reset-names = "3d";
ed821f07
TR		 78 };
79
80 dc@54200000 {
81 compatible = "nvidia,tegra20-dc";
82 reg = <0x54200000 0x00040000>;
6cecf916 83 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 84 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
85 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 86 clock-names = "dc", "parent";
3393d422
SW		 87 resets = <&tegra_car 27>;
88 reset-names = "dc";
ed821f07 89
688b56b4
TR		 90 nvidia,head = <0>;
91
ed821f07
TR		 92 rgb {
93 status = "disabled";
94 };
95 };
96
97 dc@54240000 {
98 compatible = "nvidia,tegra20-dc";
99 reg = <0x54240000 0x00040000>;
6cecf916 100 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 101 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
102 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 103 clock-names = "dc", "parent";
3393d422
SW		 104 resets = <&tegra_car 26>;
105 reset-names = "dc";
ed821f07 106
688b56b4
TR		 107 nvidia,head = <1>;
108
ed821f07
TR		 109 rgb {
110 status = "disabled";
111 };
112 };
113
58ecb23f 114 hdmi@54280000 {
ed821f07
TR		 115 compatible = "nvidia,tegra20-hdmi";
116 reg = <0x54280000 0x00040000>;
6cecf916 117 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 118 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
119 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
8d8b43da 120 clock-names = "hdmi", "parent";
3393d422
SW		 121 resets = <&tegra_car 51>;
122 reset-names = "hdmi";
ed821f07
TR		 123 status = "disabled";
124 };
125
58ecb23f 126 tvo@542c0000 {
ed821f07
TR		 127 compatible = "nvidia,tegra20-tvo";
128 reg = <0x542c0000 0x00040000>;
6cecf916 129 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 130 clocks = <&tegra_car TEGRA20_CLK_TVO>;
ed821f07
TR		 131 status = "disabled";
132 };
133
de47699d 134 dsi@54300000 {
ed821f07 135 compatible = "nvidia,tegra20-dsi";
de47699d 136 reg = <0x54300000 0x00040000>;
885a8cfa 137 clocks = <&tegra_car TEGRA20_CLK_DSI>;
3393d422
SW		 138 resets = <&tegra_car 48>;
139 reset-names = "dsi";
ed821f07
TR		 140 status = "disabled";
141 };
142 };
143
2cda1880 144 timer@50040600 {
73368ba0 145 compatible = "arm,cortex-a9-twd-timer";
870c81a4 146 interrupt-parent = <&intc>;
73368ba0 147 reg = <0x50040600 0x20>;
6cecf916 148 interrupts = <GIC_PPI 13
e7d9b270 149 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
885a8cfa 150 clocks = <&tegra_car TEGRA20_CLK_TWD>;
73368ba0
SW		 151 };
152
58ecb23f 153 intc: interrupt-controller@50041000 {
0d4f7479 154 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 155 reg = <0x50041000 0x1000
156 0x50040100 0x0100>;
2eaab06e
SW		 157 interrupt-controller;
158 #interrupt-cells = <3>;
870c81a4 159 interrupt-parent = <&intc>;
8e267f3d
GL		 160 };
161
58ecb23f 162 cache-controller@50043000 {
bb2c1de9
SW		 163 compatible = "arm,pl310-cache";
164 reg = <0x50043000 0x1000>;
165 arm,data-latency = <5 5 2>;
166 arm,tag-latency = <4 4 2>;
167 cache-unified;
168 cache-level = <2>;
169 };
170
870c81a4
MZ		 171 lic: interrupt-controller@60004000 {
172 compatible = "nvidia,tegra20-ictlr";
173 reg = <0x60004000 0x100>,
174 <0x60004100 0x50>,
175 <0x60004200 0x50>,
176 <0x60004300 0x50>;
177 interrupt-controller;
178 #interrupt-cells = <3>;
179 interrupt-parent = <&intc>;
180 };
181
2f2b7fb2
SW		 182 timer@60005000 {
183 compatible = "nvidia,tegra20-timer";
184 reg = <0x60005000 0x60>;
6cecf916
SW		 185 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 189 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
2f2b7fb2
SW		 190 };
191
58ecb23f 192 tegra_car: clock@60006000 {
270f8ce3
SW		 193 compatible = "nvidia,tegra20-car";
194 reg = <0x60006000 0x1000>;
195 #clock-cells = <1>;
3393d422 196 #reset-cells = <1>;
270f8ce3
SW		 197 };
198
b1023134
TR		 199 flow-controller@60007000 {
200 compatible = "nvidia,tegra20-flowctrl";
201 reg = <0x60007000 0x1000>;
202 };
203
58ecb23f 204 apbdma: dma@6000a000 {
8051b75a
SW		 205 compatible = "nvidia,tegra20-apbdma";
206 reg = <0x6000a000 0x1200>;
6cecf916
SW		 207 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 223 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
3393d422
SW		 224 resets = <&tegra_car 34>;
225 reset-names = "dma";
034d023f 226 #dma-cells = <1>;
8051b75a
SW		 227 };
228
0d5ccb38 229 ahb@6000c000 {
c04abb3a 230 compatible = "nvidia,tegra20-ahb";
0d5ccb38 231 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
8e267f3d
GL		 232 };
233
58ecb23f 234 gpio: gpio@6000d000 {
8e267f3d 235 compatible = "nvidia,tegra20-gpio";
95decf84 236 reg = <0x6000d000 0x1000>;
6cecf916
SW		 237 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
8e267f3d
GL		 244 #gpio-cells = <2>;
245 gpio-controller;
6f74dc9b
SW		 246 #interrupt-cells = <2>;
247 interrupt-controller;
4f1d8414 248 /*
17cdddf0 249 gpio-ranges = <&pinmux 0 0 224>;
4f1d8414 250 */
8e267f3d
GL		 251 };
252
155dfc7b
PDS		 253 apbmisc@70000800 {
254 compatible = "nvidia,tegra20-apbmisc";
255 reg = <0x70000800 0x64 /* Chip revision */
256 0x70000008 0x04>; /* Strapping options */
257 };
258
58ecb23f 259 pinmux: pinmux@70000014 {
f62f548c 260 compatible = "nvidia,tegra20-pinmux";
95decf84
SW		 261 reg = <0x70000014 0x10 /* Tri-state registers */
262 0x70000080 0x20 /* Mux registers */
263 0x700000a0 0x14 /* Pull-up/down registers */
264 0x70000868 0xa8>; /* Pad control registers */
f62f548c
SW		 265 };
266
58ecb23f 267 das@70000c00 {
c04abb3a
SW		 268 compatible = "nvidia,tegra20-das";
269 reg = <0x70000c00 0x80>;
270 };
fc5c306b 271
58ecb23f 272 tegra_ac97: ac97@70002000 {
0698ed19
LS		 273 compatible = "nvidia,tegra20-ac97";
274 reg = <0x70002000 0x200>;
6cecf916 275 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 276 clocks = <&tegra_car TEGRA20_CLK_AC97>;
3393d422
SW		 277 resets = <&tegra_car 3>;
278 reset-names = "ac97";
034d023f
SW		 279 dmas = <&apbdma 12>, <&apbdma 12>;
280 dma-names = "rx", "tx";
0698ed19
LS		 281 status = "disabled";
282 };
c04abb3a
SW		 283
284 tegra_i2s1: i2s@70002800 {
285 compatible = "nvidia,tegra20-i2s";
286 reg = <0x70002800 0x200>;
6cecf916 287 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 288 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
3393d422
SW		 289 resets = <&tegra_car 11>;
290 reset-names = "i2s";
034d023f
SW		 291 dmas = <&apbdma 2>, <&apbdma 2>;
292 dma-names = "rx", "tx";
223ef78d 293 status = "disabled";
c04abb3a
SW		 294 };
295
296 tegra_i2s2: i2s@70002a00 {
297 compatible = "nvidia,tegra20-i2s";
298 reg = <0x70002a00 0x200>;
6cecf916 299 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 300 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
3393d422
SW		 301 resets = <&tegra_car 18>;
302 reset-names = "i2s";
034d023f
SW		 303 dmas = <&apbdma 1>, <&apbdma 1>;
304 dma-names = "rx", "tx";
223ef78d 305 status = "disabled";
c04abb3a
SW		 306 };
307
b6551bb9
LD		 308 /*
309 * There are two serial driver i.e. 8250 based simple serial
310 * driver and APB DMA based serial driver for higher baudrate
311 * and performace. To enable the 8250 based driver, the compatible
312 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
e1098248 313 * driver, the compatible is "nvidia,tegra20-hsuart".
b6551bb9
LD		 314 */
315 uarta: serial@70006000 {
8e267f3d
GL		 316 compatible = "nvidia,tegra20-uart";
317 reg = <0x70006000 0x40>;
318 reg-shift = <2>;
6cecf916 319 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 320 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
3393d422
SW		 321 resets = <&tegra_car 6>;
322 reset-names = "serial";
034d023f
SW		 323 dmas = <&apbdma 8>, <&apbdma 8>;
324 dma-names = "rx", "tx";
223ef78d 325 status = "disabled";
8e267f3d
GL		 326 };
327
b6551bb9 328 uartb: serial@70006040 {
8e267f3d
GL		 329 compatible = "nvidia,tegra20-uart";
330 reg = <0x70006040 0x40>;
331 reg-shift = <2>;
6cecf916 332 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 333 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
3393d422
SW		 334 resets = <&tegra_car 7>;
335 reset-names = "serial";
034d023f
SW		 336 dmas = <&apbdma 9>, <&apbdma 9>;
337 dma-names = "rx", "tx";
223ef78d 338 status = "disabled";
8e267f3d
GL		 339 };
340
b6551bb9 341 uartc: serial@70006200 {
8e267f3d
GL		 342 compatible = "nvidia,tegra20-uart";
343 reg = <0x70006200 0x100>;
344 reg-shift = <2>;
6cecf916 345 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 346 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
3393d422
SW		 347 resets = <&tegra_car 55>;
348 reset-names = "serial";
034d023f
SW		 349 dmas = <&apbdma 10>, <&apbdma 10>;
350 dma-names = "rx", "tx";
223ef78d 351 status = "disabled";
8e267f3d
GL		 352 };
353
b6551bb9 354 uartd: serial@70006300 {
8e267f3d
GL		 355 compatible = "nvidia,tegra20-uart";
356 reg = <0x70006300 0x100>;
357 reg-shift = <2>;
6cecf916 358 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 359 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
3393d422
SW		 360 resets = <&tegra_car 65>;
361 reset-names = "serial";
034d023f
SW		 362 dmas = <&apbdma 19>, <&apbdma 19>;
363 dma-names = "rx", "tx";
223ef78d 364 status = "disabled";
8e267f3d
GL		 365 };
366
b6551bb9 367 uarte: serial@70006400 {
8e267f3d
GL		 368 compatible = "nvidia,tegra20-uart";
369 reg = <0x70006400 0x100>;
370 reg-shift = <2>;
6cecf916 371 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 372 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
3393d422
SW		 373 resets = <&tegra_car 66>;
374 reset-names = "serial";
034d023f
SW		 375 dmas = <&apbdma 20>, <&apbdma 20>;
376 dma-names = "rx", "tx";
223ef78d 377 status = "disabled";
8e267f3d
GL		 378 };
379
c1700644
MK		 380 gmi@70009000 {
381 compatible = "nvidia,tegra20-gmi";
382 reg = <0x70009000 0x1000>;
383 #address-cells = <2>;
384 #size-cells = <1>;
385 ranges = <0 0 0xd0000000 0xfffffff>;
386 clocks = <&tegra_car TEGRA20_CLK_NOR>;
387 clock-names = "gmi";
388 resets = <&tegra_car 42>;
389 reset-names = "gmi";
390 status = "disabled";
391 };
392
58ecb23f 393 pwm: pwm@7000a000 {
140fd977
TR		 394 compatible = "nvidia,tegra20-pwm";
395 reg = <0x7000a000 0x100>;
396 #pwm-cells = <2>;
885a8cfa 397 clocks = <&tegra_car TEGRA20_CLK_PWM>;
3393d422
SW		 398 resets = <&tegra_car 17>;
399 reset-names = "pwm";
b69cd984 400 status = "disabled";
140fd977
TR		 401 };
402
58ecb23f 403 rtc@7000e000 {
380e04ac
SW		 404 compatible = "nvidia,tegra20-rtc";
405 reg = <0x7000e000 0x100>;
6cecf916 406 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 407 clocks = <&tegra_car TEGRA20_CLK_RTC>;
380e04ac
SW		 408 };
409
c04abb3a 410 i2c@7000c000 {
c04abb3a
SW		 411 compatible = "nvidia,tegra20-i2c";
412 reg = <0x7000c000 0x100>;
6cecf916 413 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 414 #address-cells = <1>;
415 #size-cells = <0>;
885a8cfa
HD		 416 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
417 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 418 clock-names = "div-clk", "fast-clk";
3393d422
SW		 419 resets = <&tegra_car 12>;
420 reset-names = "i2c";
034d023f
SW		 421 dmas = <&apbdma 21>, <&apbdma 21>;
422 dma-names = "rx", "tx";
223ef78d 423 status = "disabled";
0c6700ab
OJ		 424 };
425
fa98a114
LD		 426 spi@7000c380 {
427 compatible = "nvidia,tegra20-sflash";
428 reg = <0x7000c380 0x80>;
6cecf916 429 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
fa98a114
LD		 430 #address-cells = <1>;
431 #size-cells = <0>;
885a8cfa 432 clocks = <&tegra_car TEGRA20_CLK_SPI>;
3393d422
SW		 433 resets = <&tegra_car 43>;
434 reset-names = "spi";
034d023f
SW		 435 dmas = <&apbdma 11>, <&apbdma 11>;
436 dma-names = "rx", "tx";
fa98a114
LD		 437 status = "disabled";
438 };
439
c04abb3a 440 i2c@7000c400 {
c04abb3a
SW		 441 compatible = "nvidia,tegra20-i2c";
442 reg = <0x7000c400 0x100>;
6cecf916 443 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 444 #address-cells = <1>;
445 #size-cells = <0>;
885a8cfa
HD		 446 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
447 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 448 clock-names = "div-clk", "fast-clk";
3393d422
SW		 449 resets = <&tegra_car 54>;
450 reset-names = "i2c";
034d023f
SW		 451 dmas = <&apbdma 22>, <&apbdma 22>;
452 dma-names = "rx", "tx";
223ef78d 453 status = "disabled";
8e267f3d
GL		 454 };
455
c04abb3a 456 i2c@7000c500 {
c04abb3a
SW		 457 compatible = "nvidia,tegra20-i2c";
458 reg = <0x7000c500 0x100>;
6cecf916 459 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 460 #address-cells = <1>;
461 #size-cells = <0>;
885a8cfa
HD		 462 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
463 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 464 clock-names = "div-clk", "fast-clk";
3393d422
SW		 465 resets = <&tegra_car 67>;
466 reset-names = "i2c";
034d023f
SW		 467 dmas = <&apbdma 23>, <&apbdma 23>;
468 dma-names = "rx", "tx";
223ef78d 469 status = "disabled";
8e267f3d
GL		 470 };
471
c04abb3a 472 i2c@7000d000 {
c04abb3a
SW		 473 compatible = "nvidia,tegra20-i2c-dvc";
474 reg = <0x7000d000 0x200>;
6cecf916 475 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 476 #address-cells = <1>;
477 #size-cells = <0>;
885a8cfa
HD		 478 clocks = <&tegra_car TEGRA20_CLK_DVC>,
479 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 480 clock-names = "div-clk", "fast-clk";
3393d422
SW		 481 resets = <&tegra_car 47>;
482 reset-names = "i2c";
034d023f
SW		 483 dmas = <&apbdma 24>, <&apbdma 24>;
484 dma-names = "rx", "tx";
223ef78d 485 status = "disabled";
8e267f3d
GL		 486 };
487
a86b0db3
LD		 488 spi@7000d400 {
489 compatible = "nvidia,tegra20-slink";
490 reg = <0x7000d400 0x200>;
6cecf916 491 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 492 #address-cells = <1>;
493 #size-cells = <0>;
885a8cfa 494 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
3393d422
SW		 495 resets = <&tegra_car 41>;
496 reset-names = "spi";
034d023f
SW		 497 dmas = <&apbdma 15>, <&apbdma 15>;
498 dma-names = "rx", "tx";
a86b0db3
LD		 499 status = "disabled";
500 };
501
502 spi@7000d600 {
503 compatible = "nvidia,tegra20-slink";
504 reg = <0x7000d600 0x200>;
6cecf916 505 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 506 #address-cells = <1>;
507 #size-cells = <0>;
885a8cfa 508 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
3393d422
SW		 509 resets = <&tegra_car 44>;
510 reset-names = "spi";
034d023f
SW		 511 dmas = <&apbdma 16>, <&apbdma 16>;
512 dma-names = "rx", "tx";
a86b0db3
LD		 513 status = "disabled";
514 };
515
516 spi@7000d800 {
517 compatible = "nvidia,tegra20-slink";
57471c8d 518 reg = <0x7000d800 0x200>;
6cecf916 519 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 520 #address-cells = <1>;
521 #size-cells = <0>;
885a8cfa 522 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
3393d422
SW		 523 resets = <&tegra_car 46>;
524 reset-names = "spi";
034d023f
SW		 525 dmas = <&apbdma 17>, <&apbdma 17>;
526 dma-names = "rx", "tx";
a86b0db3
LD		 527 status = "disabled";
528 };
529
530 spi@7000da00 {
531 compatible = "nvidia,tegra20-slink";
532 reg = <0x7000da00 0x200>;
6cecf916 533 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 534 #address-cells = <1>;
535 #size-cells = <0>;
885a8cfa 536 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
3393d422
SW		 537 resets = <&tegra_car 68>;
538 reset-names = "spi";
034d023f
SW		 539 dmas = <&apbdma 18>, <&apbdma 18>;
540 dma-names = "rx", "tx";
a86b0db3
LD		 541 status = "disabled";
542 };
543
58ecb23f 544 kbc@7000e200 {
699ed4b9
LD		 545 compatible = "nvidia,tegra20-kbc";
546 reg = <0x7000e200 0x100>;
6cecf916 547 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 548 clocks = <&tegra_car TEGRA20_CLK_KBC>;
3393d422
SW		 549 resets = <&tegra_car 36>;
550 reset-names = "kbc";
699ed4b9
LD		 551 status = "disabled";
552 };
553
58ecb23f 554 pmc@7000e400 {
c04abb3a
SW		 555 compatible = "nvidia,tegra20-pmc";
556 reg = <0x7000e400 0x400>;
885a8cfa 557 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
7021d122 558 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 559 };
560
bbfc33bd 561 memory-controller@7000f000 {
c04abb3a
SW		 562 compatible = "nvidia,tegra20-mc";
563 reg = <0x7000f000 0x024
564 0x7000f03c 0x3c4>;
6cecf916 565 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a
SW		 566 };
567
58ecb23f 568 iommu@7000f024 {
c04abb3a
SW		 569 compatible = "nvidia,tegra20-gart";
570 reg = <0x7000f024 0x00000018 /* controller registers */
571 0x58000000 0x02000000>; /* GART aperture */
572 };
573
bbfc33bd 574 memory-controller@7000f400 {
c04abb3a
SW		 575 compatible = "nvidia,tegra20-emc";
576 reg = <0x7000f400 0x200>;
2eaab06e
SW		 577 #address-cells = <1>;
578 #size-cells = <0>;
8e267f3d 579 };
c27317c0 580
155dfc7b
PDS		 581 fuse@7000f800 {
582 compatible = "nvidia,tegra20-efuse";
5431b0fd 583 reg = <0x7000f800 0x400>;
155dfc7b
PDS		 584 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
585 clock-names = "fuse";
586 resets = <&tegra_car 39>;
587 reset-names = "fuse";
588 };
589
508d690e 590 pcie@80003000 {
1b62b611
TR		 591 compatible = "nvidia,tegra20-pcie";
592 device_type = "pci";
593 reg = <0x80003000 0x00000800 /* PADS registers */
594 0x80003800 0x00000200 /* AFI registers */
595 0x90000000 0x10000000>; /* configuration space */
596 reg-names = "pads", "afi", "cs";
597 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
598 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
599 interrupt-names = "intr", "msi";
600
97070bd4
LS		 601 #interrupt-cells = <1>;
602 interrupt-map-mask = <0 0 0 0>;
603 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
604
1b62b611
TR		 605 bus-range = <0x00 0xff>;
606 #address-cells = <3>;
607 #size-cells = <2>;
608
609 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
610 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
611 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 612 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
613 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
1b62b611
TR		 614
615 clocks = <&tegra_car TEGRA20_CLK_PEX>,
616 <&tegra_car TEGRA20_CLK_AFI>,
1b62b611 617 <&tegra_car TEGRA20_CLK_PLL_E>;
2bd541ff 618 clock-names = "pex", "afi", "pll_e";
3393d422 619 resets = <&tegra_car 70>,
d8b316b2
MZ		 620 <&tegra_car 72>,
621 <&tegra_car 74>;
3393d422 622 reset-names = "pex", "afi", "pcie_x";
1b62b611
TR		 623 status = "disabled";
624
625 pci@1,0 {
626 device_type = "pci";
627 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
628 reg = <0x000800 0 0 0 0>;
508d690e 629 bus-range = <0x00 0xff>;
1b62b611
TR		 630 status = "disabled";
631
632 #address-cells = <3>;
633 #size-cells = <2>;
634 ranges;
635
636 nvidia,num-lanes = <2>;
637 };
638
639 pci@2,0 {
640 device_type = "pci";
641 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
642 reg = <0x001000 0 0 0 0>;
508d690e 643 bus-range = <0x00 0xff>;
1b62b611
TR		 644 status = "disabled";
645
646 #address-cells = <3>;
647 #size-cells = <2>;
648 ranges;
649
650 nvidia,num-lanes = <2>;
651 };
652 };
653
c27317c0
OJ		 654 usb@c5000000 {
655 compatible = "nvidia,tegra20-ehci", "usb-ehci";
656 reg = <0xc5000000 0x4000>;
6cecf916 657 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 658 phy_type = "utmi";
ba202f15 659 nvidia,has-legacy-mode;
885a8cfa 660 clocks = <&tegra_car TEGRA20_CLK_USBD>;
3393d422
SW		 661 resets = <&tegra_car 22>;
662 reset-names = "usb";
b4e07478 663 nvidia,needs-double-reset;
e374b65c 664 nvidia,phy = <&phy1>;
223ef78d 665 status = "disabled";
c27317c0
OJ		 666 };
667
4c94c8b5 668 phy1: usb-phy@c5000000 {
5d324410 669 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 670 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
5d324410 671 phy_type = "utmi";
885a8cfa
HD		 672 clocks = <&tegra_car TEGRA20_CLK_USBD>,
673 <&tegra_car TEGRA20_CLK_PLL_U>,
674 <&tegra_car TEGRA20_CLK_CLK_M>,
675 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 676 clock-names = "reg", "pll_u", "timer", "utmi-pads";
308efde2
TT		 677 resets = <&tegra_car 22>, <&tegra_car 22>;
678 reset-names = "usb", "utmi-pads";
5d324410 679 nvidia,has-legacy-mode;
c49667e5
MP		 680 nvidia,hssync-start-delay = <9>;
681 nvidia,idle-wait-delay = <17>;
682 nvidia,elastic-limit = <16>;
683 nvidia,term-range-adj = <6>;
684 nvidia,xcvr-setup = <9>;
685 nvidia,xcvr-lsfslew = <1>;
686 nvidia,xcvr-lsrslew = <1>;
308efde2 687 nvidia,has-utmi-pad-registers;
4c94c8b5 688 status = "disabled";
5d324410
SW		 689 };
690
c27317c0
OJ		 691 usb@c5004000 {
692 compatible = "nvidia,tegra20-ehci", "usb-ehci";
693 reg = <0xc5004000 0x4000>;
6cecf916 694 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 695 phy_type = "ulpi";
885a8cfa 696 clocks = <&tegra_car TEGRA20_CLK_USB2>;
3393d422
SW		 697 resets = <&tegra_car 58>;
698 reset-names = "usb";
e374b65c 699 nvidia,phy = <&phy2>;
223ef78d 700 status = "disabled";
c27317c0
OJ		 701 };
702
4c94c8b5 703 phy2: usb-phy@c5004000 {
5d324410 704 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 705 reg = <0xc5004000 0x4000>;
5d324410 706 phy_type = "ulpi";
885a8cfa
HD		 707 clocks = <&tegra_car TEGRA20_CLK_USB2>,
708 <&tegra_car TEGRA20_CLK_PLL_U>,
709 <&tegra_car TEGRA20_CLK_CDEV2>;
4c94c8b5 710 clock-names = "reg", "pll_u", "ulpi-link";
308efde2
TT		 711 resets = <&tegra_car 58>, <&tegra_car 22>;
712 reset-names = "usb", "utmi-pads";
4c94c8b5 713 status = "disabled";
5d324410
SW		 714 };
715
c27317c0
OJ		 716 usb@c5008000 {
717 compatible = "nvidia,tegra20-ehci", "usb-ehci";
718 reg = <0xc5008000 0x4000>;
6cecf916 719 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 720 phy_type = "utmi";
885a8cfa 721 clocks = <&tegra_car TEGRA20_CLK_USB3>;
3393d422
SW		 722 resets = <&tegra_car 59>;
723 reset-names = "usb";
e374b65c 724 nvidia,phy = <&phy3>;
223ef78d 725 status = "disabled";
c27317c0 726 };
7868a9bc 727
4c94c8b5 728 phy3: usb-phy@c5008000 {
5d324410 729 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 730 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
5d324410 731 phy_type = "utmi";
885a8cfa
HD		 732 clocks = <&tegra_car TEGRA20_CLK_USB3>,
733 <&tegra_car TEGRA20_CLK_PLL_U>,
734 <&tegra_car TEGRA20_CLK_CLK_M>,
735 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 736 clock-names = "reg", "pll_u", "timer", "utmi-pads";
308efde2
TT		 737 resets = <&tegra_car 59>, <&tegra_car 22>;
738 reset-names = "usb", "utmi-pads";
c49667e5
MP		 739 nvidia,hssync-start-delay = <9>;
740 nvidia,idle-wait-delay = <17>;
741 nvidia,elastic-limit = <16>;
742 nvidia,term-range-adj = <6>;
743 nvidia,xcvr-setup = <9>;
744 nvidia,xcvr-lsfslew = <2>;
745 nvidia,xcvr-lsrslew = <2>;
4c94c8b5 746 status = "disabled";
5d324410
SW		 747 };
748
c04abb3a
SW		 749 sdhci@c8000000 {
750 compatible = "nvidia,tegra20-sdhci";
751 reg = <0xc8000000 0x200>;
6cecf916 752 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 753 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
3393d422
SW		 754 resets = <&tegra_car 14>;
755 reset-names = "sdhci";
223ef78d 756 status = "disabled";
7868a9bc 757 };
4a82f2b3 758
c04abb3a
SW		 759 sdhci@c8000200 {
760 compatible = "nvidia,tegra20-sdhci";
761 reg = <0xc8000200 0x200>;
6cecf916 762 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 763 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
3393d422
SW		 764 resets = <&tegra_car 9>;
765 reset-names = "sdhci";
223ef78d 766 status = "disabled";
4a82f2b3 767 };
6a943e0e 768
c04abb3a
SW		 769 sdhci@c8000400 {
770 compatible = "nvidia,tegra20-sdhci";
771 reg = <0xc8000400 0x200>;
6cecf916 772 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 773 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
3393d422
SW		 774 resets = <&tegra_car 69>;
775 reset-names = "sdhci";
223ef78d 776 status = "disabled";
c04abb3a
SW		 777 };
778
779 sdhci@c8000600 {
780 compatible = "nvidia,tegra20-sdhci";
781 reg = <0xc8000600 0x200>;
6cecf916 782 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 783 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
3393d422
SW		 784 resets = <&tegra_car 15>;
785 reset-names = "sdhci";
223ef78d 786 status = "disabled";
c04abb3a
SW		 787 };
788
4dd2bd37
HD		 789 cpus {
790 #address-cells = <1>;
791 #size-cells = <0>;
792
793 cpu@0 {
794 device_type = "cpu";
795 compatible = "arm,cortex-a9";
796 reg = <0>;
797 };
798
799 cpu@1 {
800 device_type = "cpu";
801 compatible = "arm,cortex-a9";
802 reg = <1>;
803 };
804 };
805
c04abb3a
SW		 806 pmu {
807 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 808 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6a943e0e 810 };
8e267f3d 811};
Linux 6.x block layer and io_uring tree(s)