Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
8e267f3d GL |
2 | /dts-v1/; |
3 | ||
6bccbd5e | 4 | #include <dt-bindings/input/input.h> |
1bd0bd49 | 5 | #include "tegra20.dtsi" |
8e267f3d GL |
6 | |
7 | / { | |
8 | model = "NVIDIA Seaboard"; | |
9 | compatible = "nvidia,seaboard", "nvidia,tegra20"; | |
10 | ||
553c0a20 SW |
11 | aliases { |
12 | rtc0 = "/i2c@7000d000/tps6586x@34"; | |
13 | rtc1 = "/rtc@7000e000"; | |
c4574aa0 | 14 | serial0 = &uartd; |
553c0a20 SW |
15 | }; |
16 | ||
f5bbb327 JH |
17 | chosen { |
18 | stdout-path = "serial0:115200n8"; | |
19 | }; | |
20 | ||
8e267f3d | 21 | memory { |
95decf84 | 22 | reg = <0x00000000 0x40000000>; |
8e267f3d GL |
23 | }; |
24 | ||
58ecb23f | 25 | host1x@50000000 { |
9615d656 SW |
26 | dc@54200000 { |
27 | rgb { | |
28 | status = "okay"; | |
29 | ||
30 | nvidia,panel = <&panel>; | |
31 | }; | |
32 | }; | |
33 | ||
58ecb23f | 34 | hdmi@54280000 { |
a75191e6 SW |
35 | status = "okay"; |
36 | ||
37 | vdd-supply = <&hdmi_vdd_reg>; | |
38 | pll-supply = <&hdmi_pll_reg>; | |
5264d274 | 39 | hdmi-supply = <&vdd_hdmi>; |
a75191e6 SW |
40 | |
41 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
3325f1bc SW |
42 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
43 | GPIO_ACTIVE_HIGH>; | |
a75191e6 SW |
44 | }; |
45 | }; | |
46 | ||
58ecb23f | 47 | pinmux@70000014 { |
ecc295bb SW |
48 | pinctrl-names = "default"; |
49 | pinctrl-0 = <&state_default>; | |
50 | ||
51 | state_default: pinmux { | |
52 | ata { | |
53 | nvidia,pins = "ata"; | |
54 | nvidia,function = "ide"; | |
55 | }; | |
56 | atb { | |
57 | nvidia,pins = "atb", "gma", "gme"; | |
58 | nvidia,function = "sdio4"; | |
59 | }; | |
60 | atc { | |
61 | nvidia,pins = "atc"; | |
62 | nvidia,function = "nand"; | |
63 | }; | |
64 | atd { | |
65 | nvidia,pins = "atd", "ate", "gmb", "spia", | |
66 | "spib", "spic"; | |
67 | nvidia,function = "gmi"; | |
68 | }; | |
69 | cdev1 { | |
70 | nvidia,pins = "cdev1"; | |
71 | nvidia,function = "plla_out"; | |
72 | }; | |
73 | cdev2 { | |
74 | nvidia,pins = "cdev2"; | |
75 | nvidia,function = "pllp_out4"; | |
76 | }; | |
77 | crtp { | |
78 | nvidia,pins = "crtp", "lm1"; | |
79 | nvidia,function = "crt"; | |
80 | }; | |
81 | csus { | |
82 | nvidia,pins = "csus"; | |
83 | nvidia,function = "vi_sensor_clk"; | |
84 | }; | |
85 | dap1 { | |
86 | nvidia,pins = "dap1"; | |
87 | nvidia,function = "dap1"; | |
88 | }; | |
89 | dap2 { | |
90 | nvidia,pins = "dap2"; | |
91 | nvidia,function = "dap2"; | |
92 | }; | |
93 | dap3 { | |
94 | nvidia,pins = "dap3"; | |
95 | nvidia,function = "dap3"; | |
96 | }; | |
97 | dap4 { | |
98 | nvidia,pins = "dap4"; | |
99 | nvidia,function = "dap4"; | |
100 | }; | |
ecc295bb SW |
101 | dta { |
102 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; | |
103 | nvidia,function = "vi"; | |
104 | }; | |
105 | dtf { | |
106 | nvidia,pins = "dtf"; | |
107 | nvidia,function = "i2c3"; | |
108 | }; | |
109 | gmc { | |
110 | nvidia,pins = "gmc"; | |
111 | nvidia,function = "uartd"; | |
112 | }; | |
113 | gmd { | |
114 | nvidia,pins = "gmd"; | |
115 | nvidia,function = "sflash"; | |
116 | }; | |
117 | gpu { | |
118 | nvidia,pins = "gpu"; | |
119 | nvidia,function = "pwm"; | |
120 | }; | |
121 | gpu7 { | |
122 | nvidia,pins = "gpu7"; | |
123 | nvidia,function = "rtck"; | |
124 | }; | |
125 | gpv { | |
126 | nvidia,pins = "gpv", "slxa", "slxk"; | |
127 | nvidia,function = "pcie"; | |
128 | }; | |
129 | hdint { | |
130 | nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", | |
802a8499 | 131 | "lsck", "lsda"; |
ecc295bb SW |
132 | nvidia,function = "hdmi"; |
133 | }; | |
134 | i2cp { | |
135 | nvidia,pins = "i2cp"; | |
136 | nvidia,function = "i2cp"; | |
137 | }; | |
138 | irrx { | |
139 | nvidia,pins = "irrx", "irtx"; | |
140 | nvidia,function = "uartb"; | |
141 | }; | |
142 | kbca { | |
143 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
144 | "kbce", "kbcf"; | |
145 | nvidia,function = "kbc"; | |
146 | }; | |
147 | lcsn { | |
148 | nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", | |
149 | "lsdi", "lvp0"; | |
150 | nvidia,function = "rsvd4"; | |
151 | }; | |
152 | ld0 { | |
153 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
154 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
155 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
156 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
157 | "lhp1", "lhp2", "lhs", "lpp", "lsc0", | |
158 | "lspi", "lvp1", "lvs"; | |
159 | nvidia,function = "displaya"; | |
160 | }; | |
a18cf6dc SW |
161 | owc { |
162 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | |
163 | nvidia,function = "rsvd2"; | |
164 | }; | |
ecc295bb SW |
165 | pmc { |
166 | nvidia,pins = "pmc"; | |
167 | nvidia,function = "pwr_on"; | |
168 | }; | |
169 | rm { | |
170 | nvidia,pins = "rm"; | |
171 | nvidia,function = "i2c1"; | |
172 | }; | |
173 | sdb { | |
174 | nvidia,pins = "sdb", "sdc", "sdd"; | |
175 | nvidia,function = "sdio3"; | |
176 | }; | |
177 | sdio1 { | |
178 | nvidia,pins = "sdio1"; | |
179 | nvidia,function = "sdio1"; | |
180 | }; | |
181 | slxc { | |
182 | nvidia,pins = "slxc", "slxd"; | |
183 | nvidia,function = "spdif"; | |
184 | }; | |
185 | spid { | |
186 | nvidia,pins = "spid", "spie", "spif"; | |
187 | nvidia,function = "spi1"; | |
188 | }; | |
189 | spig { | |
190 | nvidia,pins = "spig", "spih"; | |
191 | nvidia,function = "spi2_alt"; | |
192 | }; | |
193 | uaa { | |
194 | nvidia,pins = "uaa", "uab", "uda"; | |
195 | nvidia,function = "ulpi"; | |
196 | }; | |
197 | uad { | |
198 | nvidia,pins = "uad"; | |
199 | nvidia,function = "irda"; | |
200 | }; | |
201 | uca { | |
202 | nvidia,pins = "uca", "ucb"; | |
203 | nvidia,function = "uartc"; | |
204 | }; | |
205 | conf_ata { | |
206 | nvidia,pins = "ata", "atb", "atc", "atd", | |
207 | "cdev1", "cdev2", "dap1", "dap2", | |
a18cf6dc | 208 | "dap4", "ddc", "dtf", "gma", "gmc", "gmd", |
ecc295bb SW |
209 | "gme", "gpu", "gpu7", "i2cp", "irrx", |
210 | "irtx", "pta", "rm", "sdc", "sdd", | |
211 | "slxd", "slxk", "spdi", "spdo", "uac", | |
212 | "uad", "uca", "ucb", "uda"; | |
ba4104e7 LD |
213 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
214 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
215 | }; |
216 | conf_ate { | |
a18cf6dc | 217 | nvidia,pins = "ate", "csus", "dap3", |
ecc295bb SW |
218 | "gpv", "owc", "slxc", "spib", "spid", |
219 | "spie"; | |
ba4104e7 LD |
220 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
221 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
222 | }; |
223 | conf_ck32 { | |
224 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
225 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
ba4104e7 | 226 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
ecc295bb SW |
227 | }; |
228 | conf_crtp { | |
229 | nvidia,pins = "crtp", "gmb", "slxa", "spia", | |
230 | "spig", "spih"; | |
ba4104e7 LD |
231 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
232 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
233 | }; |
234 | conf_dta { | |
235 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; | |
ba4104e7 LD |
236 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
237 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
238 | }; |
239 | conf_dte { | |
240 | nvidia,pins = "dte", "spif"; | |
ba4104e7 LD |
241 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
242 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
243 | }; |
244 | conf_hdint { | |
245 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | |
246 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", | |
247 | "lvp0"; | |
ba4104e7 | 248 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
ecc295bb SW |
249 | }; |
250 | conf_kbca { | |
251 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
252 | "kbce", "kbcf", "sdio1", "spic", "uaa", | |
253 | "uab"; | |
ba4104e7 LD |
254 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
255 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
256 | }; |
257 | conf_lc { | |
258 | nvidia,pins = "lc", "ls"; | |
ba4104e7 | 259 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
ecc295bb SW |
260 | }; |
261 | conf_ld0 { | |
262 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
263 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
264 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
265 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
266 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | |
267 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", | |
268 | "lvs", "pmc", "sdb"; | |
ba4104e7 | 269 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
ecc295bb SW |
270 | }; |
271 | conf_ld17_0 { | |
272 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
273 | "ld23_22"; | |
ba4104e7 | 274 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
ecc295bb SW |
275 | }; |
276 | drive_sdio1 { | |
277 | nvidia,pins = "drive_sdio1"; | |
ba4104e7 LD |
278 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
279 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
280 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
ecc295bb SW |
281 | nvidia,pull-down-strength = <31>; |
282 | nvidia,pull-up-strength = <31>; | |
ba4104e7 LD |
283 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
284 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; | |
ecc295bb SW |
285 | }; |
286 | }; | |
a18cf6dc SW |
287 | |
288 | state_i2cmux_ddc: pinmux_i2cmux_ddc { | |
289 | ddc { | |
290 | nvidia,pins = "ddc"; | |
291 | nvidia,function = "i2c2"; | |
292 | }; | |
293 | pta { | |
294 | nvidia,pins = "pta"; | |
295 | nvidia,function = "rsvd4"; | |
296 | }; | |
297 | }; | |
298 | ||
299 | state_i2cmux_pta: pinmux_i2cmux_pta { | |
300 | ddc { | |
301 | nvidia,pins = "ddc"; | |
302 | nvidia,function = "rsvd4"; | |
303 | }; | |
304 | pta { | |
305 | nvidia,pins = "pta"; | |
306 | nvidia,function = "i2c2"; | |
307 | }; | |
308 | }; | |
309 | ||
310 | state_i2cmux_idle: pinmux_i2cmux_idle { | |
311 | ddc { | |
312 | nvidia,pins = "ddc"; | |
313 | nvidia,function = "rsvd4"; | |
314 | }; | |
315 | pta { | |
316 | nvidia,pins = "pta"; | |
317 | nvidia,function = "rsvd4"; | |
318 | }; | |
319 | }; | |
ecc295bb SW |
320 | }; |
321 | ||
2a5fdc9a SW |
322 | i2s@70002800 { |
323 | status = "okay"; | |
c04abb3a SW |
324 | }; |
325 | ||
326 | serial@70006300 { | |
2a5fdc9a | 327 | status = "okay"; |
c04abb3a SW |
328 | }; |
329 | ||
9615d656 SW |
330 | pwm: pwm@7000a000 { |
331 | status = "okay"; | |
332 | }; | |
333 | ||
88950f3b | 334 | i2c@7000c000 { |
2a5fdc9a | 335 | status = "okay"; |
88950f3b | 336 | clock-frequency = <400000>; |
797acf70 SW |
337 | |
338 | wm8903: wm8903@1a { | |
339 | compatible = "wlf,wm8903"; | |
340 | reg = <0x1a>; | |
341 | interrupt-parent = <&gpio>; | |
6cecf916 | 342 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
797acf70 SW |
343 | |
344 | gpio-controller; | |
345 | #gpio-cells = <2>; | |
346 | ||
347 | micdet-cfg = <0>; | |
348 | micdet-delay = <100>; | |
95decf84 | 349 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
797acf70 | 350 | }; |
b46b0b54 LD |
351 | |
352 | /* ALS and proximity sensor */ | |
353 | isl29018@44 { | |
354 | compatible = "isil,isl29018"; | |
355 | reg = <0x44>; | |
356 | interrupt-parent = <&gpio>; | |
6cecf916 | 357 | interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; |
b46b0b54 | 358 | }; |
45dbe9dd OJ |
359 | |
360 | gyrometer@68 { | |
361 | compatible = "invn,mpu3050"; | |
362 | reg = <0x68>; | |
363 | interrupt-parent = <&gpio>; | |
6cecf916 | 364 | interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>; |
45dbe9dd | 365 | }; |
88950f3b SW |
366 | }; |
367 | ||
368 | i2c@7000c400 { | |
2a5fdc9a | 369 | status = "okay"; |
22bd1f7e | 370 | clock-frequency = <100000>; |
88950f3b SW |
371 | }; |
372 | ||
a18cf6dc SW |
373 | i2cmux { |
374 | compatible = "i2c-mux-pinctrl"; | |
375 | #address-cells = <1>; | |
376 | #size-cells = <0>; | |
377 | ||
378 | i2c-parent = <&{/i2c@7000c400}>; | |
379 | ||
380 | pinctrl-names = "ddc", "pta", "idle"; | |
381 | pinctrl-0 = <&state_i2cmux_ddc>; | |
382 | pinctrl-1 = <&state_i2cmux_pta>; | |
383 | pinctrl-2 = <&state_i2cmux_idle>; | |
384 | ||
a75191e6 | 385 | hdmi_ddc: i2c@0 { |
a18cf6dc SW |
386 | reg = <0>; |
387 | #address-cells = <1>; | |
388 | #size-cells = <0>; | |
389 | }; | |
390 | ||
9615d656 | 391 | lvds_ddc: i2c@1 { |
a18cf6dc SW |
392 | reg = <1>; |
393 | #address-cells = <1>; | |
394 | #size-cells = <0>; | |
0879c5f7 SW |
395 | |
396 | smart-battery@b { | |
397 | compatible = "ti,bq20z75", "smart-battery-1.1"; | |
398 | reg = <0xb>; | |
399 | ti,i2c-retry-count = <2>; | |
400 | ti,poll-retry-count = <10>; | |
401 | }; | |
a18cf6dc SW |
402 | }; |
403 | }; | |
404 | ||
88950f3b | 405 | i2c@7000c500 { |
2a5fdc9a | 406 | status = "okay"; |
88950f3b SW |
407 | clock-frequency = <400000>; |
408 | }; | |
409 | ||
410 | i2c@7000d000 { | |
2a5fdc9a | 411 | status = "okay"; |
88950f3b | 412 | clock-frequency = <400000>; |
401c9a50 | 413 | |
57899053 | 414 | magnetometer@c { |
7c7a9b3d | 415 | compatible = "asahi-kasei,ak8975"; |
57899053 SW |
416 | reg = <0xc>; |
417 | interrupt-parent = <&gpio>; | |
418 | interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; | |
419 | }; | |
420 | ||
6529e638 SW |
421 | pmic: tps6586x@34 { |
422 | compatible = "ti,tps6586x"; | |
423 | reg = <0x34>; | |
6cecf916 | 424 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
6529e638 | 425 | |
44b12ef7 SW |
426 | ti,system-power-controller; |
427 | ||
6529e638 SW |
428 | #gpio-cells = <2>; |
429 | gpio-controller; | |
430 | ||
431 | sys-supply = <&vdd_5v0_reg>; | |
432 | vin-sm0-supply = <&sys_reg>; | |
433 | vin-sm1-supply = <&sys_reg>; | |
434 | vin-sm2-supply = <&sys_reg>; | |
435 | vinldo01-supply = <&sm2_reg>; | |
436 | vinldo23-supply = <&sm2_reg>; | |
437 | vinldo4-supply = <&sm2_reg>; | |
438 | vinldo678-supply = <&sm2_reg>; | |
439 | vinldo9-supply = <&sm2_reg>; | |
440 | ||
441 | regulators { | |
b9c665d7 | 442 | sys_reg: sys { |
6529e638 SW |
443 | regulator-name = "vdd_sys"; |
444 | regulator-always-on; | |
445 | }; | |
446 | ||
b9c665d7 | 447 | sm0 { |
6529e638 SW |
448 | regulator-name = "vdd_sm0,vdd_core"; |
449 | regulator-min-microvolt = <1300000>; | |
450 | regulator-max-microvolt = <1300000>; | |
451 | regulator-always-on; | |
452 | }; | |
453 | ||
b9c665d7 | 454 | sm1 { |
6529e638 SW |
455 | regulator-name = "vdd_sm1,vdd_cpu"; |
456 | regulator-min-microvolt = <1125000>; | |
457 | regulator-max-microvolt = <1125000>; | |
458 | regulator-always-on; | |
459 | }; | |
460 | ||
b9c665d7 | 461 | sm2_reg: sm2 { |
6529e638 SW |
462 | regulator-name = "vdd_sm2,vin_ldo*"; |
463 | regulator-min-microvolt = <3700000>; | |
464 | regulator-max-microvolt = <3700000>; | |
465 | regulator-always-on; | |
466 | }; | |
467 | ||
468 | /* LDO0 is not connected to anything */ | |
469 | ||
b9c665d7 | 470 | ldo1 { |
6529e638 SW |
471 | regulator-name = "vdd_ldo1,avdd_pll*"; |
472 | regulator-min-microvolt = <1100000>; | |
473 | regulator-max-microvolt = <1100000>; | |
474 | regulator-always-on; | |
475 | }; | |
476 | ||
b9c665d7 | 477 | ldo2 { |
6529e638 SW |
478 | regulator-name = "vdd_ldo2,vdd_rtc"; |
479 | regulator-min-microvolt = <1200000>; | |
480 | regulator-max-microvolt = <1200000>; | |
481 | }; | |
482 | ||
b9c665d7 | 483 | ldo3 { |
6529e638 SW |
484 | regulator-name = "vdd_ldo3,avdd_usb*"; |
485 | regulator-min-microvolt = <3300000>; | |
486 | regulator-max-microvolt = <3300000>; | |
487 | regulator-always-on; | |
488 | }; | |
489 | ||
b9c665d7 | 490 | ldo4 { |
6529e638 SW |
491 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
492 | regulator-min-microvolt = <1800000>; | |
493 | regulator-max-microvolt = <1800000>; | |
494 | regulator-always-on; | |
495 | }; | |
496 | ||
b9c665d7 | 497 | ldo5 { |
6529e638 SW |
498 | regulator-name = "vdd_ldo5,vcore_mmc"; |
499 | regulator-min-microvolt = <2850000>; | |
500 | regulator-max-microvolt = <2850000>; | |
501 | regulator-always-on; | |
502 | }; | |
503 | ||
b9c665d7 | 504 | ldo6 { |
6529e638 SW |
505 | regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; |
506 | regulator-min-microvolt = <1800000>; | |
507 | regulator-max-microvolt = <1800000>; | |
508 | }; | |
509 | ||
a75191e6 | 510 | hdmi_vdd_reg: ldo7 { |
6529e638 SW |
511 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; |
512 | regulator-min-microvolt = <3300000>; | |
513 | regulator-max-microvolt = <3300000>; | |
514 | }; | |
515 | ||
a75191e6 | 516 | hdmi_pll_reg: ldo8 { |
6529e638 SW |
517 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
518 | regulator-min-microvolt = <1800000>; | |
519 | regulator-max-microvolt = <1800000>; | |
520 | }; | |
521 | ||
b9c665d7 | 522 | ldo9 { |
6529e638 SW |
523 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; |
524 | regulator-min-microvolt = <2850000>; | |
525 | regulator-max-microvolt = <2850000>; | |
526 | regulator-always-on; | |
527 | }; | |
528 | ||
b9c665d7 | 529 | ldo_rtc { |
6529e638 SW |
530 | regulator-name = "vdd_rtc_out,vdd_cell"; |
531 | regulator-min-microvolt = <3300000>; | |
532 | regulator-max-microvolt = <3300000>; | |
533 | regulator-always-on; | |
534 | }; | |
535 | }; | |
536 | }; | |
537 | ||
45dbe9dd | 538 | temperature-sensor@4c { |
9846210b | 539 | compatible = "onnn,nct1008"; |
401c9a50 SW |
540 | reg = <0x4c>; |
541 | }; | |
f0d14306 | 542 | }; |
d8017a97 | 543 | |
58ecb23f | 544 | kbc@7000e200 { |
beb0e325 LD |
545 | status = "okay"; |
546 | nvidia,debounce-delay-ms = <32>; | |
547 | nvidia,repeat-delay-ms = <160>; | |
548 | nvidia,ghost-filter; | |
549 | nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; | |
550 | nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; | |
6bccbd5e LD |
551 | linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) |
552 | MATRIX_KEY(0x00, 0x03, KEY_S) | |
553 | MATRIX_KEY(0x00, 0x04, KEY_A) | |
554 | MATRIX_KEY(0x00, 0x05, KEY_Z) | |
555 | MATRIX_KEY(0x00, 0x07, KEY_FN) | |
556 | ||
557 | MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA) | |
558 | MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT) | |
559 | MATRIX_KEY(0x02, 0x07, KEY_LEFTALT) | |
560 | ||
561 | MATRIX_KEY(0x03, 0x00, KEY_5) | |
562 | MATRIX_KEY(0x03, 0x01, KEY_4) | |
563 | MATRIX_KEY(0x03, 0x02, KEY_R) | |
564 | MATRIX_KEY(0x03, 0x03, KEY_E) | |
565 | MATRIX_KEY(0x03, 0x04, KEY_F) | |
566 | MATRIX_KEY(0x03, 0x05, KEY_D) | |
567 | MATRIX_KEY(0x03, 0x06, KEY_X) | |
568 | ||
569 | MATRIX_KEY(0x04, 0x00, KEY_7) | |
570 | MATRIX_KEY(0x04, 0x01, KEY_6) | |
571 | MATRIX_KEY(0x04, 0x02, KEY_T) | |
572 | MATRIX_KEY(0x04, 0x03, KEY_H) | |
573 | MATRIX_KEY(0x04, 0x04, KEY_G) | |
574 | MATRIX_KEY(0x04, 0x05, KEY_V) | |
575 | MATRIX_KEY(0x04, 0x06, KEY_C) | |
576 | MATRIX_KEY(0x04, 0x07, KEY_SPACE) | |
577 | ||
578 | MATRIX_KEY(0x05, 0x00, KEY_9) | |
579 | MATRIX_KEY(0x05, 0x01, KEY_8) | |
580 | MATRIX_KEY(0x05, 0x02, KEY_U) | |
581 | MATRIX_KEY(0x05, 0x03, KEY_Y) | |
582 | MATRIX_KEY(0x05, 0x04, KEY_J) | |
583 | MATRIX_KEY(0x05, 0x05, KEY_N) | |
584 | MATRIX_KEY(0x05, 0x06, KEY_B) | |
585 | MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) | |
586 | ||
587 | MATRIX_KEY(0x06, 0x00, KEY_MINUS) | |
588 | MATRIX_KEY(0x06, 0x01, KEY_0) | |
589 | MATRIX_KEY(0x06, 0x02, KEY_O) | |
590 | MATRIX_KEY(0x06, 0x03, KEY_I) | |
591 | MATRIX_KEY(0x06, 0x04, KEY_L) | |
592 | MATRIX_KEY(0x06, 0x05, KEY_K) | |
593 | MATRIX_KEY(0x06, 0x06, KEY_COMMA) | |
594 | MATRIX_KEY(0x06, 0x07, KEY_M) | |
595 | ||
596 | MATRIX_KEY(0x07, 0x01, KEY_EQUAL) | |
597 | MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) | |
598 | MATRIX_KEY(0x07, 0x03, KEY_ENTER) | |
599 | MATRIX_KEY(0x07, 0x07, KEY_MENU) | |
600 | ||
601 | MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT) | |
602 | MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT) | |
603 | ||
604 | MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL) | |
605 | MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL) | |
606 | ||
607 | MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) | |
608 | MATRIX_KEY(0x0B, 0x01, KEY_P) | |
609 | MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) | |
610 | MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) | |
611 | MATRIX_KEY(0x0B, 0x04, KEY_SLASH) | |
612 | MATRIX_KEY(0x0B, 0x05, KEY_DOT) | |
613 | ||
614 | MATRIX_KEY(0x0C, 0x00, KEY_F10) | |
615 | MATRIX_KEY(0x0C, 0x01, KEY_F9) | |
616 | MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) | |
617 | MATRIX_KEY(0x0C, 0x03, KEY_3) | |
618 | MATRIX_KEY(0x0C, 0x04, KEY_2) | |
619 | MATRIX_KEY(0x0C, 0x05, KEY_UP) | |
620 | MATRIX_KEY(0x0C, 0x06, KEY_PRINT) | |
621 | MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) | |
622 | ||
623 | MATRIX_KEY(0x0D, 0x00, KEY_INSERT) | |
624 | MATRIX_KEY(0x0D, 0x01, KEY_DELETE) | |
625 | MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) | |
626 | MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) | |
627 | MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) | |
628 | MATRIX_KEY(0x0D, 0x06, KEY_DOWN) | |
629 | MATRIX_KEY(0x0D, 0x07, KEY_LEFT) | |
630 | ||
631 | MATRIX_KEY(0x0E, 0x00, KEY_F11) | |
632 | MATRIX_KEY(0x0E, 0x01, KEY_F12) | |
633 | MATRIX_KEY(0x0E, 0x02, KEY_F8) | |
634 | MATRIX_KEY(0x0E, 0x03, KEY_Q) | |
635 | MATRIX_KEY(0x0E, 0x04, KEY_F4) | |
636 | MATRIX_KEY(0x0E, 0x05, KEY_F3) | |
637 | MATRIX_KEY(0x0E, 0x06, KEY_1) | |
638 | MATRIX_KEY(0x0E, 0x07, KEY_F7) | |
639 | ||
640 | MATRIX_KEY(0x0F, 0x00, KEY_ESC) | |
641 | MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) | |
642 | MATRIX_KEY(0x0F, 0x02, KEY_F5) | |
643 | MATRIX_KEY(0x0F, 0x03, KEY_TAB) | |
644 | MATRIX_KEY(0x0F, 0x04, KEY_F1) | |
645 | MATRIX_KEY(0x0F, 0x05, KEY_F2) | |
646 | MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) | |
647 | MATRIX_KEY(0x0F, 0x07, KEY_F6) | |
beb0e325 LD |
648 | |
649 | /* Software Handled Function Keys */ | |
6bccbd5e LD |
650 | MATRIX_KEY(0x14, 0x00, KEY_KP7) |
651 | ||
652 | MATRIX_KEY(0x15, 0x00, KEY_KP9) | |
653 | MATRIX_KEY(0x15, 0x01, KEY_KP8) | |
654 | MATRIX_KEY(0x15, 0x02, KEY_KP4) | |
655 | MATRIX_KEY(0x15, 0x04, KEY_KP1) | |
656 | ||
657 | MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) | |
658 | MATRIX_KEY(0x16, 0x02, KEY_KP6) | |
659 | MATRIX_KEY(0x16, 0x03, KEY_KP5) | |
660 | MATRIX_KEY(0x16, 0x04, KEY_KP3) | |
661 | MATRIX_KEY(0x16, 0x05, KEY_KP2) | |
662 | MATRIX_KEY(0x16, 0x07, KEY_KP0) | |
663 | ||
664 | MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) | |
665 | MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) | |
666 | MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) | |
667 | MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) | |
668 | ||
669 | MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) | |
670 | ||
671 | MATRIX_KEY(0x1D, 0x03, KEY_HOME) | |
672 | MATRIX_KEY(0x1D, 0x04, KEY_END) | |
673 | MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN) | |
674 | MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) | |
675 | MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP) | |
676 | ||
677 | MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) | |
678 | MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) | |
679 | MATRIX_KEY(0x1E, 0x02, KEY_MUTE) | |
680 | ||
681 | MATRIX_KEY(0x1F, 0x04, KEY_HELP)>; | |
beb0e325 | 682 | }; |
57899053 SW |
683 | |
684 | pmc@7000e400 { | |
685 | nvidia,invert-interrupt; | |
686 | nvidia,suspend-mode = <1>; | |
687 | nvidia,cpu-pwr-good-time = <5000>; | |
688 | nvidia,cpu-pwr-off-time = <5000>; | |
689 | nvidia,core-pwr-good-time = <3845 3845>; | |
690 | nvidia,core-pwr-off-time = <3875>; | |
691 | nvidia,sys-clock-req-active-high; | |
692 | }; | |
693 | ||
694 | memory-controller@7000f400 { | |
695 | emc-table@190000 { | |
696 | reg = <190000>; | |
697 | compatible = "nvidia,tegra20-emc-table"; | |
698 | clock-frequency = <190000>; | |
699 | nvidia,emc-registers = <0x0000000c 0x00000026 | |
700 | 0x00000009 0x00000003 0x00000004 0x00000004 | |
701 | 0x00000002 0x0000000c 0x00000003 0x00000003 | |
702 | 0x00000002 0x00000001 0x00000004 0x00000005 | |
703 | 0x00000004 0x00000009 0x0000000d 0x0000059f | |
704 | 0x00000000 0x00000003 0x00000003 0x00000003 | |
705 | 0x00000003 0x00000001 0x0000000b 0x000000c8 | |
706 | 0x00000003 0x00000007 0x00000004 0x0000000f | |
707 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
708 | 0x00000000 0x00000000 0x00000083 0xa06204ae | |
709 | 0x007dc010 0x00000000 0x00000000 0x00000000 | |
710 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
711 | }; | |
712 | ||
713 | emc-table@380000 { | |
714 | reg = <380000>; | |
715 | compatible = "nvidia,tegra20-emc-table"; | |
716 | clock-frequency = <380000>; | |
717 | nvidia,emc-registers = <0x00000017 0x0000004b | |
718 | 0x00000012 0x00000006 0x00000004 0x00000005 | |
719 | 0x00000003 0x0000000c 0x00000006 0x00000006 | |
720 | 0x00000003 0x00000001 0x00000004 0x00000005 | |
721 | 0x00000004 0x00000009 0x0000000d 0x00000b5f | |
722 | 0x00000000 0x00000003 0x00000003 0x00000006 | |
723 | 0x00000006 0x00000001 0x00000011 0x000000c8 | |
724 | 0x00000003 0x0000000e 0x00000007 0x0000000f | |
725 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
726 | 0x00000000 0x00000000 0x00000083 0xe044048b | |
727 | 0x007d8010 0x00000000 0x00000000 0x00000000 | |
728 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
729 | }; | |
730 | }; | |
731 | ||
732 | usb@c5000000 { | |
733 | status = "okay"; | |
734 | dr_mode = "otg"; | |
735 | }; | |
736 | ||
737 | usb-phy@c5000000 { | |
738 | status = "okay"; | |
739 | vbus-supply = <&vbus_reg>; | |
740 | dr_mode = "otg"; | |
741 | }; | |
742 | ||
743 | usb@c5004000 { | |
744 | status = "okay"; | |
745 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) | |
746 | GPIO_ACTIVE_LOW>; | |
747 | }; | |
748 | ||
749 | usb-phy@c5004000 { | |
750 | status = "okay"; | |
751 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) | |
752 | GPIO_ACTIVE_LOW>; | |
753 | }; | |
754 | ||
755 | usb@c5008000 { | |
756 | status = "okay"; | |
757 | }; | |
758 | ||
759 | usb-phy@c5008000 { | |
760 | status = "okay"; | |
761 | }; | |
762 | ||
763 | sdhci@c8000000 { | |
764 | status = "okay"; | |
765 | power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | |
766 | bus-width = <4>; | |
767 | keep-power-in-suspend; | |
768 | }; | |
769 | ||
770 | sdhci@c8000400 { | |
771 | status = "okay"; | |
772 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; | |
773 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; | |
774 | power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; | |
775 | bus-width = <4>; | |
776 | }; | |
777 | ||
778 | sdhci@c8000600 { | |
779 | status = "okay"; | |
780 | bus-width = <8>; | |
781 | non-removable; | |
782 | }; | |
783 | ||
9615d656 SW |
784 | backlight: backlight { |
785 | compatible = "pwm-backlight"; | |
786 | ||
787 | enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; | |
788 | power-supply = <&vdd_bl_reg>; | |
789 | pwms = <&pwm 2 5000000>; | |
790 | ||
791 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
792 | default-brightness-level = <6>; | |
793 | }; | |
794 | ||
57899053 SW |
795 | clocks { |
796 | compatible = "simple-bus"; | |
797 | #address-cells = <1>; | |
798 | #size-cells = <0>; | |
799 | ||
800 | clk32k_in: clock@0 { | |
801 | compatible = "fixed-clock"; | |
4ec2e601 | 802 | reg = <0>; |
57899053 SW |
803 | #clock-cells = <0>; |
804 | clock-frequency = <32768>; | |
805 | }; | |
806 | }; | |
807 | ||
808 | gpio-keys { | |
809 | compatible = "gpio-keys"; | |
810 | ||
811 | power { | |
812 | label = "Power"; | |
813 | gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; | |
6bccbd5e | 814 | linux,code = <KEY_POWER>; |
d1c04d30 | 815 | wakeup-source; |
57899053 SW |
816 | }; |
817 | ||
818 | lid { | |
819 | label = "Lid"; | |
820 | gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; | |
821 | linux,input-type = <5>; /* EV_SW */ | |
822 | linux,code = <0>; /* SW_LID */ | |
823 | debounce-interval = <1>; | |
d1c04d30 | 824 | wakeup-source; |
57899053 SW |
825 | }; |
826 | }; | |
827 | ||
9615d656 SW |
828 | panel: panel { |
829 | compatible = "chunghwa,claa101wa01a", "simple-panel"; | |
830 | ||
831 | power-supply = <&vdd_pnl_reg>; | |
832 | enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; | |
833 | ||
834 | backlight = <&backlight>; | |
835 | ddc-i2c-bus = <&lvds_ddc>; | |
836 | }; | |
837 | ||
6529e638 SW |
838 | regulators { |
839 | compatible = "simple-bus"; | |
840 | #address-cells = <1>; | |
841 | #size-cells = <0>; | |
842 | ||
843 | vdd_5v0_reg: regulator@0 { | |
844 | compatible = "regulator-fixed"; | |
845 | reg = <0>; | |
846 | regulator-name = "vdd_5v0"; | |
847 | regulator-min-microvolt = <5000000>; | |
848 | regulator-max-microvolt = <5000000>; | |
849 | regulator-always-on; | |
850 | }; | |
851 | ||
852 | regulator@1 { | |
853 | compatible = "regulator-fixed"; | |
854 | reg = <1>; | |
855 | regulator-name = "vdd_1v5"; | |
856 | regulator-min-microvolt = <1500000>; | |
857 | regulator-max-microvolt = <1500000>; | |
3325f1bc | 858 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
6529e638 SW |
859 | }; |
860 | ||
861 | regulator@2 { | |
862 | compatible = "regulator-fixed"; | |
863 | reg = <2>; | |
864 | regulator-name = "vdd_1v2"; | |
865 | regulator-min-microvolt = <1200000>; | |
866 | regulator-max-microvolt = <1200000>; | |
3325f1bc | 867 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
6529e638 SW |
868 | enable-active-high; |
869 | }; | |
4c94c8b5 VB |
870 | |
871 | vbus_reg: regulator@3 { | |
872 | compatible = "regulator-fixed"; | |
873 | reg = <3>; | |
874 | regulator-name = "vdd_vbus_wup1"; | |
875 | regulator-min-microvolt = <5000000>; | |
876 | regulator-max-microvolt = <5000000>; | |
9f310ded | 877 | enable-active-high; |
23f95ef2 | 878 | gpio = <&gpio TEGRA_GPIO(D, 0) 0>; |
30ca2226 SW |
879 | regulator-always-on; |
880 | regulator-boot-on; | |
4c94c8b5 | 881 | }; |
9615d656 SW |
882 | |
883 | vdd_pnl_reg: regulator@4 { | |
884 | compatible = "regulator-fixed"; | |
885 | reg = <4>; | |
886 | regulator-name = "vdd_pnl"; | |
887 | regulator-min-microvolt = <2800000>; | |
888 | regulator-max-microvolt = <2800000>; | |
889 | gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; | |
890 | enable-active-high; | |
891 | }; | |
892 | ||
893 | vdd_bl_reg: regulator@5 { | |
894 | compatible = "regulator-fixed"; | |
895 | reg = <5>; | |
896 | regulator-name = "vdd_bl"; | |
897 | regulator-min-microvolt = <2800000>; | |
898 | regulator-max-microvolt = <2800000>; | |
899 | gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; | |
900 | enable-active-high; | |
901 | }; | |
5264d274 TR |
902 | |
903 | vdd_hdmi: regulator@6 { | |
904 | compatible = "regulator-fixed"; | |
905 | reg = <6>; | |
906 | regulator-name = "VDDIO_HDMI"; | |
907 | regulator-min-microvolt = <5000000>; | |
908 | regulator-max-microvolt = <5000000>; | |
909 | gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; | |
910 | enable-active-high; | |
911 | vin-supply = <&vdd_5v0_reg>; | |
912 | }; | |
6529e638 SW |
913 | }; |
914 | ||
c04abb3a SW |
915 | sound { |
916 | compatible = "nvidia,tegra-audio-wm8903-seaboard", | |
917 | "nvidia,tegra-audio-wm8903"; | |
918 | nvidia,model = "NVIDIA Tegra Seaboard"; | |
d8017a97 | 919 | |
c04abb3a SW |
920 | nvidia,audio-routing = |
921 | "Headphone Jack", "HPOUTR", | |
922 | "Headphone Jack", "HPOUTL", | |
923 | "Int Spk", "ROP", | |
924 | "Int Spk", "RON", | |
925 | "Int Spk", "LOP", | |
926 | "Int Spk", "LON", | |
927 | "Mic Jack", "MICBIAS", | |
928 | "IN1R", "Mic Jack"; | |
aa607ebf | 929 | |
c04abb3a SW |
930 | nvidia,i2s-controller = <&tegra_i2s1>; |
931 | nvidia,audio-codec = <&wm8903>; | |
932 | ||
3325f1bc SW |
933 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
934 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; | |
f9cd2b3b | 935 | |
885a8cfa HD |
936 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
937 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | |
938 | <&tegra_car TEGRA20_CLK_CDEV1>; | |
f9cd2b3b | 939 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
aa607ebf | 940 | }; |
8e267f3d | 941 | }; |