projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 731fb450 TR |
1 | /dts-v1/; |
| 2 | ||
| 1bd0bd49 | 3 | #include "tegra20-tamonten.dtsi" |
| 731fb450 TR |
4 | |
| 5 | / { | |
| 6 | model = "Avionic Design Medcom-Wide board"; | |
| 7 | compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; | |
| 8 | ||
| 58ecb23f | 9 | pwm@7000a000 { |
| b69cd984 AC |
10 | status = "okay"; |
| 11 | }; | |
| 12 | ||
| 731fb450 TR |
13 | i2c@7000c000 { |
| 14 | wm8903: wm8903@1a { | |
| 15 | compatible = "wlf,wm8903"; | |
| 16 | reg = <0x1a>; | |
| 17 | interrupt-parent = <&gpio>; | |
| 6cecf916 | 18 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
| 731fb450 TR |
19 | |
| 20 | gpio-controller; | |
| 21 | #gpio-cells = <2>; | |
| 22 | ||
| 23 | micdet-cfg = <0>; | |
| 24 | micdet-delay = <100>; | |
| 25 | gpio-cfg = <0xffffffff | |
| 26 | 0xffffffff | |
| 27 | 0 | |
| 28 | 0xffffffff | |
| 29 | 0xffffffff>; | |
| 30 | }; | |
| 31 | }; | |
| 32 | ||
| 33 | backlight { | |
| 34 | compatible = "pwm-backlight"; | |
| 35 | pwms = <&pwm 0 5000000>; | |
| 36 | ||
| 37 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
| 38 | default-brightness-level = <6>; | |
| 39 | }; | |
| 40 | ||
| 41 | sound { | |
| 42 | compatible = "ad,tegra-audio-wm8903-medcom-wide", | |
| 43 | "nvidia,tegra-audio-wm8903"; | |
| 44 | nvidia,model = "Avionic Design Medcom-Wide"; | |
| 45 | ||
| 46 | nvidia,audio-routing = | |
| 47 | "Headphone Jack", "HPOUTR", | |
| 48 | "Headphone Jack", "HPOUTL", | |
| 49 | "Int Spk", "ROP", | |
| 50 | "Int Spk", "RON", | |
| 51 | "Int Spk", "LOP", | |
| 52 | "Int Spk", "LON", | |
| 53 | "Mic Jack", "MICBIAS", | |
| 54 | "IN1L", "Mic Jack"; | |
| 55 | ||
| 56 | nvidia,i2s-controller = <&tegra_i2s1>; | |
| 57 | nvidia,audio-codec = <&wm8903>; | |
| 58 | ||
| 3325f1bc SW |
59 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 60 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; | |
| f9cd2b3b | 61 | |
| 885a8cfa HD |
62 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 63 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | |
| 64 | <&tegra_car TEGRA20_CLK_CDEV1>; | |
| f9cd2b3b | 65 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 731fb450 TR |
66 | }; |
| 67 | }; |