Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1bd0bd49 | 2 | #include "tegra20.dtsi" |
fc9c713a LS |
3 | |
4 | / { | |
8ab11f80 | 5 | model = "Toradex Colibri T20 256/512 MB"; |
fc9c713a LS |
6 | compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; |
7 | ||
48299769 | 8 | memory@0 { |
8ab11f80 KK |
9 | /* |
10 | * Set memory to 256 MB to be safe as this could be used on | |
11 | * 256 or 512 MB module. It is expected from bootloader | |
12 | * to fix this up for 512 MB version. | |
13 | */ | |
14 | reg = <0x00000000 0x10000000>; | |
fc9c713a LS |
15 | }; |
16 | ||
58ecb23f SW |
17 | host1x@50000000 { |
18 | hdmi@54280000 { | |
fc9c713a | 19 | nvidia,ddc-i2c-bus = <&i2c_ddc>; |
e6800c21 MZ |
20 | nvidia,hpd-gpio = |
21 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
3647c7b8 MZ |
22 | pll-supply = <®_1v8_avdd_hdmi_pll>; |
23 | vdd-supply = <®_3v3_avdd_hdmi>; | |
fc9c713a LS |
24 | }; |
25 | }; | |
26 | ||
58ecb23f | 27 | pinmux@70000014 { |
fc9c713a LS |
28 | pinctrl-names = "default"; |
29 | pinctrl-0 = <&state_default>; | |
30 | ||
31 | state_default: pinmux { | |
a2cb59be MZ |
32 | /* Analogue Audio AC97 to WM9712 (On-module) */ |
33 | audio-refclk { | |
fc9c713a LS |
34 | nvidia,pins = "cdev1"; |
35 | nvidia,function = "plla_out"; | |
ba4104e7 LD |
36 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
37 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a | 38 | }; |
fc9c713a LS |
39 | dap3 { |
40 | nvidia,pins = "dap3"; | |
41 | nvidia,function = "dap3"; | |
ba4104e7 LD |
42 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
43 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a | 44 | }; |
a2cb59be MZ |
45 | |
46 | /* | |
47 | * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ | |
48 | * (All on-module), SODIMM Pin 45 Wakeup | |
49 | */ | |
50 | gpio-uac { | |
51 | nvidia,pins = "uac"; | |
52 | nvidia,function = "rsvd2"; | |
ba4104e7 LD |
53 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
54 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a | 55 | }; |
a2cb59be MZ |
56 | |
57 | /* | |
58 | * Buffer Enables for nPWE and RDnWR (On-module, | |
59 | * see GPIO hogging further down below) | |
60 | */ | |
61 | gpio-pta { | |
fc9c713a LS |
62 | nvidia,pins = "pta"; |
63 | nvidia,function = "rsvd4"; | |
ba4104e7 LD |
64 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
65 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a | 66 | }; |
a2cb59be MZ |
67 | |
68 | /* | |
69 | * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N, | |
70 | * SYS_CLK_REQ (All on-module) | |
71 | */ | |
72 | pmc { | |
73 | nvidia,pins = "pmc"; | |
74 | nvidia,function = "pwr_on"; | |
ba4104e7 | 75 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
fc9c713a | 76 | }; |
a2cb59be | 77 | |
992cf09b MZ |
78 | /* |
79 | * Colibri Address/Data Bus (GMI) | |
80 | * Note: spid and spie optionally used for SPI1 | |
81 | */ | |
82 | gmi { | |
83 | nvidia,pins = "atc", "atd", "ate", "dap1", | |
84 | "dap2", "dap4", "gmd", "gpu", | |
85 | "irrx", "irtx", "spia", "spib", | |
86 | "spic", "spid", "spie", "uca", | |
87 | "ucb"; | |
a2cb59be MZ |
88 | nvidia,function = "gmi"; |
89 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
992cf09b MZ |
90 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
91 | }; | |
92 | /* Further pins may be used as GPIOs */ | |
93 | gmi-gpio1 { | |
94 | nvidia,pins = "lpw0", "lsc1", "lsck", "lsda"; | |
95 | nvidia,function = "hdmi"; | |
96 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
97 | }; | |
98 | gmi-gpio2 { | |
99 | nvidia,pins = "lcsn", "ldc", "lm0", "lsdi"; | |
100 | nvidia,function = "rsvd4"; | |
101 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 102 | }; |
a2cb59be MZ |
103 | |
104 | /* Colibri BL_ON */ | |
105 | bl-on { | |
106 | nvidia,pins = "dta"; | |
992cf09b | 107 | nvidia,function = "rsvd1"; |
ba4104e7 LD |
108 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
109 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 110 | }; |
a2cb59be MZ |
111 | |
112 | /* Colibri Backlight PWM<A>, PWM<B> */ | |
113 | pwm-a-b { | |
114 | nvidia,pins = "sdc"; | |
115 | nvidia,function = "pwm"; | |
ba4104e7 | 116 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fc9c713a | 117 | }; |
a2cb59be MZ |
118 | |
119 | /* Colibri DDC */ | |
120 | ddc { | |
fc9c713a LS |
121 | nvidia,pins = "ddc"; |
122 | nvidia,function = "i2c2"; | |
ba4104e7 LD |
123 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
124 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 125 | }; |
a2cb59be MZ |
126 | |
127 | /* | |
128 | * Colibri EXT_IO* | |
129 | * Note: dtf optionally used for I2C3 | |
130 | */ | |
131 | ext-io { | |
992cf09b MZ |
132 | nvidia,pins = "dtf", "spdi"; |
133 | nvidia,function = "rsvd2"; | |
ba4104e7 | 134 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
a2cb59be | 135 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fc9c713a | 136 | }; |
a2cb59be MZ |
137 | |
138 | /* | |
139 | * Colibri Ethernet (On-module) | |
140 | * ULPI EHCI instance 1 USB2_DP/N -> AX88772B | |
141 | */ | |
142 | ulpi { | |
143 | nvidia,pins = "uaa", "uab", "uda"; | |
144 | nvidia,function = "ulpi"; | |
ba4104e7 | 145 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
a2cb59be | 146 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
fc9c713a | 147 | }; |
a2cb59be MZ |
148 | ulpi-refclk { |
149 | nvidia,pins = "cdev2"; | |
150 | nvidia,function = "pllp_out4"; | |
ba4104e7 LD |
151 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
152 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a | 153 | }; |
a2cb59be MZ |
154 | |
155 | /* Colibri HOTPLUG_DETECT (HDMI) */ | |
156 | hotplug-detect { | |
157 | nvidia,pins = "hdint"; | |
158 | nvidia,function = "hdmi"; | |
159 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
160 | }; | |
161 | ||
162 | /* Colibri I2C */ | |
163 | i2c { | |
164 | nvidia,pins = "rm"; | |
165 | nvidia,function = "i2c1"; | |
ba4104e7 LD |
166 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
167 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 168 | }; |
a2cb59be | 169 | |
992cf09b MZ |
170 | /* |
171 | * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE | |
172 | * today's display need DE, disable LCD_M1 | |
173 | */ | |
174 | lm1 { | |
175 | nvidia,pins = "lm1"; | |
176 | nvidia,function = "rsvd3"; | |
177 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
178 | }; | |
179 | ||
a2cb59be MZ |
180 | /* Colibri LCD (L_* resp. LDD<*>) */ |
181 | lcd { | |
182 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", | |
183 | "ld4", "ld5", "ld6", "ld7", | |
184 | "ld8", "ld9", "ld10", "ld11", | |
185 | "ld12", "ld13", "ld14", "ld15", | |
992cf09b MZ |
186 | "ld16", "ld17", "lhs", "lsc0", |
187 | "lspi", "lvs"; | |
188 | nvidia,function = "displaya"; | |
189 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
190 | }; | |
191 | /* Colibri LCD (Optional 24 BPP Support) */ | |
192 | lcd-24 { | |
193 | nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2", | |
194 | "lpp", "lvp1"; | |
a2cb59be MZ |
195 | nvidia,function = "displaya"; |
196 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 197 | }; |
a2cb59be MZ |
198 | |
199 | /* Colibri MMC */ | |
200 | mmc { | |
201 | nvidia,pins = "atb", "gma"; | |
202 | nvidia,function = "sdio4"; | |
203 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
ba4104e7 | 204 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fc9c713a | 205 | }; |
a2cb59be | 206 | |
992cf09b MZ |
207 | /* Colibri MMCCD */ |
208 | mmccd { | |
209 | nvidia,pins = "gmb"; | |
210 | nvidia,function = "gmi_int"; | |
211 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
212 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
213 | }; | |
214 | ||
a2cb59be MZ |
215 | /* Colibri MMC (Optional 8-bit) */ |
216 | mmc-8bit { | |
217 | nvidia,pins = "gme"; | |
fc9c713a | 218 | nvidia,function = "sdio4"; |
ba4104e7 LD |
219 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
220 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 221 | }; |
a2cb59be MZ |
222 | |
223 | /* | |
224 | * Colibri Parallel Camera (Optional) | |
225 | * pins multiplexed with others and therefore disabled | |
226 | * Note: dta used for BL_ON by default | |
227 | */ | |
228 | cif-mclk { | |
229 | nvidia,pins = "csus"; | |
230 | nvidia,function = "vi_sensor_clk"; | |
231 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
232 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
233 | }; | |
234 | cif { | |
235 | nvidia,pins = "dtb", "dtc", "dtd"; | |
236 | nvidia,function = "vi"; | |
ba4104e7 LD |
237 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
238 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 239 | }; |
a2cb59be MZ |
240 | |
241 | /* Colibri PWM<C>, PWM<D> */ | |
242 | pwm-c-d { | |
243 | nvidia,pins = "sdb", "sdd"; | |
244 | nvidia,function = "pwm"; | |
245 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
246 | }; | |
247 | ||
248 | /* Colibri SSP */ | |
249 | ssp { | |
fc9c713a LS |
250 | nvidia,pins = "slxa", "slxc", "slxd", "slxk"; |
251 | nvidia,function = "spi4"; | |
ba4104e7 LD |
252 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
253 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 254 | }; |
a2cb59be MZ |
255 | |
256 | /* Colibri UART-A */ | |
257 | uart-a { | |
fc9c713a LS |
258 | nvidia,pins = "sdio1"; |
259 | nvidia,function = "uarta"; | |
ba4104e7 LD |
260 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
261 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 262 | }; |
992cf09b MZ |
263 | uart-a-dsr { |
264 | nvidia,pins = "lpw1"; | |
265 | nvidia,function = "rsvd3"; | |
266 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
267 | }; | |
268 | uart-a-dcd { | |
269 | nvidia,pins = "lpw2"; | |
270 | nvidia,function = "hdmi"; | |
271 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
272 | }; | |
a2cb59be MZ |
273 | |
274 | /* Colibri UART-B */ | |
275 | uart-b { | |
fc9c713a LS |
276 | nvidia,pins = "gmc"; |
277 | nvidia,function = "uartd"; | |
ba4104e7 LD |
278 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
279 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 280 | }; |
a2cb59be MZ |
281 | |
282 | /* Colibri UART-C */ | |
283 | uart-c { | |
284 | nvidia,pins = "uad"; | |
285 | nvidia,function = "irda"; | |
ba4104e7 | 286 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
a2cb59be | 287 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fc9c713a | 288 | }; |
a2cb59be | 289 | |
992cf09b MZ |
290 | /* Colibri USB_CDET */ |
291 | usb-cdet { | |
292 | nvidia,pins = "spdo"; | |
293 | nvidia,function = "rsvd2"; | |
294 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
295 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
296 | }; | |
297 | ||
a2cb59be MZ |
298 | /* Colibri USBH_OC */ |
299 | usbh-oc { | |
300 | nvidia,pins = "spih"; | |
301 | nvidia,function = "spi2_alt"; | |
ba4104e7 | 302 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
992cf09b | 303 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fc9c713a | 304 | }; |
a2cb59be MZ |
305 | |
306 | /* Colibri USBH_PEN */ | |
307 | usbh-pen { | |
308 | nvidia,pins = "spig"; | |
fc9c713a | 309 | nvidia,function = "spi2_alt"; |
ba4104e7 | 310 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
992cf09b | 311 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fc9c713a | 312 | }; |
a2cb59be MZ |
313 | |
314 | /* Colibri VGA not supported */ | |
315 | vga { | |
316 | nvidia,pins = "crtp"; | |
317 | nvidia,function = "crt"; | |
ba4104e7 LD |
318 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
319 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 320 | }; |
a2cb59be | 321 | |
992cf09b MZ |
322 | /* I2C3 (Optional) */ |
323 | i2c3 { | |
324 | nvidia,pins = "dtf"; | |
325 | nvidia,function = "i2c3"; | |
326 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
327 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
328 | }; | |
329 | ||
330 | /* JTAG_RTCK */ | |
331 | jtag-rtck { | |
332 | nvidia,pins = "gpu7"; | |
333 | nvidia,function = "rtck"; | |
334 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
335 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
336 | }; | |
337 | ||
338 | /* | |
339 | * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME | |
340 | * (All On-module) | |
341 | */ | |
342 | gpio-gpv { | |
343 | nvidia,pins = "gpv"; | |
344 | nvidia,function = "rsvd2"; | |
345 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
346 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
347 | }; | |
348 | ||
a2cb59be MZ |
349 | /* |
350 | * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN | |
351 | * (All On-module); Colibri CAN_INT | |
352 | */ | |
353 | gpio-dte { | |
354 | nvidia,pins = "dte"; | |
355 | nvidia,function = "rsvd1"; | |
356 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
357 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
358 | }; | |
359 | ||
360 | /* NAND (On-module) */ | |
361 | nand { | |
992cf09b | 362 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
a2cb59be MZ |
363 | "kbce", "kbcf"; |
364 | nvidia,function = "nand"; | |
365 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
366 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
367 | }; | |
368 | ||
369 | /* Onewire (Optional) */ | |
370 | owr { | |
371 | nvidia,pins = "owc"; | |
372 | nvidia,function = "owr"; | |
373 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
374 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
375 | }; | |
376 | ||
377 | /* Power I2C (On-module) */ | |
378 | i2cp { | |
379 | nvidia,pins = "i2cp"; | |
380 | nvidia,function = "i2cp"; | |
381 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
382 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
383 | }; | |
384 | ||
992cf09b MZ |
385 | /* RESET_OUT */ |
386 | reset-out { | |
387 | nvidia,pins = "ata"; | |
388 | nvidia,function = "gmi"; | |
389 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
390 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
391 | }; | |
392 | ||
a2cb59be MZ |
393 | /* |
394 | * SPI1 (Optional) | |
395 | * Note: spid and spie used for Colibri Address/Data | |
396 | * Bus (GMI) | |
397 | */ | |
398 | spi1 { | |
399 | nvidia,pins = "spid", "spie", "spif"; | |
400 | nvidia,function = "spi1"; | |
ba4104e7 LD |
401 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
402 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a | 403 | }; |
992cf09b MZ |
404 | |
405 | /* | |
406 | * THERMD_ALERT# (On-module), unlatched I2C address pin | |
407 | * of LM95245 temperature sensor therefore requires | |
408 | * disabling for now | |
409 | */ | |
410 | lvp0 { | |
411 | nvidia,pins = "lvp0"; | |
412 | nvidia,function = "rsvd3"; | |
413 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
414 | }; | |
fc9c713a LS |
415 | }; |
416 | }; | |
417 | ||
57899053 SW |
418 | ac97: ac97@70002000 { |
419 | status = "okay"; | |
035ae62d MZ |
420 | nvidia,codec-reset-gpio = |
421 | <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; | |
422 | nvidia,codec-sync-gpio = | |
423 | <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; | |
57899053 SW |
424 | }; |
425 | ||
9ad510b3 MZ |
426 | serial@70006040 { |
427 | compatible = "nvidia,tegra20-hsuart"; | |
428 | }; | |
429 | ||
430 | serial@70006300 { | |
431 | compatible = "nvidia,tegra20-hsuart"; | |
432 | }; | |
433 | ||
5def854e SA |
434 | nand-controller@70008000 { |
435 | status = "okay"; | |
436 | ||
437 | nand@0 { | |
438 | reg = <0>; | |
439 | #address-cells = <1>; | |
440 | #size-cells = <1>; | |
441 | nand-bus-width = <8>; | |
442 | nand-on-flash-bbt; | |
443 | nand-ecc-algo = "bch"; | |
444 | nand-is-boot-medium; | |
445 | nand-ecc-maximize; | |
446 | wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; | |
447 | }; | |
448 | }; | |
449 | ||
1c3389e6 MZ |
450 | /* |
451 | * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier | |
452 | * board) | |
453 | */ | |
fc9c713a LS |
454 | i2c@7000c000 { |
455 | clock-frequency = <400000>; | |
456 | }; | |
457 | ||
1c3389e6 | 458 | /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ |
fc9c713a | 459 | i2c_ddc: i2c@7000c400 { |
1c3389e6 | 460 | clock-frequency = <10000>; |
fc9c713a LS |
461 | }; |
462 | ||
1c3389e6 | 463 | /* GEN2_I2C: unused */ |
fc9c713a | 464 | |
1c3389e6 MZ |
465 | /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */ |
466 | ||
467 | /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */ | |
fc9c713a LS |
468 | i2c@7000d000 { |
469 | status = "okay"; | |
1c3389e6 | 470 | clock-frequency = <100000>; |
fc9c713a LS |
471 | |
472 | pmic: tps6586x@34 { | |
473 | compatible = "ti,tps6586x"; | |
474 | reg = <0x34>; | |
6cecf916 | 475 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
fc9c713a | 476 | ti,system-power-controller; |
fc9c713a LS |
477 | #gpio-cells = <2>; |
478 | gpio-controller; | |
3647c7b8 MZ |
479 | sys-supply = <®_module_3v3>; |
480 | vin-sm0-supply = <®_3v3_vsys>; | |
481 | vin-sm1-supply = <®_3v3_vsys>; | |
482 | vin-sm2-supply = <®_3v3_vsys>; | |
483 | vinldo01-supply = <®_1v8_vdd_ddr2>; | |
484 | vinldo23-supply = <®_module_3v3>; | |
485 | vinldo4-supply = <®_module_3v3>; | |
486 | vinldo678-supply = <®_module_3v3>; | |
487 | vinldo9-supply = <®_module_3v3>; | |
fc9c713a LS |
488 | |
489 | regulators { | |
3647c7b8 MZ |
490 | reg_3v3_vsys: sys { |
491 | regulator-name = "VSYS_3.3V"; | |
fc9c713a LS |
492 | regulator-always-on; |
493 | }; | |
494 | ||
3647c7b8 MZ |
495 | sm0 { |
496 | regulator-name = "VDD_CORE_1.2V"; | |
c7ac2b7b SA |
497 | regulator-min-microvolt = <1200000>; |
498 | regulator-max-microvolt = <1200000>; | |
fc9c713a LS |
499 | regulator-always-on; |
500 | }; | |
501 | ||
3647c7b8 MZ |
502 | sm1 { |
503 | regulator-name = "VDD_CPU_1.0V"; | |
c7ac2b7b SA |
504 | regulator-min-microvolt = <1000000>; |
505 | regulator-max-microvolt = <1000000>; | |
fc9c713a LS |
506 | regulator-always-on; |
507 | }; | |
508 | ||
3647c7b8 MZ |
509 | reg_1v8_vdd_ddr2: sm2 { |
510 | regulator-name = "VDD_DDR2_1.8V"; | |
844a4f0d SA |
511 | regulator-min-microvolt = <1800000>; |
512 | regulator-max-microvolt = <1800000>; | |
fc9c713a LS |
513 | regulator-always-on; |
514 | }; | |
515 | ||
516 | /* LDO0 is not connected to anything */ | |
517 | ||
3647c7b8 MZ |
518 | /* |
519 | * +3.3V_ENABLE_N switching via FET: | |
520 | * AVDD_AUDIO_S and +3.3V | |
521 | * see also +3.3V fixed supply | |
522 | */ | |
523 | ldo1 { | |
524 | regulator-name = "AVDD_PLL_1.1V"; | |
fc9c713a LS |
525 | regulator-min-microvolt = <1100000>; |
526 | regulator-max-microvolt = <1100000>; | |
527 | regulator-always-on; | |
528 | }; | |
529 | ||
3647c7b8 MZ |
530 | ldo2 { |
531 | regulator-name = "VDD_RTC_1.2V"; | |
fc9c713a LS |
532 | regulator-min-microvolt = <1200000>; |
533 | regulator-max-microvolt = <1200000>; | |
534 | }; | |
535 | ||
536 | /* LDO3 is not connected to anything */ | |
537 | ||
3647c7b8 MZ |
538 | ldo4 { |
539 | regulator-name = "VDDIO_SYS_1.8V"; | |
fc9c713a LS |
540 | regulator-min-microvolt = <1800000>; |
541 | regulator-max-microvolt = <1800000>; | |
542 | regulator-always-on; | |
543 | }; | |
544 | ||
3647c7b8 MZ |
545 | /* Switched via FET from regular +3.3V */ |
546 | ldo5 { | |
547 | regulator-name = "+3.3V_USB"; | |
fc9c713a LS |
548 | regulator-min-microvolt = <3300000>; |
549 | regulator-max-microvolt = <3300000>; | |
550 | regulator-always-on; | |
551 | }; | |
552 | ||
3647c7b8 MZ |
553 | ldo6 { |
554 | regulator-name = "AVDD_VDAC_2.85V"; | |
c7ac2b7b SA |
555 | regulator-min-microvolt = <2850000>; |
556 | regulator-max-microvolt = <2850000>; | |
fc9c713a LS |
557 | }; |
558 | ||
3647c7b8 MZ |
559 | reg_3v3_avdd_hdmi: ldo7 { |
560 | regulator-name = "AVDD_HDMI_3.3V"; | |
fc9c713a LS |
561 | regulator-min-microvolt = <3300000>; |
562 | regulator-max-microvolt = <3300000>; | |
563 | }; | |
564 | ||
3647c7b8 MZ |
565 | reg_1v8_avdd_hdmi_pll: ldo8 { |
566 | regulator-name = "AVDD_HDMI_PLL_1.8V"; | |
fc9c713a LS |
567 | regulator-min-microvolt = <1800000>; |
568 | regulator-max-microvolt = <1800000>; | |
569 | }; | |
570 | ||
3647c7b8 MZ |
571 | ldo9 { |
572 | regulator-name = "VDDIO_RX_DDR_2.85V"; | |
fc9c713a LS |
573 | regulator-min-microvolt = <2850000>; |
574 | regulator-max-microvolt = <2850000>; | |
575 | regulator-always-on; | |
576 | }; | |
577 | ||
3647c7b8 MZ |
578 | ldo_rtc { |
579 | regulator-name = "VCC_BATT"; | |
fc9c713a LS |
580 | regulator-min-microvolt = <3300000>; |
581 | regulator-max-microvolt = <3300000>; | |
582 | regulator-always-on; | |
583 | }; | |
584 | }; | |
585 | }; | |
586 | ||
df2be1ae MZ |
587 | /* LM95245 temperature sensor */ |
588 | temp-sensor@4c { | |
fc9c713a LS |
589 | compatible = "national,lm95245"; |
590 | reg = <0x4c>; | |
591 | }; | |
592 | }; | |
593 | ||
58ecb23f | 594 | pmc@7000e400 { |
47d2d63b | 595 | nvidia,suspend-mode = <1>; |
a44a019d JL |
596 | nvidia,cpu-pwr-good-time = <5000>; |
597 | nvidia,cpu-pwr-off-time = <5000>; | |
598 | nvidia,core-pwr-good-time = <3845 3845>; | |
599 | nvidia,core-pwr-off-time = <3875>; | |
600 | nvidia,sys-clock-req-active-high; | |
d5178bb6 MZ |
601 | |
602 | /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */ | |
603 | i2c-thermtrip { | |
604 | nvidia,i2c-controller-id = <3>; | |
605 | nvidia,bus-addr = <0x34>; | |
606 | nvidia,reg-addr = <0x14>; | |
607 | nvidia,reg-data = <0x8>; | |
608 | }; | |
a44a019d JL |
609 | }; |
610 | ||
fc9c713a LS |
611 | memory-controller@7000f400 { |
612 | emc-table@83250 { | |
613 | reg = <83250>; | |
614 | compatible = "nvidia,tegra20-emc-table"; | |
615 | clock-frequency = <83250>; | |
616 | nvidia,emc-registers = <0x00000005 0x00000011 | |
617 | 0x00000004 0x00000002 0x00000004 0x00000004 | |
618 | 0x00000001 0x0000000a 0x00000002 0x00000002 | |
619 | 0x00000001 0x00000001 0x00000003 0x00000004 | |
620 | 0x00000003 0x00000009 0x0000000c 0x0000025f | |
621 | 0x00000000 0x00000003 0x00000003 0x00000002 | |
622 | 0x00000002 0x00000001 0x00000008 0x000000c8 | |
623 | 0x00000003 0x00000005 0x00000003 0x0000000c | |
624 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
625 | 0x00000000 0x00000000 0x00000083 0x00520006 | |
626 | 0x00000010 0x00000008 0x00000000 0x00000000 | |
627 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
628 | }; | |
629 | emc-table@133200 { | |
630 | reg = <133200>; | |
631 | compatible = "nvidia,tegra20-emc-table"; | |
632 | clock-frequency = <133200>; | |
633 | nvidia,emc-registers = <0x00000008 0x00000019 | |
634 | 0x00000006 0x00000002 0x00000004 0x00000004 | |
635 | 0x00000001 0x0000000a 0x00000002 0x00000002 | |
636 | 0x00000002 0x00000001 0x00000003 0x00000004 | |
637 | 0x00000003 0x00000009 0x0000000c 0x0000039f | |
638 | 0x00000000 0x00000003 0x00000003 0x00000002 | |
639 | 0x00000002 0x00000001 0x00000008 0x000000c8 | |
640 | 0x00000003 0x00000007 0x00000003 0x0000000c | |
641 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
642 | 0x00000000 0x00000000 0x00000083 0x00510006 | |
643 | 0x00000010 0x00000008 0x00000000 0x00000000 | |
644 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
645 | }; | |
646 | emc-table@166500 { | |
647 | reg = <166500>; | |
648 | compatible = "nvidia,tegra20-emc-table"; | |
649 | clock-frequency = <166500>; | |
650 | nvidia,emc-registers = <0x0000000a 0x00000021 | |
651 | 0x00000008 0x00000003 0x00000004 0x00000004 | |
652 | 0x00000002 0x0000000a 0x00000003 0x00000003 | |
653 | 0x00000002 0x00000001 0x00000003 0x00000004 | |
654 | 0x00000003 0x00000009 0x0000000c 0x000004df | |
655 | 0x00000000 0x00000003 0x00000003 0x00000003 | |
656 | 0x00000003 0x00000001 0x00000009 0x000000c8 | |
657 | 0x00000003 0x00000009 0x00000004 0x0000000c | |
658 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
659 | 0x00000000 0x00000000 0x00000083 0x004f0006 | |
660 | 0x00000010 0x00000008 0x00000000 0x00000000 | |
661 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
662 | }; | |
663 | emc-table@333000 { | |
664 | reg = <333000>; | |
665 | compatible = "nvidia,tegra20-emc-table"; | |
666 | clock-frequency = <333000>; | |
667 | nvidia,emc-registers = <0x00000014 0x00000041 | |
668 | 0x0000000f 0x00000005 0x00000004 0x00000005 | |
669 | 0x00000003 0x0000000a 0x00000005 0x00000005 | |
670 | 0x00000004 0x00000001 0x00000003 0x00000004 | |
671 | 0x00000003 0x00000009 0x0000000c 0x000009ff | |
672 | 0x00000000 0x00000003 0x00000003 0x00000005 | |
673 | 0x00000005 0x00000001 0x0000000e 0x000000c8 | |
674 | 0x00000003 0x00000011 0x00000006 0x0000000c | |
675 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
676 | 0x00000000 0x00000000 0x00000083 0x00380006 | |
677 | 0x00000010 0x00000008 0x00000000 0x00000000 | |
678 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
679 | }; | |
680 | }; | |
681 | ||
2287ef76 | 682 | /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */ |
fc9c713a LS |
683 | usb@c5004000 { |
684 | status = "okay"; | |
364ba104 MZ |
685 | #address-cells = <1>; |
686 | #size-cells = <0>; | |
687 | ||
688 | asix@1 { | |
689 | reg = <1>; | |
690 | local-mac-address = [00 00 00 00 00 00]; | |
691 | }; | |
9dffe3be VB |
692 | }; |
693 | ||
694 | usb-phy@c5004000 { | |
a1632ad3 | 695 | status = "okay"; |
035ae62d MZ |
696 | nvidia,phy-reset-gpio = |
697 | <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; | |
18e6ccef | 698 | vbus-supply = <®_lan_v_bus>; |
fc9c713a LS |
699 | }; |
700 | ||
7021d122 JL |
701 | clocks { |
702 | compatible = "simple-bus"; | |
703 | #address-cells = <1>; | |
704 | #size-cells = <0>; | |
705 | ||
58ecb23f | 706 | clk32k_in: clock@0 { |
7021d122 | 707 | compatible = "fixed-clock"; |
4ec2e601 | 708 | reg = <0>; |
7021d122 JL |
709 | #clock-cells = <0>; |
710 | clock-frequency = <32768>; | |
711 | }; | |
712 | }; | |
713 | ||
3647c7b8 MZ |
714 | reg_lan_v_bus: regulator-lan-v-bus { |
715 | compatible = "regulator-fixed"; | |
716 | regulator-name = "LAN_V_BUS"; | |
717 | regulator-min-microvolt = <5000000>; | |
718 | regulator-max-microvolt = <5000000>; | |
719 | enable-active-high; | |
720 | gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; | |
721 | }; | |
fc9c713a | 722 | |
3647c7b8 MZ |
723 | reg_module_3v3: regulator-module-3v3 { |
724 | compatible = "regulator-fixed"; | |
725 | regulator-name = "+V3.3"; | |
726 | regulator-min-microvolt = <3300000>; | |
727 | regulator-max-microvolt = <3300000>; | |
728 | regulator-always-on; | |
fc9c713a | 729 | }; |
57899053 SW |
730 | |
731 | sound { | |
732 | compatible = "nvidia,tegra-audio-wm9712-colibri_t20", | |
035ae62d | 733 | "nvidia,tegra-audio-wm9712"; |
ea60afb8 | 734 | nvidia,model = "Toradex Colibri T20"; |
57899053 SW |
735 | nvidia,audio-routing = |
736 | "Headphone", "HPOUTL", | |
737 | "Headphone", "HPOUTR", | |
738 | "LineIn", "LINEINL", | |
739 | "LineIn", "LINEINR", | |
740 | "Mic", "MIC1"; | |
57899053 | 741 | nvidia,ac97-controller = <&ac97>; |
57899053 SW |
742 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
743 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | |
744 | <&tegra_car TEGRA20_CLK_CDEV1>; | |
745 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
746 | }; | |
fc9c713a | 747 | }; |
0b51e73b MZ |
748 | |
749 | &gpio { | |
750 | lan-reset-n { | |
751 | gpio-hog; | |
752 | gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>; | |
753 | output-high; | |
754 | line-name = "LAN_RESET#"; | |
755 | }; | |
351c72c8 MZ |
756 | |
757 | /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ | |
758 | npwe { | |
759 | gpio-hog; | |
760 | gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; | |
761 | output-high; | |
762 | line-name = "Tri-state nPWE"; | |
763 | }; | |
764 | ||
765 | /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ | |
766 | rdnwr { | |
767 | gpio-hog; | |
768 | gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; | |
769 | output-low; | |
770 | line-name = "Not tri-state RDnWR"; | |
771 | }; | |
0b51e73b | 772 | }; |