projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: tegra: colibri_t20: remove phy-reset-gpio from controller node
[linux-2.6-block.git] / arch / arm / boot / dts / tegra20-colibri.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
1bd0bd49 2#include "tegra20.dtsi"
fc9c713a
LS		 3
4/ {
8ab11f80 5 model = "Toradex Colibri T20 256/512 MB";
fc9c713a
LS		 6 compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
7
48299769 8 memory@0 {
8ab11f80
KK		 9 /*
10 * Set memory to 256 MB to be safe as this could be used on
11 * 256 or 512 MB module. It is expected from bootloader
12 * to fix this up for 512 MB version.
13 */
14 reg = <0x00000000 0x10000000>;
fc9c713a
LS		 15 };
16
58ecb23f
SW		 17 host1x@50000000 {
18 hdmi@54280000 {
fc9c713a 19 nvidia,ddc-i2c-bus = <&i2c_ddc>;
e6800c21
MZ		 20 nvidia,hpd-gpio =
21 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
3647c7b8
MZ		 22 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
23 vdd-supply = <&reg_3v3_avdd_hdmi>;
fc9c713a
LS		 24 };
25 };
26
58ecb23f 27 pinmux@70000014 {
fc9c713a
LS		 28 pinctrl-names = "default";
29 pinctrl-0 = <&state_default>;
30
31 state_default: pinmux {
32 audio_refclk {
33 nvidia,pins = "cdev1";
34 nvidia,function = "plla_out";
ba4104e7
LD		 35 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
36 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 37 };
38 crt {
39 nvidia,pins = "crtp";
40 nvidia,function = "crt";
ba4104e7
LD		 41 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
42 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 43 };
44 dap3 {
45 nvidia,pins = "dap3";
46 nvidia,function = "dap3";
ba4104e7
LD		 47 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
48 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 49 };
50 displaya {
51 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
52 "ld4", "ld5", "ld6", "ld7", "ld8",
53 "ld9", "ld10", "ld11", "ld12", "ld13",
54 "ld14", "ld15", "ld16", "ld17",
55 "lhs", "lpw0", "lpw2", "lsc0",
56 "lsc1", "lsck", "lsda", "lspi", "lvs";
57 nvidia,function = "displaya";
ba4104e7 58 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 59 };
60 gpio_dte {
61 nvidia,pins = "dte";
62 nvidia,function = "rsvd1";
ba4104e7
LD		 63 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
64 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 65 };
66 gpio_gmi {
67 nvidia,pins = "ata", "atc", "atd", "ate",
68 "dap1", "dap2", "dap4", "gpu", "irrx",
69 "irtx", "spia", "spib", "spic";
70 nvidia,function = "gmi";
ba4104e7
LD		 71 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
72 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 73 };
74 gpio_pta {
75 nvidia,pins = "pta";
76 nvidia,function = "rsvd4";
ba4104e7
LD		 77 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 79 };
80 gpio_uac {
81 nvidia,pins = "uac";
82 nvidia,function = "rsvd2";
ba4104e7
LD		 83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 85 };
86 hdint {
87 nvidia,pins = "hdint";
88 nvidia,function = "hdmi";
ba4104e7 89 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 90 };
91 i2c1 {
92 nvidia,pins = "rm";
93 nvidia,function = "i2c1";
ba4104e7
LD		 94 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
95 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 96 };
97 i2c3 {
98 nvidia,pins = "dtf";
99 nvidia,function = "i2c3";
ba4104e7
LD		 100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
101 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 102 };
103 i2cddc {
104 nvidia,pins = "ddc";
105 nvidia,function = "i2c2";
ba4104e7
LD		 106 nvidia,pull = <TEGRA_PIN_PULL_UP>;
107 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 108 };
109 i2cp {
110 nvidia,pins = "i2cp";
111 nvidia,function = "i2cp";
ba4104e7
LD		 112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 114 };
115 irda {
116 nvidia,pins = "uad";
117 nvidia,function = "irda";
ba4104e7
LD		 118 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
119 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 120 };
121 nand {
122 nvidia,pins = "kbca", "kbcc", "kbcd",
123 "kbce", "kbcf";
124 nvidia,function = "nand";
ba4104e7
LD		 125 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 127 };
128 owc {
129 nvidia,pins = "owc";
130 nvidia,function = "owr";
ba4104e7
LD		 131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 133 };
134 pmc {
135 nvidia,pins = "pmc";
136 nvidia,function = "pwr_on";
ba4104e7 137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 138 };
139 pwm {
140 nvidia,pins = "sdb", "sdc", "sdd";
141 nvidia,function = "pwm";
ba4104e7 142 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 143 };
144 sdio4 {
145 nvidia,pins = "atb", "gma", "gme";
146 nvidia,function = "sdio4";
ba4104e7
LD		 147 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
148 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 149 };
150 spi1 {
151 nvidia,pins = "spid", "spie", "spif";
152 nvidia,function = "spi1";
ba4104e7
LD		 153 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
154 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 155 };
156 spi4 {
157 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
158 nvidia,function = "spi4";
ba4104e7
LD		 159 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
160 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 161 };
162 uarta {
163 nvidia,pins = "sdio1";
164 nvidia,function = "uarta";
ba4104e7
LD		 165 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 167 };
168 uartd {
169 nvidia,pins = "gmc";
170 nvidia,function = "uartd";
ba4104e7
LD		 171 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
172 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 173 };
174 ulpi {
175 nvidia,pins = "uaa", "uab", "uda";
176 nvidia,function = "ulpi";
ba4104e7
LD		 177 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
178 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 179 };
180 ulpi_refclk {
181 nvidia,pins = "cdev2";
182 nvidia,function = "pllp_out4";
ba4104e7
LD		 183 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
184 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 185 };
186 usb_gpio {
187 nvidia,pins = "spig", "spih";
188 nvidia,function = "spi2_alt";
ba4104e7
LD		 189 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
190 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a
LS		 191 };
192 vi {
193 nvidia,pins = "dta", "dtb", "dtc", "dtd";
194 nvidia,function = "vi";
ba4104e7
LD		 195 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
196 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 197 };
198 vi_sc {
199 nvidia,pins = "csus";
200 nvidia,function = "vi_sensor_clk";
ba4104e7
LD		 201 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a
LS		 203 };
204 };
205 };
206
57899053
SW		 207 ac97: ac97@70002000 {
208 status = "okay";
209 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
210 GPIO_ACTIVE_HIGH>;
211 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
212 GPIO_ACTIVE_HIGH>;
213 };
214
5def854e
SA		 215 nand-controller@70008000 {
216 status = "okay";
217
218 nand@0 {
219 reg = <0>;
220 #address-cells = <1>;
221 #size-cells = <1>;
222 nand-bus-width = <8>;
223 nand-on-flash-bbt;
224 nand-ecc-algo = "bch";
225 nand-is-boot-medium;
226 nand-ecc-maximize;
227 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
228 };
229 };
230
1c3389e6
MZ		 231 /*
232 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
233 * board)
234 */
fc9c713a
LS		 235 i2c@7000c000 {
236 clock-frequency = <400000>;
237 };
238
1c3389e6 239 /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
fc9c713a 240 i2c_ddc: i2c@7000c400 {
1c3389e6 241 clock-frequency = <10000>;
fc9c713a
LS		 242 };
243
1c3389e6 244 /* GEN2_I2C: unused */
fc9c713a 245
1c3389e6
MZ		 246 /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
247
248 /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
fc9c713a
LS		 249 i2c@7000d000 {
250 status = "okay";
1c3389e6 251 clock-frequency = <100000>;
fc9c713a
LS		 252
253 pmic: tps6586x@34 {
254 compatible = "ti,tps6586x";
255 reg = <0x34>;
6cecf916 256 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
fc9c713a
LS		 257
258 ti,system-power-controller;
259
260 #gpio-cells = <2>;
261 gpio-controller;
262
3647c7b8
MZ		 263 sys-supply = <&reg_module_3v3>;
264 vin-sm0-supply = <&reg_3v3_vsys>;
265 vin-sm1-supply = <&reg_3v3_vsys>;
266 vin-sm2-supply = <&reg_3v3_vsys>;
267 vinldo01-supply = <&reg_1v8_vdd_ddr2>;
268 vinldo23-supply = <&reg_module_3v3>;
269 vinldo4-supply = <&reg_module_3v3>;
270 vinldo678-supply = <&reg_module_3v3>;
271 vinldo9-supply = <&reg_module_3v3>;
fc9c713a
LS		 272
273 regulators {
3647c7b8
MZ		 274 reg_3v3_vsys: sys {
275 regulator-name = "VSYS_3.3V";
fc9c713a
LS		 276 regulator-always-on;
277 };
278
3647c7b8
MZ		 279 sm0 {
280 regulator-name = "VDD_CORE_1.2V";
c7ac2b7b
SA		 281 regulator-min-microvolt = <1200000>;
282 regulator-max-microvolt = <1200000>;
fc9c713a
LS		 283 regulator-always-on;
284 };
285
3647c7b8
MZ		 286 sm1 {
287 regulator-name = "VDD_CPU_1.0V";
c7ac2b7b
SA		 288 regulator-min-microvolt = <1000000>;
289 regulator-max-microvolt = <1000000>;
fc9c713a
LS		 290 regulator-always-on;
291 };
292
3647c7b8
MZ		 293 reg_1v8_vdd_ddr2: sm2 {
294 regulator-name = "VDD_DDR2_1.8V";
844a4f0d
SA		 295 regulator-min-microvolt = <1800000>;
296 regulator-max-microvolt = <1800000>;
fc9c713a
LS		 297 regulator-always-on;
298 };
299
300 /* LDO0 is not connected to anything */
301
3647c7b8
MZ		 302 /*
303 * +3.3V_ENABLE_N switching via FET:
304 * AVDD_AUDIO_S and +3.3V
305 * see also +3.3V fixed supply
306 */
307 ldo1 {
308 regulator-name = "AVDD_PLL_1.1V";
fc9c713a
LS		 309 regulator-min-microvolt = <1100000>;
310 regulator-max-microvolt = <1100000>;
311 regulator-always-on;
312 };
313
3647c7b8
MZ		 314 ldo2 {
315 regulator-name = "VDD_RTC_1.2V";
fc9c713a
LS		 316 regulator-min-microvolt = <1200000>;
317 regulator-max-microvolt = <1200000>;
318 };
319
320 /* LDO3 is not connected to anything */
321
3647c7b8
MZ		 322 ldo4 {
323 regulator-name = "VDDIO_SYS_1.8V";
fc9c713a
LS		 324 regulator-min-microvolt = <1800000>;
325 regulator-max-microvolt = <1800000>;
326 regulator-always-on;
327 };
328
3647c7b8
MZ		 329 /* Switched via FET from regular +3.3V */
330 ldo5 {
331 regulator-name = "+3.3V_USB";
fc9c713a
LS		 332 regulator-min-microvolt = <3300000>;
333 regulator-max-microvolt = <3300000>;
334 regulator-always-on;
335 };
336
3647c7b8
MZ		 337 ldo6 {
338 regulator-name = "AVDD_VDAC_2.85V";
c7ac2b7b
SA		 339 regulator-min-microvolt = <2850000>;
340 regulator-max-microvolt = <2850000>;
fc9c713a
LS		 341 };
342
3647c7b8
MZ		 343 reg_3v3_avdd_hdmi: ldo7 {
344 regulator-name = "AVDD_HDMI_3.3V";
fc9c713a
LS		 345 regulator-min-microvolt = <3300000>;
346 regulator-max-microvolt = <3300000>;
347 };
348
3647c7b8
MZ		 349 reg_1v8_avdd_hdmi_pll: ldo8 {
350 regulator-name = "AVDD_HDMI_PLL_1.8V";
fc9c713a
LS		 351 regulator-min-microvolt = <1800000>;
352 regulator-max-microvolt = <1800000>;
353 };
354
3647c7b8
MZ		 355 ldo9 {
356 regulator-name = "VDDIO_RX_DDR_2.85V";
fc9c713a
LS		 357 regulator-min-microvolt = <2850000>;
358 regulator-max-microvolt = <2850000>;
359 regulator-always-on;
360 };
361
3647c7b8
MZ		 362 ldo_rtc {
363 regulator-name = "VCC_BATT";
fc9c713a
LS		 364 regulator-min-microvolt = <3300000>;
365 regulator-max-microvolt = <3300000>;
366 regulator-always-on;
367 };
368 };
369 };
370
371 temperature-sensor@4c {
372 compatible = "national,lm95245";
373 reg = <0x4c>;
374 };
375 };
376
58ecb23f 377 pmc@7000e400 {
47d2d63b 378 nvidia,suspend-mode = <1>;
a44a019d
JL		 379 nvidia,cpu-pwr-good-time = <5000>;
380 nvidia,cpu-pwr-off-time = <5000>;
381 nvidia,core-pwr-good-time = <3845 3845>;
382 nvidia,core-pwr-off-time = <3875>;
383 nvidia,sys-clock-req-active-high;
384 };
385
fc9c713a
LS		 386 memory-controller@7000f400 {
387 emc-table@83250 {
388 reg = <83250>;
389 compatible = "nvidia,tegra20-emc-table";
390 clock-frequency = <83250>;
391 nvidia,emc-registers = <0x00000005 0x00000011
392 0x00000004 0x00000002 0x00000004 0x00000004
393 0x00000001 0x0000000a 0x00000002 0x00000002
394 0x00000001 0x00000001 0x00000003 0x00000004
395 0x00000003 0x00000009 0x0000000c 0x0000025f
396 0x00000000 0x00000003 0x00000003 0x00000002
397 0x00000002 0x00000001 0x00000008 0x000000c8
398 0x00000003 0x00000005 0x00000003 0x0000000c
399 0x00000002 0x00000000 0x00000000 0x00000002
400 0x00000000 0x00000000 0x00000083 0x00520006
401 0x00000010 0x00000008 0x00000000 0x00000000
402 0x00000000 0x00000000 0x00000000 0x00000000>;
403 };
404 emc-table@133200 {
405 reg = <133200>;
406 compatible = "nvidia,tegra20-emc-table";
407 clock-frequency = <133200>;
408 nvidia,emc-registers = <0x00000008 0x00000019
409 0x00000006 0x00000002 0x00000004 0x00000004
410 0x00000001 0x0000000a 0x00000002 0x00000002
411 0x00000002 0x00000001 0x00000003 0x00000004
412 0x00000003 0x00000009 0x0000000c 0x0000039f
413 0x00000000 0x00000003 0x00000003 0x00000002
414 0x00000002 0x00000001 0x00000008 0x000000c8
415 0x00000003 0x00000007 0x00000003 0x0000000c
416 0x00000002 0x00000000 0x00000000 0x00000002
417 0x00000000 0x00000000 0x00000083 0x00510006
418 0x00000010 0x00000008 0x00000000 0x00000000
419 0x00000000 0x00000000 0x00000000 0x00000000>;
420 };
421 emc-table@166500 {
422 reg = <166500>;
423 compatible = "nvidia,tegra20-emc-table";
424 clock-frequency = <166500>;
425 nvidia,emc-registers = <0x0000000a 0x00000021
426 0x00000008 0x00000003 0x00000004 0x00000004
427 0x00000002 0x0000000a 0x00000003 0x00000003
428 0x00000002 0x00000001 0x00000003 0x00000004
429 0x00000003 0x00000009 0x0000000c 0x000004df
430 0x00000000 0x00000003 0x00000003 0x00000003
431 0x00000003 0x00000001 0x00000009 0x000000c8
432 0x00000003 0x00000009 0x00000004 0x0000000c
433 0x00000002 0x00000000 0x00000000 0x00000002
434 0x00000000 0x00000000 0x00000083 0x004f0006
435 0x00000010 0x00000008 0x00000000 0x00000000
436 0x00000000 0x00000000 0x00000000 0x00000000>;
437 };
438 emc-table@333000 {
439 reg = <333000>;
440 compatible = "nvidia,tegra20-emc-table";
441 clock-frequency = <333000>;
442 nvidia,emc-registers = <0x00000014 0x00000041
443 0x0000000f 0x00000005 0x00000004 0x00000005
444 0x00000003 0x0000000a 0x00000005 0x00000005
445 0x00000004 0x00000001 0x00000003 0x00000004
446 0x00000003 0x00000009 0x0000000c 0x000009ff
447 0x00000000 0x00000003 0x00000003 0x00000005
448 0x00000005 0x00000001 0x0000000e 0x000000c8
449 0x00000003 0x00000011 0x00000006 0x0000000c
450 0x00000002 0x00000000 0x00000000 0x00000002
451 0x00000000 0x00000000 0x00000083 0x00380006
452 0x00000010 0x00000008 0x00000000 0x00000000
453 0x00000000 0x00000000 0x00000000 0x00000000>;
454 };
455 };
456
2287ef76 457 /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
fc9c713a
LS		 458 usb@c5004000 {
459 status = "okay";
364ba104
MZ		 460 #address-cells = <1>;
461 #size-cells = <0>;
462
463 asix@1 {
464 reg = <1>;
465 local-mac-address = [00 00 00 00 00 00];
466 };
9dffe3be
VB		 467 };
468
469 usb-phy@c5004000 {
a1632ad3 470 status = "okay";
3325f1bc
SW		 471 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
472 GPIO_ACTIVE_LOW>;
18e6ccef 473 vbus-supply = <&reg_lan_v_bus>;
fc9c713a
LS		 474 };
475
476 sdhci@c8000600 {
3325f1bc 477 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
fc9c713a
LS		 478 };
479
7021d122
JL		 480 clocks {
481 compatible = "simple-bus";
482 #address-cells = <1>;
483 #size-cells = <0>;
484
58ecb23f 485 clk32k_in: clock@0 {
7021d122 486 compatible = "fixed-clock";
4ec2e601 487 reg = <0>;
7021d122
JL		 488 #clock-cells = <0>;
489 clock-frequency = <32768>;
490 };
491 };
492
3647c7b8
MZ		 493 reg_lan_v_bus: regulator-lan-v-bus {
494 compatible = "regulator-fixed";
495 regulator-name = "LAN_V_BUS";
496 regulator-min-microvolt = <5000000>;
497 regulator-max-microvolt = <5000000>;
498 enable-active-high;
499 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
500 };
fc9c713a 501
3647c7b8
MZ		 502 reg_module_3v3: regulator-module-3v3 {
503 compatible = "regulator-fixed";
504 regulator-name = "+V3.3";
505 regulator-min-microvolt = <3300000>;
506 regulator-max-microvolt = <3300000>;
507 regulator-always-on;
fc9c713a 508 };
57899053
SW		 509
510 sound {
511 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
512 "nvidia,tegra-audio-wm9712";
513 nvidia,model = "Colibri T20 AC97 Audio";
514
515 nvidia,audio-routing =
516 "Headphone", "HPOUTL",
517 "Headphone", "HPOUTR",
518 "LineIn", "LINEINL",
519 "LineIn", "LINEINR",
520 "Mic", "MIC1";
521
522 nvidia,ac97-controller = <&ac97>;
523
524 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
525 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
526 <&tegra_car TEGRA20_CLK_CDEV1>;
527 clock-names = "pll_a", "pll_a_out0", "mclk";
528 };
fc9c713a 529};
Linux 6.x block layer and io_uring tree(s)