Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1bd0bd49 | 2 | #include "tegra20.dtsi" |
fc9c713a LS |
3 | |
4 | / { | |
8ab11f80 | 5 | model = "Toradex Colibri T20 256/512 MB"; |
fc9c713a LS |
6 | compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; |
7 | ||
48299769 | 8 | memory@0 { |
8ab11f80 KK |
9 | /* |
10 | * Set memory to 256 MB to be safe as this could be used on | |
11 | * 256 or 512 MB module. It is expected from bootloader | |
12 | * to fix this up for 512 MB version. | |
13 | */ | |
14 | reg = <0x00000000 0x10000000>; | |
fc9c713a LS |
15 | }; |
16 | ||
58ecb23f SW |
17 | host1x@50000000 { |
18 | hdmi@54280000 { | |
fc9c713a | 19 | nvidia,ddc-i2c-bus = <&i2c_ddc>; |
e6800c21 MZ |
20 | nvidia,hpd-gpio = |
21 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
22 | pll-supply = <&hdmi_pll_reg>; | |
23 | vdd-supply = <&hdmi_vdd_reg>; | |
fc9c713a LS |
24 | }; |
25 | }; | |
26 | ||
58ecb23f | 27 | pinmux@70000014 { |
fc9c713a LS |
28 | pinctrl-names = "default"; |
29 | pinctrl-0 = <&state_default>; | |
30 | ||
31 | state_default: pinmux { | |
32 | audio_refclk { | |
33 | nvidia,pins = "cdev1"; | |
34 | nvidia,function = "plla_out"; | |
ba4104e7 LD |
35 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
36 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a LS |
37 | }; |
38 | crt { | |
39 | nvidia,pins = "crtp"; | |
40 | nvidia,function = "crt"; | |
ba4104e7 LD |
41 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
42 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
43 | }; |
44 | dap3 { | |
45 | nvidia,pins = "dap3"; | |
46 | nvidia,function = "dap3"; | |
ba4104e7 LD |
47 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
48 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a LS |
49 | }; |
50 | displaya { | |
51 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", | |
52 | "ld4", "ld5", "ld6", "ld7", "ld8", | |
53 | "ld9", "ld10", "ld11", "ld12", "ld13", | |
54 | "ld14", "ld15", "ld16", "ld17", | |
55 | "lhs", "lpw0", "lpw2", "lsc0", | |
56 | "lsc1", "lsck", "lsda", "lspi", "lvs"; | |
57 | nvidia,function = "displaya"; | |
ba4104e7 | 58 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fc9c713a LS |
59 | }; |
60 | gpio_dte { | |
61 | nvidia,pins = "dte"; | |
62 | nvidia,function = "rsvd1"; | |
ba4104e7 LD |
63 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
64 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a LS |
65 | }; |
66 | gpio_gmi { | |
67 | nvidia,pins = "ata", "atc", "atd", "ate", | |
68 | "dap1", "dap2", "dap4", "gpu", "irrx", | |
69 | "irtx", "spia", "spib", "spic"; | |
70 | nvidia,function = "gmi"; | |
ba4104e7 LD |
71 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
72 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a LS |
73 | }; |
74 | gpio_pta { | |
75 | nvidia,pins = "pta"; | |
76 | nvidia,function = "rsvd4"; | |
ba4104e7 LD |
77 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
78 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a LS |
79 | }; |
80 | gpio_uac { | |
81 | nvidia,pins = "uac"; | |
82 | nvidia,function = "rsvd2"; | |
ba4104e7 LD |
83 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
84 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a LS |
85 | }; |
86 | hdint { | |
87 | nvidia,pins = "hdint"; | |
88 | nvidia,function = "hdmi"; | |
ba4104e7 | 89 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fc9c713a LS |
90 | }; |
91 | i2c1 { | |
92 | nvidia,pins = "rm"; | |
93 | nvidia,function = "i2c1"; | |
ba4104e7 LD |
94 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
95 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
96 | }; |
97 | i2c3 { | |
98 | nvidia,pins = "dtf"; | |
99 | nvidia,function = "i2c3"; | |
ba4104e7 LD |
100 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
101 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
102 | }; |
103 | i2cddc { | |
104 | nvidia,pins = "ddc"; | |
105 | nvidia,function = "i2c2"; | |
ba4104e7 LD |
106 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
107 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
108 | }; |
109 | i2cp { | |
110 | nvidia,pins = "i2cp"; | |
111 | nvidia,function = "i2cp"; | |
ba4104e7 LD |
112 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
113 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a LS |
114 | }; |
115 | irda { | |
116 | nvidia,pins = "uad"; | |
117 | nvidia,function = "irda"; | |
ba4104e7 LD |
118 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
119 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
120 | }; |
121 | nand { | |
122 | nvidia,pins = "kbca", "kbcc", "kbcd", | |
123 | "kbce", "kbcf"; | |
124 | nvidia,function = "nand"; | |
ba4104e7 LD |
125 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
126 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a LS |
127 | }; |
128 | owc { | |
129 | nvidia,pins = "owc"; | |
130 | nvidia,function = "owr"; | |
ba4104e7 LD |
131 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
132 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
133 | }; |
134 | pmc { | |
135 | nvidia,pins = "pmc"; | |
136 | nvidia,function = "pwr_on"; | |
ba4104e7 | 137 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
fc9c713a LS |
138 | }; |
139 | pwm { | |
140 | nvidia,pins = "sdb", "sdc", "sdd"; | |
141 | nvidia,function = "pwm"; | |
ba4104e7 | 142 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fc9c713a LS |
143 | }; |
144 | sdio4 { | |
145 | nvidia,pins = "atb", "gma", "gme"; | |
146 | nvidia,function = "sdio4"; | |
ba4104e7 LD |
147 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
148 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
149 | }; |
150 | spi1 { | |
151 | nvidia,pins = "spid", "spie", "spif"; | |
152 | nvidia,function = "spi1"; | |
ba4104e7 LD |
153 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
154 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
155 | }; |
156 | spi4 { | |
157 | nvidia,pins = "slxa", "slxc", "slxd", "slxk"; | |
158 | nvidia,function = "spi4"; | |
ba4104e7 LD |
159 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
160 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
161 | }; |
162 | uarta { | |
163 | nvidia,pins = "sdio1"; | |
164 | nvidia,function = "uarta"; | |
ba4104e7 LD |
165 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
166 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
167 | }; |
168 | uartd { | |
169 | nvidia,pins = "gmc"; | |
170 | nvidia,function = "uartd"; | |
ba4104e7 LD |
171 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
172 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
173 | }; |
174 | ulpi { | |
175 | nvidia,pins = "uaa", "uab", "uda"; | |
176 | nvidia,function = "ulpi"; | |
ba4104e7 LD |
177 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
178 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a LS |
179 | }; |
180 | ulpi_refclk { | |
181 | nvidia,pins = "cdev2"; | |
182 | nvidia,function = "pllp_out4"; | |
ba4104e7 LD |
183 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
184 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a LS |
185 | }; |
186 | usb_gpio { | |
187 | nvidia,pins = "spig", "spih"; | |
188 | nvidia,function = "spi2_alt"; | |
ba4104e7 LD |
189 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
190 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fc9c713a LS |
191 | }; |
192 | vi { | |
193 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; | |
194 | nvidia,function = "vi"; | |
ba4104e7 LD |
195 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
196 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
197 | }; |
198 | vi_sc { | |
199 | nvidia,pins = "csus"; | |
200 | nvidia,function = "vi_sensor_clk"; | |
ba4104e7 LD |
201 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
202 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
fc9c713a LS |
203 | }; |
204 | }; | |
205 | }; | |
206 | ||
57899053 SW |
207 | ac97: ac97@70002000 { |
208 | status = "okay"; | |
209 | nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) | |
210 | GPIO_ACTIVE_HIGH>; | |
211 | nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) | |
212 | GPIO_ACTIVE_HIGH>; | |
213 | }; | |
214 | ||
5def854e SA |
215 | nand-controller@70008000 { |
216 | status = "okay"; | |
217 | ||
218 | nand@0 { | |
219 | reg = <0>; | |
220 | #address-cells = <1>; | |
221 | #size-cells = <1>; | |
222 | nand-bus-width = <8>; | |
223 | nand-on-flash-bbt; | |
224 | nand-ecc-algo = "bch"; | |
225 | nand-is-boot-medium; | |
226 | nand-ecc-maximize; | |
227 | wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; | |
228 | }; | |
229 | }; | |
230 | ||
1c3389e6 MZ |
231 | /* |
232 | * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier | |
233 | * board) | |
234 | */ | |
fc9c713a LS |
235 | i2c@7000c000 { |
236 | clock-frequency = <400000>; | |
237 | }; | |
238 | ||
1c3389e6 | 239 | /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ |
fc9c713a | 240 | i2c_ddc: i2c@7000c400 { |
1c3389e6 | 241 | clock-frequency = <10000>; |
fc9c713a LS |
242 | }; |
243 | ||
1c3389e6 | 244 | /* GEN2_I2C: unused */ |
fc9c713a | 245 | |
1c3389e6 MZ |
246 | /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */ |
247 | ||
248 | /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */ | |
fc9c713a LS |
249 | i2c@7000d000 { |
250 | status = "okay"; | |
1c3389e6 | 251 | clock-frequency = <100000>; |
fc9c713a LS |
252 | |
253 | pmic: tps6586x@34 { | |
254 | compatible = "ti,tps6586x"; | |
255 | reg = <0x34>; | |
6cecf916 | 256 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
fc9c713a LS |
257 | |
258 | ti,system-power-controller; | |
259 | ||
260 | #gpio-cells = <2>; | |
261 | gpio-controller; | |
262 | ||
c7ac2b7b | 263 | sys-supply = <&vdd_3v3_reg>; |
fc9c713a LS |
264 | vin-sm0-supply = <&sys_reg>; |
265 | vin-sm1-supply = <&sys_reg>; | |
266 | vin-sm2-supply = <&sys_reg>; | |
267 | vinldo01-supply = <&sm2_reg>; | |
c7ac2b7b SA |
268 | vinldo23-supply = <&vdd_3v3_reg>; |
269 | vinldo4-supply = <&vdd_3v3_reg>; | |
270 | vinldo678-supply = <&vdd_3v3_reg>; | |
271 | vinldo9-supply = <&vdd_3v3_reg>; | |
fc9c713a LS |
272 | |
273 | regulators { | |
274 | #address-cells = <1>; | |
275 | #size-cells = <0>; | |
276 | ||
277 | sys_reg: regulator@0 { | |
278 | reg = <0>; | |
279 | regulator-compatible = "sys"; | |
280 | regulator-name = "vdd_sys"; | |
281 | regulator-always-on; | |
282 | }; | |
283 | ||
284 | regulator@1 { | |
285 | reg = <1>; | |
286 | regulator-compatible = "sm0"; | |
287 | regulator-name = "vdd_sm0,vdd_core"; | |
c7ac2b7b SA |
288 | regulator-min-microvolt = <1200000>; |
289 | regulator-max-microvolt = <1200000>; | |
fc9c713a LS |
290 | regulator-always-on; |
291 | }; | |
292 | ||
293 | regulator@2 { | |
294 | reg = <2>; | |
295 | regulator-compatible = "sm1"; | |
296 | regulator-name = "vdd_sm1,vdd_cpu"; | |
c7ac2b7b SA |
297 | regulator-min-microvolt = <1000000>; |
298 | regulator-max-microvolt = <1000000>; | |
fc9c713a LS |
299 | regulator-always-on; |
300 | }; | |
301 | ||
302 | sm2_reg: regulator@3 { | |
303 | reg = <3>; | |
304 | regulator-compatible = "sm2"; | |
305 | regulator-name = "vdd_sm2,vin_ldo*"; | |
844a4f0d SA |
306 | regulator-min-microvolt = <1800000>; |
307 | regulator-max-microvolt = <1800000>; | |
fc9c713a LS |
308 | regulator-always-on; |
309 | }; | |
310 | ||
311 | /* LDO0 is not connected to anything */ | |
312 | ||
313 | regulator@5 { | |
314 | reg = <5>; | |
315 | regulator-compatible = "ldo1"; | |
316 | regulator-name = "vdd_ldo1,avdd_pll*"; | |
317 | regulator-min-microvolt = <1100000>; | |
318 | regulator-max-microvolt = <1100000>; | |
319 | regulator-always-on; | |
320 | }; | |
321 | ||
322 | regulator@6 { | |
323 | reg = <6>; | |
324 | regulator-compatible = "ldo2"; | |
325 | regulator-name = "vdd_ldo2,vdd_rtc"; | |
326 | regulator-min-microvolt = <1200000>; | |
327 | regulator-max-microvolt = <1200000>; | |
328 | }; | |
329 | ||
330 | /* LDO3 is not connected to anything */ | |
331 | ||
332 | regulator@8 { | |
333 | reg = <8>; | |
334 | regulator-compatible = "ldo4"; | |
335 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; | |
336 | regulator-min-microvolt = <1800000>; | |
337 | regulator-max-microvolt = <1800000>; | |
338 | regulator-always-on; | |
339 | }; | |
340 | ||
341 | ldo5_reg: regulator@9 { | |
342 | reg = <9>; | |
343 | regulator-compatible = "ldo5"; | |
344 | regulator-name = "vdd_ldo5,vdd_fuse"; | |
345 | regulator-min-microvolt = <3300000>; | |
346 | regulator-max-microvolt = <3300000>; | |
347 | regulator-always-on; | |
348 | }; | |
349 | ||
350 | regulator@10 { | |
351 | reg = <10>; | |
352 | regulator-compatible = "ldo6"; | |
353 | regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; | |
c7ac2b7b SA |
354 | regulator-min-microvolt = <2850000>; |
355 | regulator-max-microvolt = <2850000>; | |
fc9c713a LS |
356 | }; |
357 | ||
358 | hdmi_vdd_reg: regulator@11 { | |
359 | reg = <11>; | |
360 | regulator-compatible = "ldo7"; | |
361 | regulator-name = "vdd_ldo7,avdd_hdmi"; | |
362 | regulator-min-microvolt = <3300000>; | |
363 | regulator-max-microvolt = <3300000>; | |
364 | }; | |
365 | ||
366 | hdmi_pll_reg: regulator@12 { | |
367 | reg = <12>; | |
368 | regulator-compatible = "ldo8"; | |
369 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; | |
370 | regulator-min-microvolt = <1800000>; | |
371 | regulator-max-microvolt = <1800000>; | |
372 | }; | |
373 | ||
374 | regulator@13 { | |
375 | reg = <13>; | |
376 | regulator-compatible = "ldo9"; | |
377 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; | |
378 | regulator-min-microvolt = <2850000>; | |
379 | regulator-max-microvolt = <2850000>; | |
380 | regulator-always-on; | |
381 | }; | |
382 | ||
383 | regulator@14 { | |
384 | reg = <14>; | |
385 | regulator-compatible = "ldo_rtc"; | |
386 | regulator-name = "vdd_rtc_out,vdd_cell"; | |
387 | regulator-min-microvolt = <3300000>; | |
388 | regulator-max-microvolt = <3300000>; | |
389 | regulator-always-on; | |
390 | }; | |
391 | }; | |
392 | }; | |
393 | ||
394 | temperature-sensor@4c { | |
395 | compatible = "national,lm95245"; | |
396 | reg = <0x4c>; | |
397 | }; | |
398 | }; | |
399 | ||
58ecb23f | 400 | pmc@7000e400 { |
47d2d63b | 401 | nvidia,suspend-mode = <1>; |
a44a019d JL |
402 | nvidia,cpu-pwr-good-time = <5000>; |
403 | nvidia,cpu-pwr-off-time = <5000>; | |
404 | nvidia,core-pwr-good-time = <3845 3845>; | |
405 | nvidia,core-pwr-off-time = <3875>; | |
406 | nvidia,sys-clock-req-active-high; | |
407 | }; | |
408 | ||
fc9c713a LS |
409 | memory-controller@7000f400 { |
410 | emc-table@83250 { | |
411 | reg = <83250>; | |
412 | compatible = "nvidia,tegra20-emc-table"; | |
413 | clock-frequency = <83250>; | |
414 | nvidia,emc-registers = <0x00000005 0x00000011 | |
415 | 0x00000004 0x00000002 0x00000004 0x00000004 | |
416 | 0x00000001 0x0000000a 0x00000002 0x00000002 | |
417 | 0x00000001 0x00000001 0x00000003 0x00000004 | |
418 | 0x00000003 0x00000009 0x0000000c 0x0000025f | |
419 | 0x00000000 0x00000003 0x00000003 0x00000002 | |
420 | 0x00000002 0x00000001 0x00000008 0x000000c8 | |
421 | 0x00000003 0x00000005 0x00000003 0x0000000c | |
422 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
423 | 0x00000000 0x00000000 0x00000083 0x00520006 | |
424 | 0x00000010 0x00000008 0x00000000 0x00000000 | |
425 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
426 | }; | |
427 | emc-table@133200 { | |
428 | reg = <133200>; | |
429 | compatible = "nvidia,tegra20-emc-table"; | |
430 | clock-frequency = <133200>; | |
431 | nvidia,emc-registers = <0x00000008 0x00000019 | |
432 | 0x00000006 0x00000002 0x00000004 0x00000004 | |
433 | 0x00000001 0x0000000a 0x00000002 0x00000002 | |
434 | 0x00000002 0x00000001 0x00000003 0x00000004 | |
435 | 0x00000003 0x00000009 0x0000000c 0x0000039f | |
436 | 0x00000000 0x00000003 0x00000003 0x00000002 | |
437 | 0x00000002 0x00000001 0x00000008 0x000000c8 | |
438 | 0x00000003 0x00000007 0x00000003 0x0000000c | |
439 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
440 | 0x00000000 0x00000000 0x00000083 0x00510006 | |
441 | 0x00000010 0x00000008 0x00000000 0x00000000 | |
442 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
443 | }; | |
444 | emc-table@166500 { | |
445 | reg = <166500>; | |
446 | compatible = "nvidia,tegra20-emc-table"; | |
447 | clock-frequency = <166500>; | |
448 | nvidia,emc-registers = <0x0000000a 0x00000021 | |
449 | 0x00000008 0x00000003 0x00000004 0x00000004 | |
450 | 0x00000002 0x0000000a 0x00000003 0x00000003 | |
451 | 0x00000002 0x00000001 0x00000003 0x00000004 | |
452 | 0x00000003 0x00000009 0x0000000c 0x000004df | |
453 | 0x00000000 0x00000003 0x00000003 0x00000003 | |
454 | 0x00000003 0x00000001 0x00000009 0x000000c8 | |
455 | 0x00000003 0x00000009 0x00000004 0x0000000c | |
456 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
457 | 0x00000000 0x00000000 0x00000083 0x004f0006 | |
458 | 0x00000010 0x00000008 0x00000000 0x00000000 | |
459 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
460 | }; | |
461 | emc-table@333000 { | |
462 | reg = <333000>; | |
463 | compatible = "nvidia,tegra20-emc-table"; | |
464 | clock-frequency = <333000>; | |
465 | nvidia,emc-registers = <0x00000014 0x00000041 | |
466 | 0x0000000f 0x00000005 0x00000004 0x00000005 | |
467 | 0x00000003 0x0000000a 0x00000005 0x00000005 | |
468 | 0x00000004 0x00000001 0x00000003 0x00000004 | |
469 | 0x00000003 0x00000009 0x0000000c 0x000009ff | |
470 | 0x00000000 0x00000003 0x00000003 0x00000005 | |
471 | 0x00000005 0x00000001 0x0000000e 0x000000c8 | |
472 | 0x00000003 0x00000011 0x00000006 0x0000000c | |
473 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
474 | 0x00000000 0x00000000 0x00000083 0x00380006 | |
475 | 0x00000010 0x00000008 0x00000000 0x00000000 | |
476 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
477 | }; | |
478 | }; | |
479 | ||
fc9c713a LS |
480 | usb@c5004000 { |
481 | status = "okay"; | |
3325f1bc SW |
482 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
483 | GPIO_ACTIVE_LOW>; | |
364ba104 MZ |
484 | #address-cells = <1>; |
485 | #size-cells = <0>; | |
486 | ||
487 | asix@1 { | |
488 | reg = <1>; | |
489 | local-mac-address = [00 00 00 00 00 00]; | |
490 | }; | |
9dffe3be VB |
491 | }; |
492 | ||
493 | usb-phy@c5004000 { | |
a1632ad3 | 494 | status = "okay"; |
3325f1bc SW |
495 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
496 | GPIO_ACTIVE_LOW>; | |
fc9c713a LS |
497 | }; |
498 | ||
499 | sdhci@c8000600 { | |
3325f1bc | 500 | cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; |
fc9c713a LS |
501 | }; |
502 | ||
7021d122 JL |
503 | clocks { |
504 | compatible = "simple-bus"; | |
505 | #address-cells = <1>; | |
506 | #size-cells = <0>; | |
507 | ||
58ecb23f | 508 | clk32k_in: clock@0 { |
7021d122 | 509 | compatible = "fixed-clock"; |
4ec2e601 | 510 | reg = <0>; |
7021d122 JL |
511 | #clock-cells = <0>; |
512 | clock-frequency = <32768>; | |
513 | }; | |
514 | }; | |
515 | ||
fc9c713a LS |
516 | regulators { |
517 | compatible = "simple-bus"; | |
518 | #address-cells = <1>; | |
519 | #size-cells = <0>; | |
520 | ||
c7ac2b7b | 521 | vdd_3v3_reg: regulator@100 { |
fc9c713a LS |
522 | compatible = "regulator-fixed"; |
523 | reg = <100>; | |
c7ac2b7b SA |
524 | regulator-name = "vdd_3v3"; |
525 | regulator-min-microvolt = <3300000>; | |
526 | regulator-max-microvolt = <3300000>; | |
fc9c713a LS |
527 | regulator-always-on; |
528 | }; | |
529 | ||
530 | regulator@101 { | |
531 | compatible = "regulator-fixed"; | |
532 | reg = <101>; | |
533 | regulator-name = "internal_usb"; | |
534 | regulator-min-microvolt = <5000000>; | |
535 | regulator-max-microvolt = <5000000>; | |
536 | enable-active-high; | |
537 | regulator-boot-on; | |
538 | regulator-always-on; | |
3325f1bc | 539 | gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; |
fc9c713a LS |
540 | }; |
541 | }; | |
57899053 SW |
542 | |
543 | sound { | |
544 | compatible = "nvidia,tegra-audio-wm9712-colibri_t20", | |
545 | "nvidia,tegra-audio-wm9712"; | |
546 | nvidia,model = "Colibri T20 AC97 Audio"; | |
547 | ||
548 | nvidia,audio-routing = | |
549 | "Headphone", "HPOUTL", | |
550 | "Headphone", "HPOUTR", | |
551 | "LineIn", "LINEINL", | |
552 | "LineIn", "LINEINR", | |
553 | "Mic", "MIC1"; | |
554 | ||
555 | nvidia,ac97-controller = <&ac97>; | |
556 | ||
557 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, | |
558 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | |
559 | <&tegra_car TEGRA20_CLK_CDEV1>; | |
560 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
561 | }; | |
fc9c713a | 562 | }; |