[linux-block.git] / arch / arm / boot / dts / tegra20-colibri-512.dtsi

// SPDX-License-Identifier: GPL-2.0
#include "tegra20.dtsi"

/ {
	model = "Toradex Colibri T20 512MB";
	compatible = "toradex,colibri_t20-512", "nvidia,tegra20";

	aliases {
		rtc0 = "/i2c@7000d000/tps6586x@34";
		rtc1 = "/rtc@7000e000";
	};

	memory {
		reg = <0x00000000 0x20000000>;
	};

	host1x@50000000 {
		hdmi@54280000 {
			vdd-supply = <&hdmi_vdd_reg>;
			pll-supply = <&hdmi_pll_reg>;

			nvidia,ddc-i2c-bus = <&i2c_ddc>;
			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
				GPIO_ACTIVE_HIGH>;
		};
	};

	pinmux@70000014 {
		pinctrl-names = "default";
		pinctrl-0 = <&state_default>;

		state_default: pinmux {
			audio_refclk {
				nvidia,pins = "cdev1";
				nvidia,function = "plla_out";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			crt {
				nvidia,pins = "crtp";
				nvidia,function = "crt";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			dap3 {
				nvidia,pins = "dap3";
				nvidia,function = "dap3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			displaya {
				nvidia,pins = "ld0", "ld1", "ld2", "ld3",
					"ld4", "ld5", "ld6", "ld7", "ld8",
					"ld9", "ld10", "ld11", "ld12", "ld13",
					"ld14", "ld15", "ld16", "ld17",
					"lhs", "lpw0", "lpw2", "lsc0",
					"lsc1", "lsck", "lsda", "lspi", "lvs";
				nvidia,function = "displaya";
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			gpio_dte {
				nvidia,pins = "dte";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			gpio_gmi {
				nvidia,pins = "ata", "atc", "atd", "ate",
					"dap1", "dap2", "dap4", "gpu", "irrx",
					"irtx", "spia", "spib", "spic";
				nvidia,function = "gmi";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			gpio_pta {
				nvidia,pins = "pta";
				nvidia,function = "rsvd4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			gpio_uac {
				nvidia,pins = "uac";
				nvidia,function = "rsvd2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			hdint {
				nvidia,pins = "hdint";
				nvidia,function = "hdmi";
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			i2c1 {
				nvidia,pins = "rm";
				nvidia,function = "i2c1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			i2c3 {
				nvidia,pins = "dtf";
				nvidia,function = "i2c3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			i2cddc {
				nvidia,pins = "ddc";
				nvidia,function = "i2c2";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			i2cp {
				nvidia,pins = "i2cp";
				nvidia,function = "i2cp";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			irda {
				nvidia,pins = "uad";
				nvidia,function = "irda";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			nand {
				nvidia,pins = "kbca", "kbcc", "kbcd",
					"kbce", "kbcf";
				nvidia,function = "nand";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			owc {
				nvidia,pins = "owc";
				nvidia,function = "owr";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			pmc {
				nvidia,pins = "pmc";
				nvidia,function = "pwr_on";
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			pwm {
				nvidia,pins = "sdb", "sdc", "sdd";
				nvidia,function = "pwm";
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			sdio4 {
				nvidia,pins = "atb", "gma", "gme";
				nvidia,function = "sdio4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			spi1 {
				nvidia,pins = "spid", "spie", "spif";
				nvidia,function = "spi1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			spi4 {
				nvidia,pins = "slxa", "slxc", "slxd", "slxk";
				nvidia,function = "spi4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			uarta {
				nvidia,pins = "sdio1";
				nvidia,function = "uarta";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			uartd {
				nvidia,pins = "gmc";
				nvidia,function = "uartd";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			ulpi {
				nvidia,pins = "uaa", "uab", "uda";
				nvidia,function = "ulpi";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			ulpi_refclk {
				nvidia,pins = "cdev2";
				nvidia,function = "pllp_out4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			usb_gpio {
				nvidia,pins = "spig", "spih";
				nvidia,function = "spi2_alt";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			vi {
				nvidia,pins = "dta", "dtb", "dtc", "dtd";
				nvidia,function = "vi";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			vi_sc {
				nvidia,pins = "csus";
				nvidia,function = "vi_sensor_clk";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
		};
	};

	ac97: ac97@70002000 {
		status = "okay";
		nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
			GPIO_ACTIVE_HIGH>;
		nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
			GPIO_ACTIVE_HIGH>;
	};

	i2c@7000c000 {
		clock-frequency = <400000>;
	};

	i2c_ddc: i2c@7000c400 {
		clock-frequency = <100000>;
	};

	i2c@7000c500 {
		clock-frequency = <400000>;
	};

	i2c@7000d000 {
		status = "okay";
		clock-frequency = <400000>;

		pmic: tps6586x@34 {
			compatible = "ti,tps6586x";
			reg = <0x34>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

			ti,system-power-controller;

			#gpio-cells = <2>;
			gpio-controller;

			sys-supply = <&vdd_3v3_reg>;
			vin-sm0-supply = <&sys_reg>;
			vin-sm1-supply = <&sys_reg>;
			vin-sm2-supply = <&sys_reg>;
			vinldo01-supply = <&sm2_reg>;
			vinldo23-supply = <&vdd_3v3_reg>;
			vinldo4-supply = <&vdd_3v3_reg>;
			vinldo678-supply = <&vdd_3v3_reg>;
			vinldo9-supply = <&vdd_3v3_reg>;

			regulators {
				#address-cells = <1>;
				#size-cells = <0>;

				sys_reg: regulator@0 {
					reg = <0>;
					regulator-compatible = "sys";
					regulator-name = "vdd_sys";
					regulator-always-on;
				};

				regulator@1 {
					reg = <1>;
					regulator-compatible = "sm0";
					regulator-name = "vdd_sm0,vdd_core";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				regulator@2 {
					reg = <2>;
					regulator-compatible = "sm1";
					regulator-name = "vdd_sm1,vdd_cpu";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
					regulator-always-on;
				};

				sm2_reg: regulator@3 {
					reg = <3>;
					regulator-compatible = "sm2";
					regulator-name = "vdd_sm2,vin_ldo*";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
				};

				/* LDO0 is not connected to anything */

				regulator@5 {
					reg = <5>;
					regulator-compatible = "ldo1";
					regulator-name = "vdd_ldo1,avdd_pll*";
					regulator-min-microvolt = <1100000>;
					regulator-max-microvolt = <1100000>;
					regulator-always-on;
				};

				regulator@6 {
					reg = <6>;
					regulator-compatible = "ldo2";
					regulator-name = "vdd_ldo2,vdd_rtc";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
				};

				/* LDO3 is not connected to anything */

				regulator@8 {
					reg = <8>;
					regulator-compatible = "ldo4";
					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
				};

				ldo5_reg: regulator@9 {
					reg = <9>;
					regulator-compatible = "ldo5";
					regulator-name = "vdd_ldo5,vdd_fuse";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};

				regulator@10 {
					reg = <10>;
					regulator-compatible = "ldo6";
					regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
					regulator-min-microvolt = <2850000>;
					regulator-max-microvolt = <2850000>;
				};

				hdmi_vdd_reg: regulator@11 {
					reg = <11>;
					regulator-compatible = "ldo7";
					regulator-name = "vdd_ldo7,avdd_hdmi";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
				};

				hdmi_pll_reg: regulator@12 {
					reg = <12>;
					regulator-compatible = "ldo8";
					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
				};

				regulator@13 {
					reg = <13>;
					regulator-compatible = "ldo9";
					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
					regulator-min-microvolt = <2850000>;
					regulator-max-microvolt = <2850000>;
					regulator-always-on;
				};

				regulator@14 {
					reg = <14>;
					regulator-compatible = "ldo_rtc";
					regulator-name = "vdd_rtc_out,vdd_cell";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};
			};
		};

		temperature-sensor@4c {
			compatible = "national,lm95245";
			reg = <0x4c>;
		};
	};

	pmc@7000e400 {
		nvidia,suspend-mode = <1>;
		nvidia,cpu-pwr-good-time = <5000>;
		nvidia,cpu-pwr-off-time = <5000>;
		nvidia,core-pwr-good-time = <3845 3845>;
		nvidia,core-pwr-off-time = <3875>;
		nvidia,sys-clock-req-active-high;
	};

	memory-controller@7000f400 {
		emc-table@83250 {
			reg = <83250>;
			compatible = "nvidia,tegra20-emc-table";
			clock-frequency = <83250>;
			nvidia,emc-registers =   <0x00000005 0x00000011
				0x00000004 0x00000002 0x00000004 0x00000004
				0x00000001 0x0000000a 0x00000002 0x00000002
				0x00000001 0x00000001 0x00000003 0x00000004
				0x00000003 0x00000009 0x0000000c 0x0000025f
				0x00000000 0x00000003 0x00000003 0x00000002
				0x00000002 0x00000001 0x00000008 0x000000c8
				0x00000003 0x00000005 0x00000003 0x0000000c
				0x00000002 0x00000000 0x00000000 0x00000002
				0x00000000 0x00000000 0x00000083 0x00520006
				0x00000010 0x00000008 0x00000000 0x00000000
				0x00000000 0x00000000 0x00000000 0x00000000>;
		};
		emc-table@133200 {
			reg = <133200>;
			compatible = "nvidia,tegra20-emc-table";
			clock-frequency = <133200>;
			nvidia,emc-registers =   <0x00000008 0x00000019
				0x00000006 0x00000002 0x00000004 0x00000004
				0x00000001 0x0000000a 0x00000002 0x00000002
				0x00000002 0x00000001 0x00000003 0x00000004
				0x00000003 0x00000009 0x0000000c 0x0000039f
				0x00000000 0x00000003 0x00000003 0x00000002
				0x00000002 0x00000001 0x00000008 0x000000c8
				0x00000003 0x00000007 0x00000003 0x0000000c
				0x00000002 0x00000000 0x00000000 0x00000002
				0x00000000 0x00000000 0x00000083 0x00510006
				0x00000010 0x00000008 0x00000000 0x00000000
				0x00000000 0x00000000 0x00000000 0x00000000>;
		};
		emc-table@166500 {
			reg = <166500>;
			compatible = "nvidia,tegra20-emc-table";
			clock-frequency = <166500>;
			nvidia,emc-registers =   <0x0000000a 0x00000021
				0x00000008 0x00000003 0x00000004 0x00000004
				0x00000002 0x0000000a 0x00000003 0x00000003
				0x00000002 0x00000001 0x00000003 0x00000004
				0x00000003 0x00000009 0x0000000c 0x000004df
				0x00000000 0x00000003 0x00000003 0x00000003
				0x00000003 0x00000001 0x00000009 0x000000c8
				0x00000003 0x00000009 0x00000004 0x0000000c
				0x00000002 0x00000000 0x00000000 0x00000002
				0x00000000 0x00000000 0x00000083 0x004f0006
				0x00000010 0x00000008 0x00000000 0x00000000
				0x00000000 0x00000000 0x00000000 0x00000000>;
		};
		emc-table@333000 {
			reg = <333000>;
			compatible = "nvidia,tegra20-emc-table";
			clock-frequency = <333000>;
			nvidia,emc-registers =   <0x00000014 0x00000041
				0x0000000f 0x00000005 0x00000004 0x00000005
				0x00000003 0x0000000a 0x00000005 0x00000005
				0x00000004 0x00000001 0x00000003 0x00000004
				0x00000003 0x00000009 0x0000000c 0x000009ff
				0x00000000 0x00000003 0x00000003 0x00000005
				0x00000005 0x00000001 0x0000000e 0x000000c8
				0x00000003 0x00000011 0x00000006 0x0000000c
				0x00000002 0x00000000 0x00000000 0x00000002
				0x00000000 0x00000000 0x00000083 0x00380006
				0x00000010 0x00000008 0x00000000 0x00000000
				0x00000000 0x00000000 0x00000000 0x00000000>;
		};
	};

	usb@c5004000 {
		status = "okay";
		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
			GPIO_ACTIVE_LOW>;
	};

	usb-phy@c5004000 {
		status = "okay";
		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
			GPIO_ACTIVE_LOW>;
	};

	sdhci@c8000600 {
		cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		clk32k_in: clock@0 {
			compatible = "fixed-clock";
			reg = <0>;
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		vdd_3v3_reg: regulator@100 {
			compatible = "regulator-fixed";
			reg = <100>;
			regulator-name = "vdd_3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		regulator@101 {
			compatible = "regulator-fixed";
			reg = <101>;
			regulator-name = "internal_usb";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-boot-on;
			regulator-always-on;
			gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
		};
	};

	sound {
		compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
			         "nvidia,tegra-audio-wm9712";
		nvidia,model = "Colibri T20 AC97 Audio";

		nvidia,audio-routing =
			"Headphone", "HPOUTL",
			"Headphone", "HPOUTR",
			"LineIn", "LINEINL",
			"LineIn", "LINEINR",
			"Mic", "MIC1";

		nvidia,ac97-controller = <&ac97>;

		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
			 <&tegra_car TEGRA20_CLK_CDEV1>;
		clock-names = "pll_a", "pll_a_out0", "mclk";
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1bd0bd49	2	#include "tegra20.dtsi"
fc9c713a LS	3
	4	/ {
	5	model = "Toradex Colibri T20 512MB";
	6	compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
	7
553c0a20 SW	8	aliases {
	9	rtc0 = "/i2c@7000d000/tps6586x@34";
	10	rtc1 = "/rtc@7000e000";
	11	};
	12
fc9c713a LS	13	memory {
	14	reg = <0x00000000 0x20000000>;
	15	};
	16
58ecb23f SW	17	host1x@50000000 {
58ecb23f SW	18	hdmi@54280000 {
fc9c713a LS	19	vdd-supply = <&hdmi_vdd_reg>;
	20	pll-supply = <&hdmi_pll_reg>;
	21
	22	nvidia,ddc-i2c-bus = <&i2c_ddc>;
3325f1bc SW	23	nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
3325f1bc SW	24	GPIO_ACTIVE_HIGH>;
fc9c713a LS	25	};
	26	};
	27
58ecb23f	28	pinmux@70000014 {
fc9c713a LS	29	pinctrl-names = "default";
	30	pinctrl-0 = <&state_default>;
	31
	32	state_default: pinmux {
	33	audio_refclk {
	34	nvidia,pins = "cdev1";
	35	nvidia,function = "plla_out";
ba4104e7 LD	36	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	37	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	38	};
	39	crt {
	40	nvidia,pins = "crtp";
	41	nvidia,function = "crt";
ba4104e7 LD	42	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	43	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	44	};
	45	dap3 {
	46	nvidia,pins = "dap3";
	47	nvidia,function = "dap3";
ba4104e7 LD	48	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	49	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	50	};
	51	displaya {
	52	nvidia,pins = "ld0", "ld1", "ld2", "ld3",
	53	"ld4", "ld5", "ld6", "ld7", "ld8",
	54	"ld9", "ld10", "ld11", "ld12", "ld13",
	55	"ld14", "ld15", "ld16", "ld17",
	56	"lhs", "lpw0", "lpw2", "lsc0",
	57	"lsc1", "lsck", "lsda", "lspi", "lvs";
	58	nvidia,function = "displaya";
ba4104e7	59	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	60	};
	61	gpio_dte {
	62	nvidia,pins = "dte";
	63	nvidia,function = "rsvd1";
ba4104e7 LD	64	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	65	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	66	};
	67	gpio_gmi {
	68	nvidia,pins = "ata", "atc", "atd", "ate",
	69	"dap1", "dap2", "dap4", "gpu", "irrx",
	70	"irtx", "spia", "spib", "spic";
	71	nvidia,function = "gmi";
ba4104e7 LD	72	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	73	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	74	};
	75	gpio_pta {
	76	nvidia,pins = "pta";
	77	nvidia,function = "rsvd4";
ba4104e7 LD	78	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	79	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	80	};
	81	gpio_uac {
	82	nvidia,pins = "uac";
	83	nvidia,function = "rsvd2";
ba4104e7 LD	84	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	85	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	86	};
	87	hdint {
	88	nvidia,pins = "hdint";
	89	nvidia,function = "hdmi";
ba4104e7	90	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	91	};
	92	i2c1 {
	93	nvidia,pins = "rm";
	94	nvidia,function = "i2c1";
ba4104e7 LD	95	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	96	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	97	};
	98	i2c3 {
	99	nvidia,pins = "dtf";
	100	nvidia,function = "i2c3";
ba4104e7 LD	101	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	102	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	103	};
	104	i2cddc {
	105	nvidia,pins = "ddc";
	106	nvidia,function = "i2c2";
ba4104e7 LD	107	nvidia,pull = <TEGRA_PIN_PULL_UP>;
ba4104e7 LD	108	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	109	};
	110	i2cp {
	111	nvidia,pins = "i2cp";
	112	nvidia,function = "i2cp";
ba4104e7 LD	113	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	114	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	115	};
	116	irda {
	117	nvidia,pins = "uad";
	118	nvidia,function = "irda";
ba4104e7 LD	119	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	120	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	121	};
	122	nand {
	123	nvidia,pins = "kbca", "kbcc", "kbcd",
	124	"kbce", "kbcf";
	125	nvidia,function = "nand";
ba4104e7 LD	126	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	127	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	128	};
	129	owc {
	130	nvidia,pins = "owc";
	131	nvidia,function = "owr";
ba4104e7 LD	132	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	133	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	134	};
	135	pmc {
	136	nvidia,pins = "pmc";
	137	nvidia,function = "pwr_on";
ba4104e7	138	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	139	};
	140	pwm {
	141	nvidia,pins = "sdb", "sdc", "sdd";
	142	nvidia,function = "pwm";
ba4104e7	143	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	144	};
	145	sdio4 {
	146	nvidia,pins = "atb", "gma", "gme";
	147	nvidia,function = "sdio4";
ba4104e7 LD	148	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	149	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	150	};
	151	spi1 {
	152	nvidia,pins = "spid", "spie", "spif";
	153	nvidia,function = "spi1";
ba4104e7 LD	154	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	155	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	156	};
	157	spi4 {
	158	nvidia,pins = "slxa", "slxc", "slxd", "slxk";
	159	nvidia,function = "spi4";
ba4104e7 LD	160	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	161	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	162	};
	163	uarta {
	164	nvidia,pins = "sdio1";
	165	nvidia,function = "uarta";
ba4104e7 LD	166	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	167	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	168	};
	169	uartd {
	170	nvidia,pins = "gmc";
	171	nvidia,function = "uartd";
ba4104e7 LD	172	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	173	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	174	};
	175	ulpi {
	176	nvidia,pins = "uaa", "uab", "uda";
	177	nvidia,function = "ulpi";
ba4104e7 LD	178	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	179	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	180	};
	181	ulpi_refclk {
	182	nvidia,pins = "cdev2";
	183	nvidia,function = "pllp_out4";
ba4104e7 LD	184	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	185	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	186	};
	187	usb_gpio {
	188	nvidia,pins = "spig", "spih";
	189	nvidia,function = "spi2_alt";
ba4104e7 LD	190	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	191	nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a LS	192	};
	193	vi {
	194	nvidia,pins = "dta", "dtb", "dtc", "dtd";
	195	nvidia,function = "vi";
ba4104e7 LD	196	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	197	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	198	};
	199	vi_sc {
	200	nvidia,pins = "csus";
	201	nvidia,function = "vi_sensor_clk";
ba4104e7 LD	202	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	203	nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a LS	204	};
	205	};
	206	};
	207
57899053 SW	208	ac97: ac97@70002000 {
	209	status = "okay";
	210	nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
	211	GPIO_ACTIVE_HIGH>;
	212	nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
	213	GPIO_ACTIVE_HIGH>;
	214	};
	215
fc9c713a LS	216	i2c@7000c000 {
	217	clock-frequency = <400000>;
	218	};
	219
	220	i2c_ddc: i2c@7000c400 {
	221	clock-frequency = <100000>;
	222	};
	223
	224	i2c@7000c500 {
	225	clock-frequency = <400000>;
	226	};
	227
	228	i2c@7000d000 {
	229	status = "okay";
	230	clock-frequency = <400000>;
	231
	232	pmic: tps6586x@34 {
	233	compatible = "ti,tps6586x";
	234	reg = <0x34>;
6cecf916	235	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
fc9c713a LS	236
	237	ti,system-power-controller;
	238
	239	#gpio-cells = <2>;
	240	gpio-controller;
	241
c7ac2b7b	242	sys-supply = <&vdd_3v3_reg>;
fc9c713a LS	243	vin-sm0-supply = <&sys_reg>;
	244	vin-sm1-supply = <&sys_reg>;
	245	vin-sm2-supply = <&sys_reg>;
	246	vinldo01-supply = <&sm2_reg>;
c7ac2b7b SA	247	vinldo23-supply = <&vdd_3v3_reg>;
	248	vinldo4-supply = <&vdd_3v3_reg>;
	249	vinldo678-supply = <&vdd_3v3_reg>;
	250	vinldo9-supply = <&vdd_3v3_reg>;
fc9c713a LS	251
	252	regulators {
	253	#address-cells = <1>;
	254	#size-cells = <0>;
	255
	256	sys_reg: regulator@0 {
	257	reg = <0>;
	258	regulator-compatible = "sys";
	259	regulator-name = "vdd_sys";
	260	regulator-always-on;
	261	};
	262
	263	regulator@1 {
	264	reg = <1>;
	265	regulator-compatible = "sm0";
	266	regulator-name = "vdd_sm0,vdd_core";
c7ac2b7b SA	267	regulator-min-microvolt = <1200000>;
c7ac2b7b SA	268	regulator-max-microvolt = <1200000>;
fc9c713a LS	269	regulator-always-on;
	270	};
	271
	272	regulator@2 {
	273	reg = <2>;
	274	regulator-compatible = "sm1";
	275	regulator-name = "vdd_sm1,vdd_cpu";
c7ac2b7b SA	276	regulator-min-microvolt = <1000000>;
c7ac2b7b SA	277	regulator-max-microvolt = <1000000>;
fc9c713a LS	278	regulator-always-on;
	279	};
	280
	281	sm2_reg: regulator@3 {
	282	reg = <3>;
	283	regulator-compatible = "sm2";
	284	regulator-name = "vdd_sm2,vin_ldo*";
844a4f0d SA	285	regulator-min-microvolt = <1800000>;
844a4f0d SA	286	regulator-max-microvolt = <1800000>;
fc9c713a LS	287	regulator-always-on;
	288	};
	289
	290	/* LDO0 is not connected to anything */
	291
	292	regulator@5 {
	293	reg = <5>;
	294	regulator-compatible = "ldo1";
	295	regulator-name = "vdd_ldo1,avdd_pll*";
	296	regulator-min-microvolt = <1100000>;
	297	regulator-max-microvolt = <1100000>;
	298	regulator-always-on;
	299	};
	300
	301	regulator@6 {
	302	reg = <6>;
	303	regulator-compatible = "ldo2";
	304	regulator-name = "vdd_ldo2,vdd_rtc";
	305	regulator-min-microvolt = <1200000>;
	306	regulator-max-microvolt = <1200000>;
	307	};
	308
	309	/* LDO3 is not connected to anything */
	310
	311	regulator@8 {
	312	reg = <8>;
	313	regulator-compatible = "ldo4";
	314	regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
	315	regulator-min-microvolt = <1800000>;
	316	regulator-max-microvolt = <1800000>;
	317	regulator-always-on;
	318	};
	319
	320	ldo5_reg: regulator@9 {
	321	reg = <9>;
	322	regulator-compatible = "ldo5";
	323	regulator-name = "vdd_ldo5,vdd_fuse";
	324	regulator-min-microvolt = <3300000>;
	325	regulator-max-microvolt = <3300000>;
	326	regulator-always-on;
	327	};
	328
	329	regulator@10 {
	330	reg = <10>;
	331	regulator-compatible = "ldo6";
	332	regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
c7ac2b7b SA	333	regulator-min-microvolt = <2850000>;
c7ac2b7b SA	334	regulator-max-microvolt = <2850000>;
fc9c713a LS	335	};
	336
	337	hdmi_vdd_reg: regulator@11 {
	338	reg = <11>;
	339	regulator-compatible = "ldo7";
	340	regulator-name = "vdd_ldo7,avdd_hdmi";
	341	regulator-min-microvolt = <3300000>;
	342	regulator-max-microvolt = <3300000>;
	343	};
	344
	345	hdmi_pll_reg: regulator@12 {
	346	reg = <12>;
	347	regulator-compatible = "ldo8";
	348	regulator-name = "vdd_ldo8,avdd_hdmi_pll";
	349	regulator-min-microvolt = <1800000>;
	350	regulator-max-microvolt = <1800000>;
	351	};
	352
	353	regulator@13 {
	354	reg = <13>;
	355	regulator-compatible = "ldo9";
	356	regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
	357	regulator-min-microvolt = <2850000>;
	358	regulator-max-microvolt = <2850000>;
	359	regulator-always-on;
	360	};
	361
	362	regulator@14 {
	363	reg = <14>;
	364	regulator-compatible = "ldo_rtc";
	365	regulator-name = "vdd_rtc_out,vdd_cell";
	366	regulator-min-microvolt = <3300000>;
	367	regulator-max-microvolt = <3300000>;
	368	regulator-always-on;
	369	};
	370	};
	371	};
	372
	373	temperature-sensor@4c {
	374	compatible = "national,lm95245";
	375	reg = <0x4c>;
	376	};
	377	};
	378
58ecb23f	379	pmc@7000e400 {
47d2d63b	380	nvidia,suspend-mode = <1>;
a44a019d JL	381	nvidia,cpu-pwr-good-time = <5000>;
	382	nvidia,cpu-pwr-off-time = <5000>;
	383	nvidia,core-pwr-good-time = <3845 3845>;
	384	nvidia,core-pwr-off-time = <3875>;
	385	nvidia,sys-clock-req-active-high;
	386	};
	387
fc9c713a LS	388	memory-controller@7000f400 {
	389	emc-table@83250 {
	390	reg = <83250>;
	391	compatible = "nvidia,tegra20-emc-table";
	392	clock-frequency = <83250>;
	393	nvidia,emc-registers = <0x00000005 0x00000011
	394	0x00000004 0x00000002 0x00000004 0x00000004
	395	0x00000001 0x0000000a 0x00000002 0x00000002
	396	0x00000001 0x00000001 0x00000003 0x00000004
	397	0x00000003 0x00000009 0x0000000c 0x0000025f
	398	0x00000000 0x00000003 0x00000003 0x00000002
	399	0x00000002 0x00000001 0x00000008 0x000000c8
	400	0x00000003 0x00000005 0x00000003 0x0000000c
	401	0x00000002 0x00000000 0x00000000 0x00000002
	402	0x00000000 0x00000000 0x00000083 0x00520006
	403	0x00000010 0x00000008 0x00000000 0x00000000
	404	0x00000000 0x00000000 0x00000000 0x00000000>;
	405	};
	406	emc-table@133200 {
	407	reg = <133200>;
	408	compatible = "nvidia,tegra20-emc-table";
	409	clock-frequency = <133200>;
	410	nvidia,emc-registers = <0x00000008 0x00000019
	411	0x00000006 0x00000002 0x00000004 0x00000004
	412	0x00000001 0x0000000a 0x00000002 0x00000002
	413	0x00000002 0x00000001 0x00000003 0x00000004
	414	0x00000003 0x00000009 0x0000000c 0x0000039f
	415	0x00000000 0x00000003 0x00000003 0x00000002
	416	0x00000002 0x00000001 0x00000008 0x000000c8
	417	0x00000003 0x00000007 0x00000003 0x0000000c
	418	0x00000002 0x00000000 0x00000000 0x00000002
	419	0x00000000 0x00000000 0x00000083 0x00510006
	420	0x00000010 0x00000008 0x00000000 0x00000000
	421	0x00000000 0x00000000 0x00000000 0x00000000>;
	422	};
	423	emc-table@166500 {
	424	reg = <166500>;
	425	compatible = "nvidia,tegra20-emc-table";
	426	clock-frequency = <166500>;
	427	nvidia,emc-registers = <0x0000000a 0x00000021
	428	0x00000008 0x00000003 0x00000004 0x00000004
	429	0x00000002 0x0000000a 0x00000003 0x00000003
	430	0x00000002 0x00000001 0x00000003 0x00000004
	431	0x00000003 0x00000009 0x0000000c 0x000004df
	432	0x00000000 0x00000003 0x00000003 0x00000003
	433	0x00000003 0x00000001 0x00000009 0x000000c8
	434	0x00000003 0x00000009 0x00000004 0x0000000c
	435	0x00000002 0x00000000 0x00000000 0x00000002
	436	0x00000000 0x00000000 0x00000083 0x004f0006
	437	0x00000010 0x00000008 0x00000000 0x00000000
	438	0x00000000 0x00000000 0x00000000 0x00000000>;
	439	};
	440	emc-table@333000 {
	441	reg = <333000>;
	442	compatible = "nvidia,tegra20-emc-table";
	443	clock-frequency = <333000>;
	444	nvidia,emc-registers = <0x00000014 0x00000041
	445	0x0000000f 0x00000005 0x00000004 0x00000005
	446	0x00000003 0x0000000a 0x00000005 0x00000005
	447	0x00000004 0x00000001 0x00000003 0x00000004
	448	0x00000003 0x00000009 0x0000000c 0x000009ff
	449	0x00000000 0x00000003 0x00000003 0x00000005
	450	0x00000005 0x00000001 0x0000000e 0x000000c8
	451	0x00000003 0x00000011 0x00000006 0x0000000c
452	0x00000002 0x00000000 0x00000000 0x00000002
453	0x00000000 0x00000000 0x00000083 0x00380006
454	0x00000010 0x00000008 0x00000000 0x00000000
455	0x00000000 0x00000000 0x00000000 0x00000000>;
456	};
457	};
458
fc9c713a LS	459	usb@c5004000 {
fc9c713a LS	460	status = "okay";
3325f1bc SW	461	nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
3325f1bc SW	462	GPIO_ACTIVE_LOW>;
9dffe3be VB	463	};
	464
	465	usb-phy@c5004000 {
a1632ad3	466	status = "okay";
3325f1bc SW	467	nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
3325f1bc SW	468	GPIO_ACTIVE_LOW>;
fc9c713a LS	469	};
	470
	471	sdhci@c8000600 {
3325f1bc	472	cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
fc9c713a LS	473	};
fc9c713a LS	474
7021d122 JL	475	clocks {
	476	compatible = "simple-bus";
	477	#address-cells = <1>;
	478	#size-cells = <0>;
	479
58ecb23f	480	clk32k_in: clock@0 {
7021d122	481	compatible = "fixed-clock";
4ec2e601	482	reg = <0>;
7021d122 JL	483	#clock-cells = <0>;
	484	clock-frequency = <32768>;
	485	};
	486	};
	487
fc9c713a LS	488	regulators {
	489	compatible = "simple-bus";
	490	#address-cells = <1>;
	491	#size-cells = <0>;
	492
c7ac2b7b	493	vdd_3v3_reg: regulator@100 {
fc9c713a LS	494	compatible = "regulator-fixed";
fc9c713a LS	495	reg = <100>;
c7ac2b7b SA	496	regulator-name = "vdd_3v3";
	497	regulator-min-microvolt = <3300000>;
	498	regulator-max-microvolt = <3300000>;
fc9c713a LS	499	regulator-always-on;
	500	};
	501
	502	regulator@101 {
	503	compatible = "regulator-fixed";
	504	reg = <101>;
	505	regulator-name = "internal_usb";
	506	regulator-min-microvolt = <5000000>;
	507	regulator-max-microvolt = <5000000>;
	508	enable-active-high;
	509	regulator-boot-on;
	510	regulator-always-on;
3325f1bc	511	gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
fc9c713a LS	512	};
fc9c713a LS	513	};
57899053 SW	514
	515	sound {
	516	compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
	517	"nvidia,tegra-audio-wm9712";
	518	nvidia,model = "Colibri T20 AC97 Audio";
	519
	520	nvidia,audio-routing =
	521	"Headphone", "HPOUTL",
	522	"Headphone", "HPOUTR",
	523	"LineIn", "LINEINL",
	524	"LineIn", "LINEINR",
	525	"Mic", "MIC1";
	526
	527	nvidia,ac97-controller = <&ac97>;
	528
	529	clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
	530	<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
	531	<&tegra_car TEGRA20_CLK_CDEV1>;
	532	clock-names = "pll_a", "pll_a_out0", "mclk";
	533	};
fc9c713a	534	};