Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
a1425d42 JL |
2 | /dts-v1/; |
3 | ||
146db0ea | 4 | #include <dt-bindings/input/input.h> |
a1425d42 JL |
5 | #include "tegra124.dtsi" |
6 | ||
7 | / { | |
8 | model = "NVIDIA Tegra124 Venice2"; | |
9 | compatible = "nvidia,venice2", "nvidia,tegra124"; | |
10 | ||
b1afa782 | 11 | aliases { |
b5896f67 MZ |
12 | rtc0 = "/i2c@7000d000/pmic@40"; |
13 | rtc1 = "/rtc@7000e000"; | |
c4574aa0 | 14 | serial0 = &uarta; |
b1afa782 SW |
15 | }; |
16 | ||
f5bbb327 JH |
17 | chosen { |
18 | stdout-path = "serial0:115200n8"; | |
19 | }; | |
20 | ||
48299769 | 21 | memory@80000000 { |
e30cb238 | 22 | reg = <0x0 0x80000000 0x0 0x80000000>; |
a1425d42 JL |
23 | }; |
24 | ||
b5896f67 MZ |
25 | host1x@50000000 { |
26 | hdmi@54280000 { | |
329c39f8 TR |
27 | status = "okay"; |
28 | ||
29 | vdd-supply = <&vdd_3v3_hdmi>; | |
30 | pll-supply = <&vdd_hdmi_pll>; | |
31 | hdmi-supply = <&vdd_5v0_hdmi>; | |
32 | ||
33 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
34 | nvidia,hpd-gpio = | |
35 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
36 | }; | |
37 | ||
b5896f67 | 38 | sor@54540000 { |
40e231c7 TR |
39 | status = "okay"; |
40 | ||
41 | nvidia,dpaux = <&dpaux>; | |
42 | nvidia,panel = <&panel>; | |
43 | }; | |
44 | ||
b5896f67 | 45 | dpaux@545c0000 { |
40e231c7 TR |
46 | vdd-supply = <&vdd_3v3_panel>; |
47 | status = "okay"; | |
48 | }; | |
49 | }; | |
50 | ||
e34cc1b6 TR |
51 | gpu@0,57000000 { |
52 | /* | |
53 | * Node left disabled on purpose - the bootloader will enable | |
54 | * it after having set the VPR up | |
55 | */ | |
56 | vdd-supply = <&vdd_gpu>; | |
57 | }; | |
58 | ||
b5896f67 | 59 | pinmux: pinmux@70000868 { |
6dbaff2b SW |
60 | pinctrl-names = "boot"; |
61 | pinctrl-0 = <&pinmux_boot>; | |
4b20bcbe | 62 | |
6dbaff2b | 63 | pinmux_boot: common { |
4b20bcbe LD |
64 | dap_mclk1_pw4 { |
65 | nvidia,pins = "dap_mclk1_pw4"; | |
66 | nvidia,function = "extperiph1"; | |
67 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
68 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
69 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
70 | }; | |
71 | dap1_din_pn1 { | |
365c483f LD |
72 | nvidia,pins = "dap1_din_pn1"; |
73 | nvidia,function = "i2s0"; | |
74 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
75 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
76 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
77 | }; | |
78 | dap1_dout_pn2 { | |
79 | nvidia,pins = "dap1_dout_pn2", | |
4b20bcbe LD |
80 | "dap1_fs_pn0", |
81 | "dap1_sclk_pn3"; | |
82 | nvidia,function = "i2s0"; | |
365c483f | 83 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
84 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
85 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
86 | }; | |
87 | dap2_din_pa4 { | |
365c483f | 88 | nvidia,pins = "dap2_din_pa4"; |
4b20bcbe LD |
89 | nvidia,function = "i2s1"; |
90 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
91 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
4ffb9385 | 92 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
4b20bcbe | 93 | }; |
365c483f LD |
94 | dap2_dout_pa5 { |
95 | nvidia,pins = "dap2_dout_pa5", | |
96 | "dap2_fs_pa2", | |
97 | "dap2_sclk_pa3"; | |
98 | nvidia,function = "i2s1"; | |
4b20bcbe LD |
99 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
100 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
365c483f | 101 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
4b20bcbe | 102 | }; |
365c483f LD |
103 | dvfs_pwm_px0 { |
104 | nvidia,pins = "dvfs_pwm_px0", | |
105 | "dvfs_clk_px2"; | |
4b20bcbe LD |
106 | nvidia,function = "cldvfs"; |
107 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
108 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
109 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
110 | }; | |
111 | ulpi_clk_py0 { | |
112 | nvidia,pins = "ulpi_clk_py0", | |
4b20bcbe LD |
113 | "ulpi_nxt_py2", |
114 | "ulpi_stp_py3"; | |
115 | nvidia,function = "spi1"; | |
365c483f LD |
116 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
117 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
118 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
119 | }; | |
120 | ulpi_dir_py1 { | |
121 | nvidia,pins = "ulpi_dir_py1"; | |
122 | nvidia,function = "spi1"; | |
4b20bcbe | 123 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
365c483f | 124 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
4b20bcbe LD |
125 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
126 | }; | |
127 | cam_i2c_scl_pbb1 { | |
128 | nvidia,pins = "cam_i2c_scl_pbb1", | |
129 | "cam_i2c_sda_pbb2"; | |
130 | nvidia,function = "i2c3"; | |
131 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
132 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
133 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
134 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
135 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
136 | }; | |
137 | gen2_i2c_scl_pt5 { | |
138 | nvidia,pins = "gen2_i2c_scl_pt5", | |
139 | "gen2_i2c_sda_pt6"; | |
140 | nvidia,function = "i2c2"; | |
141 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
142 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
143 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
144 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
145 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
146 | }; | |
147 | pg4 { | |
148 | nvidia,pins = "pg4", | |
149 | "pg5", | |
150 | "pg6", | |
4b20bcbe LD |
151 | "pi3"; |
152 | nvidia,function = "spi4"; | |
153 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
154 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
155 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
156 | }; | |
365c483f LD |
157 | pg7 { |
158 | nvidia,pins = "pg7"; | |
159 | nvidia,function = "spi4"; | |
4b20bcbe | 160 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
365c483f LD |
161 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
162 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
4b20bcbe LD |
163 | }; |
164 | ph1 { | |
165 | nvidia,pins = "ph1"; | |
166 | nvidia,function = "pwm1"; | |
167 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
168 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
169 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
170 | }; | |
365c483f LD |
171 | pk0 { |
172 | nvidia,pins = "pk0", | |
173 | "kb_row15_ps7", | |
174 | "clk_32k_out_pa0"; | |
175 | nvidia,function = "soc"; | |
176 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
f5cb19b4 | 177 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
365c483f | 178 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
f5cb19b4 | 179 | }; |
4b20bcbe | 180 | sdmmc1_clk_pz0 { |
bf5fd5bf | 181 | nvidia,pins = "sdmmc1_clk_pz0"; |
4b20bcbe | 182 | nvidia,function = "sdmmc1"; |
bf5fd5bf | 183 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
184 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
185 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
186 | }; | |
365c483f LD |
187 | sdmmc1_cmd_pz1 { |
188 | nvidia,pins = "sdmmc1_cmd_pz1", | |
189 | "sdmmc1_dat0_py7", | |
190 | "sdmmc1_dat1_py6", | |
191 | "sdmmc1_dat2_py5", | |
192 | "sdmmc1_dat3_py4"; | |
193 | nvidia,function = "sdmmc1"; | |
194 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
195 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
196 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
197 | }; | |
4b20bcbe LD |
198 | sdmmc3_clk_pa6 { |
199 | nvidia,pins = "sdmmc3_clk_pa6"; | |
200 | nvidia,function = "sdmmc3"; | |
201 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
202 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
203 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
204 | }; | |
205 | sdmmc3_cmd_pa7 { | |
206 | nvidia,pins = "sdmmc3_cmd_pa7", | |
207 | "sdmmc3_dat0_pb7", | |
208 | "sdmmc3_dat1_pb6", | |
209 | "sdmmc3_dat2_pb5", | |
210 | "sdmmc3_dat3_pb4", | |
211 | "sdmmc3_clk_lb_out_pee4", | |
212 | "sdmmc3_clk_lb_in_pee5"; | |
213 | nvidia,function = "sdmmc3"; | |
214 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
215 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
216 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
217 | }; | |
218 | sdmmc4_clk_pcc4 { | |
219 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
220 | nvidia,function = "sdmmc4"; | |
221 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
222 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
223 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
224 | }; | |
225 | sdmmc4_cmd_pt7 { | |
226 | nvidia,pins = "sdmmc4_cmd_pt7", | |
227 | "sdmmc4_dat0_paa0", | |
228 | "sdmmc4_dat1_paa1", | |
229 | "sdmmc4_dat2_paa2", | |
230 | "sdmmc4_dat3_paa3", | |
231 | "sdmmc4_dat4_paa4", | |
232 | "sdmmc4_dat5_paa5", | |
233 | "sdmmc4_dat6_paa6", | |
234 | "sdmmc4_dat7_paa7"; | |
235 | nvidia,function = "sdmmc4"; | |
236 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
237 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
238 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
239 | }; | |
240 | pwr_i2c_scl_pz6 { | |
241 | nvidia,pins = "pwr_i2c_scl_pz6", | |
242 | "pwr_i2c_sda_pz7"; | |
243 | nvidia,function = "i2cpwr"; | |
244 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
245 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
246 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
365c483f | 247 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
248 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
249 | }; | |
250 | jtag_rtck { | |
251 | nvidia,pins = "jtag_rtck"; | |
252 | nvidia,function = "rtck"; | |
253 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
254 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
255 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
256 | }; | |
257 | clk_32k_in { | |
258 | nvidia,pins = "clk_32k_in"; | |
259 | nvidia,function = "clk"; | |
260 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
261 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
262 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
263 | }; | |
264 | core_pwr_req { | |
265 | nvidia,pins = "core_pwr_req"; | |
266 | nvidia,function = "pwron"; | |
267 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
268 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
269 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
270 | }; | |
271 | cpu_pwr_req { | |
272 | nvidia,pins = "cpu_pwr_req"; | |
273 | nvidia,function = "cpu"; | |
274 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
275 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
276 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
277 | }; | |
278 | pwr_int_n { | |
279 | nvidia,pins = "pwr_int_n"; | |
280 | nvidia,function = "pmi"; | |
281 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
282 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
283 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
284 | }; | |
285 | reset_out_n { | |
286 | nvidia,pins = "reset_out_n"; | |
287 | nvidia,function = "reset_out_n"; | |
288 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
289 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
290 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
291 | }; | |
292 | clk3_out_pee0 { | |
293 | nvidia,pins = "clk3_out_pee0"; | |
294 | nvidia,function = "extperiph3"; | |
295 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
296 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
297 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
298 | }; | |
299 | dap4_din_pp5 { | |
365c483f LD |
300 | nvidia,pins = "dap4_din_pp5"; |
301 | nvidia,function = "i2s3"; | |
302 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
303 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
304 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
305 | }; | |
306 | dap4_dout_pp6 { | |
307 | nvidia,pins = "dap4_dout_pp6", | |
4b20bcbe LD |
308 | "dap4_fs_pp4", |
309 | "dap4_sclk_pp7"; | |
310 | nvidia,function = "i2s3"; | |
365c483f | 311 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
312 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
313 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
314 | }; | |
315 | gen1_i2c_sda_pc5 { | |
316 | nvidia,pins = "gen1_i2c_sda_pc5", | |
317 | "gen1_i2c_scl_pc4"; | |
318 | nvidia,function = "i2c1"; | |
319 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
320 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
321 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
322 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
365c483f | 323 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
4b20bcbe | 324 | }; |
365c483f LD |
325 | uart2_cts_n_pj5 { |
326 | nvidia,pins = "uart2_cts_n_pj5"; | |
327 | nvidia,function = "uartb"; | |
4b20bcbe | 328 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
4ffb9385 | 329 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
4b20bcbe LD |
330 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
331 | }; | |
365c483f LD |
332 | uart2_rts_n_pj6 { |
333 | nvidia,pins = "uart2_rts_n_pj6"; | |
4b20bcbe | 334 | nvidia,function = "uartb"; |
365c483f | 335 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
336 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
337 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
338 | }; | |
339 | uart2_rxd_pc3 { | |
365c483f | 340 | nvidia,pins = "uart2_rxd_pc3"; |
4b20bcbe LD |
341 | nvidia,function = "irda"; |
342 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
343 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
344 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
345 | }; | |
365c483f LD |
346 | uart2_txd_pc2 { |
347 | nvidia,pins = "uart2_txd_pc2"; | |
348 | nvidia,function = "irda"; | |
349 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
350 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
351 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
352 | }; | |
4b20bcbe LD |
353 | uart3_cts_n_pa1 { |
354 | nvidia,pins = "uart3_cts_n_pa1", | |
365c483f | 355 | "uart3_rxd_pw7"; |
4b20bcbe LD |
356 | nvidia,function = "uartc"; |
357 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
358 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
359 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
360 | }; | |
365c483f LD |
361 | uart3_rts_n_pc0 { |
362 | nvidia,pins = "uart3_rts_n_pc0", | |
363 | "uart3_txd_pw6"; | |
364 | nvidia,function = "uartc"; | |
365 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
366 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
367 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
368 | }; | |
4b20bcbe LD |
369 | hdmi_cec_pee3 { |
370 | nvidia,pins = "hdmi_cec_pee3"; | |
371 | nvidia,function = "cec"; | |
372 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
373 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
374 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
365c483f LD |
375 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
376 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
377 | }; | |
378 | hdmi_int_pn7 { | |
379 | nvidia,pins = "hdmi_int_pn7"; | |
380 | nvidia,function = "rsvd1"; | |
381 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
382 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
383 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
4b20bcbe LD |
384 | }; |
385 | ddc_scl_pv4 { | |
386 | nvidia,pins = "ddc_scl_pv4", | |
387 | "ddc_sda_pv5"; | |
388 | nvidia,function = "i2c4"; | |
389 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
390 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
391 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
365c483f LD |
392 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
393 | nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; | |
394 | }; | |
395 | pj7 { | |
396 | nvidia,pins = "pj7", | |
397 | "pk7"; | |
398 | nvidia,function = "uartd"; | |
399 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
400 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
401 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
402 | }; | |
403 | pb0 { | |
404 | nvidia,pins = "pb0", | |
405 | "pb1"; | |
406 | nvidia,function = "uartd"; | |
407 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
408 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
409 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
410 | }; | |
411 | ph0 { | |
412 | nvidia,pins = "ph0"; | |
413 | nvidia,function = "pwm0"; | |
414 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
415 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
416 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
417 | }; | |
418 | kb_row10_ps2 { | |
419 | nvidia,pins = "kb_row10_ps2"; | |
420 | nvidia,function = "uarta"; | |
421 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
422 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
423 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
424 | }; | |
425 | kb_row9_ps1 { | |
426 | nvidia,pins = "kb_row9_ps1"; | |
427 | nvidia,function = "uarta"; | |
428 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
429 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
430 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
431 | }; | |
432 | kb_row6_pr6 { | |
433 | nvidia,pins = "kb_row6_pr6"; | |
434 | nvidia,function = "displaya_alt"; | |
435 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
436 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
437 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
4b20bcbe LD |
438 | }; |
439 | usb_vbus_en0_pn4 { | |
fa15ffaa TR |
440 | nvidia,pins = "usb_vbus_en0_pn4", |
441 | "usb_vbus_en1_pn5"; | |
4b20bcbe LD |
442 | nvidia,function = "usb"; |
443 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
fa15ffaa | 444 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
4b20bcbe LD |
445 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
446 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
365c483f | 447 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
4b20bcbe LD |
448 | }; |
449 | drive_sdio1 { | |
450 | nvidia,pins = "drive_sdio1"; | |
451 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
452 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
4b20bcbe LD |
453 | nvidia,pull-down-strength = <32>; |
454 | nvidia,pull-up-strength = <42>; | |
455 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
456 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
457 | }; | |
458 | drive_sdio3 { | |
459 | nvidia,pins = "drive_sdio3"; | |
460 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
461 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
4b20bcbe LD |
462 | nvidia,pull-down-strength = <20>; |
463 | nvidia,pull-up-strength = <36>; | |
464 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
465 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
466 | }; | |
467 | drive_gma { | |
468 | nvidia,pins = "drive_gma"; | |
469 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
470 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
471 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
472 | nvidia,pull-down-strength = <1>; | |
473 | nvidia,pull-up-strength = <2>; | |
474 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
475 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
476 | nvidia,drive-type = <1>; | |
477 | }; | |
365c483f LD |
478 | als_irq_l { |
479 | nvidia,pins = "gpio_x3_aud_px3"; | |
480 | nvidia,function = "gmi"; | |
481 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
482 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
483 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
484 | }; | |
485 | codec_irq_l { | |
486 | nvidia,pins = "ph4"; | |
487 | nvidia,function = "gmi"; | |
488 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
489 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
490 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
491 | }; | |
492 | lcd_bl_en { | |
493 | nvidia,pins = "ph2"; | |
494 | nvidia,function = "gmi"; | |
495 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
496 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
497 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
498 | }; | |
499 | touch_irq_l { | |
500 | nvidia,pins = "gpio_w3_aud_pw3"; | |
501 | nvidia,function = "spi6"; | |
502 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
503 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
504 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
505 | }; | |
506 | tpm_davint_l { | |
507 | nvidia,pins = "ph6"; | |
508 | nvidia,function = "gmi"; | |
509 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
510 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
511 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
512 | }; | |
513 | ts_irq_l { | |
514 | nvidia,pins = "pk2"; | |
515 | nvidia,function = "gmi"; | |
516 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
517 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
518 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
519 | }; | |
520 | ts_reset_l { | |
521 | nvidia,pins = "pk4"; | |
522 | nvidia,function = "gmi"; | |
523 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
524 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
525 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
526 | }; | |
527 | ts_shdn_l { | |
528 | nvidia,pins = "pk1"; | |
529 | nvidia,function = "gmi"; | |
530 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
531 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
532 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
533 | }; | |
534 | ph7 { | |
535 | nvidia,pins = "ph7"; | |
536 | nvidia,function = "gmi"; | |
537 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
538 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
539 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
540 | }; | |
541 | kb_col0_ap { | |
542 | nvidia,pins = "kb_col0_pq0"; | |
543 | nvidia,function = "rsvd4"; | |
544 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
545 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
546 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
547 | }; | |
548 | lid_open { | |
549 | nvidia,pins = "kb_row4_pr4"; | |
550 | nvidia,function = "rsvd3"; | |
551 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
552 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
553 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
554 | }; | |
555 | en_vdd_sd { | |
556 | nvidia,pins = "kb_row0_pr0"; | |
557 | nvidia,function = "rsvd4"; | |
558 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
559 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
560 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
561 | }; | |
562 | ac_ok { | |
563 | nvidia,pins = "pj0"; | |
564 | nvidia,function = "gmi"; | |
565 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
566 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
567 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
568 | }; | |
569 | sensor_irq_l { | |
570 | nvidia,pins = "pi6"; | |
571 | nvidia,function = "gmi"; | |
572 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
573 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
574 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
575 | }; | |
576 | wifi_en { | |
577 | nvidia,pins = "gpio_x7_aud_px7"; | |
578 | nvidia,function = "rsvd4"; | |
579 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
580 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
581 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
582 | }; | |
583 | wifi_rst_l { | |
584 | nvidia,pins = "clk2_req_pcc5"; | |
585 | nvidia,function = "dap"; | |
586 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
587 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
588 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
589 | }; | |
590 | hp_det_l { | |
591 | nvidia,pins = "ulpi_data1_po2"; | |
592 | nvidia,function = "spi3"; | |
593 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
594 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
595 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
596 | }; | |
4b20bcbe LD |
597 | }; |
598 | }; | |
599 | ||
b5896f67 | 600 | serial@70006000 { |
a1425d42 JL |
601 | status = "okay"; |
602 | }; | |
603 | ||
b5896f67 | 604 | pwm@7000a000 { |
e013485d TR |
605 | status = "okay"; |
606 | }; | |
607 | ||
b5896f67 | 608 | i2c@7000c000 { |
9d5b2505 SW |
609 | status = "okay"; |
610 | clock-frequency = <100000>; | |
b0e1caee SW |
611 | |
612 | acodec: audio-codec@10 { | |
613 | compatible = "maxim,max98090"; | |
614 | reg = <0x10>; | |
615 | interrupt-parent = <&gpio>; | |
b604ef9c | 616 | interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>; |
b0e1caee | 617 | }; |
9d5b2505 SW |
618 | }; |
619 | ||
b5896f67 | 620 | i2c@7000c400 { |
9d5b2505 SW |
621 | status = "okay"; |
622 | clock-frequency = <100000>; | |
bf8f0392 SW |
623 | |
624 | trackpad@4b { | |
625 | compatible = "atmel,maxtouch"; | |
626 | reg = <0x4b>; | |
627 | interrupt-parent = <&gpio>; | |
628 | interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>; | |
629 | linux,gpio-keymap = <0 0 0 BTN_LEFT>; | |
630 | }; | |
9d5b2505 SW |
631 | }; |
632 | ||
b5896f67 | 633 | i2c@7000c500 { |
9d5b2505 SW |
634 | status = "okay"; |
635 | clock-frequency = <100000>; | |
636 | }; | |
637 | ||
b5896f67 | 638 | hdmi_ddc: i2c@7000c700 { |
9d5b2505 SW |
639 | status = "okay"; |
640 | clock-frequency = <100000>; | |
641 | }; | |
642 | ||
b5896f67 | 643 | i2c@7000d000 { |
9d5b2505 | 644 | status = "okay"; |
fcacaba7 LD |
645 | clock-frequency = <400000>; |
646 | ||
fdc44f94 | 647 | pmic: pmic@40 { |
fcacaba7 LD |
648 | compatible = "ams,as3722"; |
649 | reg = <0x40>; | |
650 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | |
651 | ||
7be75df2 LD |
652 | ams,system-power-controller; |
653 | ||
fcacaba7 LD |
654 | #interrupt-cells = <2>; |
655 | interrupt-controller; | |
656 | ||
657 | gpio-controller; | |
658 | #gpio-cells = <2>; | |
659 | ||
660 | pinctrl-names = "default"; | |
661 | pinctrl-0 = <&as3722_default>; | |
662 | ||
663 | as3722_default: pinmux { | |
664 | gpio0 { | |
665 | pins = "gpio0"; | |
666 | function = "gpio"; | |
667 | bias-pull-down; | |
668 | }; | |
669 | ||
670 | gpio1_2_4_7 { | |
671 | pins = "gpio1", "gpio2", "gpio4", "gpio7"; | |
672 | function = "gpio"; | |
673 | bias-pull-up; | |
674 | }; | |
675 | ||
676 | gpio3_6 { | |
677 | pins = "gpio3", "gpio6"; | |
678 | bias-high-impedance; | |
679 | }; | |
680 | ||
681 | gpio5 { | |
682 | pins = "gpio5"; | |
683 | function = "clk32k-out"; | |
684 | }; | |
685 | }; | |
686 | ||
687 | regulators { | |
af144b8d TR |
688 | vsup-sd2-supply = <&vdd_5v0_sys>; |
689 | vsup-sd3-supply = <&vdd_5v0_sys>; | |
690 | vsup-sd4-supply = <&vdd_5v0_sys>; | |
691 | vsup-sd5-supply = <&vdd_5v0_sys>; | |
692 | vin-ldo0-supply = <&vdd_1v35_lp0>; | |
693 | vin-ldo1-6-supply = <&vdd_3v3_run>; | |
694 | vin-ldo2-5-7-supply = <&vddio_1v8>; | |
695 | vin-ldo3-4-supply = <&vdd_3v3_sys>; | |
696 | vin-ldo9-10-supply = <&vdd_5v0_sys>; | |
697 | vin-ldo11-supply = <&vdd_3v3_run>; | |
fcacaba7 LD |
698 | |
699 | sd0 { | |
af144b8d | 700 | regulator-name = "+VDD_CPU_AP"; |
fcacaba7 LD |
701 | regulator-min-microvolt = <700000>; |
702 | regulator-max-microvolt = <1400000>; | |
703 | regulator-min-microamp = <3500000>; | |
704 | regulator-max-microamp = <3500000>; | |
705 | regulator-always-on; | |
706 | regulator-boot-on; | |
ee913f7a | 707 | ams,ext-control = <2>; |
fcacaba7 LD |
708 | }; |
709 | ||
710 | sd1 { | |
af144b8d | 711 | regulator-name = "+VDD_CORE"; |
fcacaba7 LD |
712 | regulator-min-microvolt = <700000>; |
713 | regulator-max-microvolt = <1350000>; | |
714 | regulator-min-microamp = <2500000>; | |
715 | regulator-max-microamp = <2500000>; | |
716 | regulator-always-on; | |
717 | regulator-boot-on; | |
ee913f7a | 718 | ams,ext-control = <1>; |
fcacaba7 LD |
719 | }; |
720 | ||
af144b8d TR |
721 | vdd_1v35_lp0: sd2 { |
722 | regulator-name = "+1.35V_LP0(sd2)"; | |
fcacaba7 LD |
723 | regulator-min-microvolt = <1350000>; |
724 | regulator-max-microvolt = <1350000>; | |
725 | regulator-always-on; | |
726 | regulator-boot-on; | |
727 | }; | |
728 | ||
729 | sd3 { | |
af144b8d | 730 | regulator-name = "+1.35V_LP0(sd3)"; |
fcacaba7 LD |
731 | regulator-min-microvolt = <1350000>; |
732 | regulator-max-microvolt = <1350000>; | |
733 | regulator-always-on; | |
734 | regulator-boot-on; | |
735 | }; | |
736 | ||
329c39f8 | 737 | vdd_1v05_run: sd4 { |
af144b8d | 738 | regulator-name = "+1.05V_RUN"; |
fcacaba7 LD |
739 | regulator-min-microvolt = <1050000>; |
740 | regulator-max-microvolt = <1050000>; | |
fcacaba7 LD |
741 | }; |
742 | ||
af144b8d TR |
743 | vddio_1v8: sd5 { |
744 | regulator-name = "+1.8V_VDDIO"; | |
fcacaba7 LD |
745 | regulator-min-microvolt = <1800000>; |
746 | regulator-max-microvolt = <1800000>; | |
747 | regulator-boot-on; | |
748 | regulator-always-on; | |
749 | }; | |
750 | ||
e34cc1b6 | 751 | vdd_gpu: sd6 { |
af144b8d | 752 | regulator-name = "+VDD_GPU_AP"; |
fcacaba7 LD |
753 | regulator-min-microvolt = <650000>; |
754 | regulator-max-microvolt = <1200000>; | |
755 | regulator-min-microamp = <3500000>; | |
756 | regulator-max-microamp = <3500000>; | |
757 | regulator-boot-on; | |
758 | regulator-always-on; | |
759 | }; | |
760 | ||
4da6b31f | 761 | avdd_1v05_run: ldo0 { |
af144b8d | 762 | regulator-name = "+1.05V_RUN_AVDD"; |
fcacaba7 LD |
763 | regulator-min-microvolt = <1050000>; |
764 | regulator-max-microvolt = <1050000>; | |
765 | regulator-boot-on; | |
766 | regulator-always-on; | |
ee913f7a | 767 | ams,ext-control = <1>; |
fcacaba7 LD |
768 | }; |
769 | ||
770 | ldo1 { | |
af144b8d | 771 | regulator-name = "+1.8V_RUN_CAM"; |
fcacaba7 LD |
772 | regulator-min-microvolt = <1800000>; |
773 | regulator-max-microvolt = <1800000>; | |
774 | }; | |
775 | ||
776 | ldo2 { | |
af144b8d | 777 | regulator-name = "+1.2V_GEN_AVDD"; |
fcacaba7 LD |
778 | regulator-min-microvolt = <1200000>; |
779 | regulator-max-microvolt = <1200000>; | |
780 | regulator-boot-on; | |
781 | regulator-always-on; | |
782 | }; | |
783 | ||
784 | ldo3 { | |
af144b8d | 785 | regulator-name = "+1.00V_LP0_VDD_RTC"; |
fcacaba7 LD |
786 | regulator-min-microvolt = <1000000>; |
787 | regulator-max-microvolt = <1000000>; | |
788 | regulator-boot-on; | |
789 | regulator-always-on; | |
790 | ams,enable-tracking; | |
791 | }; | |
792 | ||
431b7be0 | 793 | vdd_run_cam: ldo4 { |
af144b8d | 794 | regulator-name = "+3.3V_RUN_CAM"; |
fcacaba7 LD |
795 | regulator-min-microvolt = <2800000>; |
796 | regulator-max-microvolt = <2800000>; | |
fcacaba7 LD |
797 | }; |
798 | ||
799 | ldo5 { | |
af144b8d | 800 | regulator-name = "+1.2V_RUN_CAM_FRONT"; |
fcacaba7 LD |
801 | regulator-min-microvolt = <1200000>; |
802 | regulator-max-microvolt = <1200000>; | |
803 | }; | |
804 | ||
4989b439 | 805 | vddio_sdmmc3: ldo6 { |
af144b8d | 806 | regulator-name = "+VDDIO_SDMMC3"; |
fcacaba7 LD |
807 | regulator-min-microvolt = <1800000>; |
808 | regulator-max-microvolt = <3300000>; | |
fcacaba7 LD |
809 | }; |
810 | ||
811 | ldo7 { | |
af144b8d | 812 | regulator-name = "+1.05V_RUN_CAM_REAR"; |
fcacaba7 LD |
813 | regulator-min-microvolt = <1050000>; |
814 | regulator-max-microvolt = <1050000>; | |
815 | }; | |
816 | ||
817 | ldo9 { | |
af144b8d | 818 | regulator-name = "+2.8V_RUN_TOUCH"; |
fcacaba7 LD |
819 | regulator-min-microvolt = <2800000>; |
820 | regulator-max-microvolt = <2800000>; | |
821 | }; | |
822 | ||
823 | ldo10 { | |
af144b8d | 824 | regulator-name = "+2.8V_RUN_CAM_AF"; |
fcacaba7 LD |
825 | regulator-min-microvolt = <2800000>; |
826 | regulator-max-microvolt = <2800000>; | |
827 | }; | |
828 | ||
829 | ldo11 { | |
af144b8d | 830 | regulator-name = "+1.8V_RUN_VPP_FUSE"; |
fcacaba7 LD |
831 | regulator-min-microvolt = <1800000>; |
832 | regulator-max-microvolt = <1800000>; | |
833 | }; | |
834 | }; | |
835 | }; | |
9d5b2505 SW |
836 | }; |
837 | ||
b5896f67 | 838 | spi@7000d400 { |
146db0ea TR |
839 | status = "okay"; |
840 | ||
f01dd55a | 841 | cros_ec: cros-ec@0 { |
146db0ea TR |
842 | compatible = "google,cros-ec-spi"; |
843 | spi-max-frequency = <4000000>; | |
844 | interrupt-parent = <&gpio>; | |
845 | interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; | |
846 | reg = <0>; | |
847 | ||
848 | google,cros-ec-spi-msg-delay = <2000>; | |
72ceddda DA |
849 | |
850 | i2c-tunnel { | |
851 | compatible = "google,cros-ec-i2c-tunnel"; | |
852 | #address-cells = <1>; | |
853 | #size-cells = <0>; | |
854 | ||
855 | google,remote-bus = <0>; | |
856 | ||
857 | charger: bq24735@9 { | |
858 | compatible = "ti,bq24735"; | |
859 | reg = <0x9>; | |
860 | interrupt-parent = <&gpio>; | |
861 | interrupts = <TEGRA_GPIO(J, 0) | |
b604ef9c | 862 | IRQ_TYPE_EDGE_BOTH>; |
72ceddda DA |
863 | ti,ac-detect-gpios = <&gpio |
864 | TEGRA_GPIO(J, 0) | |
865 | GPIO_ACTIVE_HIGH>; | |
866 | }; | |
867 | ||
868 | battery: sbs-battery@b { | |
869 | compatible = "sbs,sbs-battery"; | |
870 | reg = <0xb>; | |
871 | sbs,i2c-retry-count = <2>; | |
872 | sbs,poll-retry-count = <1>; | |
873 | }; | |
874 | }; | |
146db0ea TR |
875 | }; |
876 | }; | |
877 | ||
b5896f67 | 878 | spi@7000da00 { |
11e5b4f9 SW |
879 | status = "okay"; |
880 | spi-max-frequency = <25000000>; | |
881 | spi-flash@0 { | |
882 | compatible = "winbond,w25q32dw"; | |
883 | reg = <0>; | |
884 | spi-max-frequency = <20000000>; | |
885 | }; | |
886 | }; | |
887 | ||
b5896f67 | 888 | pmc@7000e400 { |
a1425d42 | 889 | nvidia,invert-interrupt; |
6ec1d127 JL |
890 | nvidia,suspend-mode = <1>; |
891 | nvidia,cpu-pwr-good-time = <500>; | |
892 | nvidia,cpu-pwr-off-time = <300>; | |
893 | nvidia,core-pwr-good-time = <641 3845>; | |
894 | nvidia,core-pwr-off-time = <61036>; | |
895 | nvidia,core-power-req-active-high; | |
896 | nvidia,sys-clock-req-active-high; | |
a1425d42 | 897 | }; |
3b86baf2 | 898 | |
b5896f67 | 899 | hda@70030000 { |
0f3d3bf8 DR |
900 | status = "okay"; |
901 | }; | |
902 | ||
b5896f67 MZ |
903 | usb@70090000 { |
904 | phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ | |
905 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ | |
906 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ | |
907 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ | |
908 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ | |
4da6b31f TR |
909 | phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; |
910 | ||
911 | avddio-pex-supply = <&vdd_1v05_run>; | |
912 | dvddio-pex-supply = <&vdd_1v05_run>; | |
913 | avdd-usb-supply = <&vdd_3v3_lp0>; | |
914 | avdd-pll-utmip-supply = <&vddio_1v8>; | |
915 | avdd-pll-erefe-supply = <&avdd_1v05_run>; | |
916 | avdd-usb-ss-pll-supply = <&vdd_1v05_run>; | |
917 | hvdd-usb-ss-supply = <&vdd_3v3_lp0>; | |
918 | hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; | |
919 | ||
920 | status = "okay"; | |
921 | }; | |
922 | ||
b5896f67 | 923 | padctl@7009f000 { |
4da6b31f TR |
924 | pads { |
925 | usb2 { | |
926 | status = "okay"; | |
927 | ||
928 | lanes { | |
929 | usb2-0 { | |
930 | nvidia,function = "xusb"; | |
931 | status = "okay"; | |
932 | }; | |
933 | ||
934 | usb2-1 { | |
935 | nvidia,function = "xusb"; | |
936 | status = "okay"; | |
937 | }; | |
938 | ||
939 | usb2-2 { | |
940 | nvidia,function = "xusb"; | |
941 | status = "okay"; | |
942 | }; | |
943 | }; | |
944 | }; | |
945 | ||
946 | pcie { | |
947 | status = "okay"; | |
948 | ||
949 | lanes { | |
950 | pcie-0 { | |
951 | nvidia,function = "usb3-ss"; | |
952 | status = "okay"; | |
953 | }; | |
954 | ||
955 | pcie-1 { | |
956 | nvidia,function = "usb3-ss"; | |
957 | status = "okay"; | |
958 | }; | |
4da6b31f TR |
959 | }; |
960 | }; | |
961 | }; | |
962 | ||
963 | ports { | |
964 | usb2-0 { | |
965 | status = "okay"; | |
966 | mode = "otg"; | |
967 | ||
968 | vbus-supply = <&vdd_usb1_vbus>; | |
969 | }; | |
970 | ||
971 | usb2-1 { | |
972 | status = "okay"; | |
973 | mode = "host"; | |
974 | ||
975 | vbus-supply = <&vdd_run_cam>; | |
976 | }; | |
977 | ||
978 | usb2-2 { | |
979 | status = "okay"; | |
980 | mode = "host"; | |
981 | ||
982 | vbus-supply = <&vdd_usb3_vbus>; | |
983 | }; | |
984 | ||
985 | usb3-0 { | |
986 | nvidia,usb2-companion = <0>; | |
987 | status = "okay"; | |
988 | }; | |
989 | ||
990 | usb3-1 { | |
991 | nvidia,usb2-companion = <2>; | |
992 | status = "okay"; | |
993 | }; | |
994 | }; | |
995 | }; | |
996 | ||
b5896f67 | 997 | sdhci@700b0400 { |
784c7444 SW |
998 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
999 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | |
2be8f4a6 | 1000 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; |
784c7444 SW |
1001 | status = "okay"; |
1002 | bus-width = <4>; | |
49228cae | 1003 | vqmmc-supply = <&vddio_sdmmc3>; |
784c7444 SW |
1004 | }; |
1005 | ||
b5896f67 | 1006 | sdhci@700b0600 { |
784c7444 SW |
1007 | status = "okay"; |
1008 | bus-width = <8>; | |
ecb53f51 | 1009 | non-removable; |
784c7444 SW |
1010 | }; |
1011 | ||
b5896f67 MZ |
1012 | ahub@70300000 { |
1013 | i2s@70301100 { | |
b0e1caee SW |
1014 | status = "okay"; |
1015 | }; | |
1016 | }; | |
1017 | ||
b5896f67 | 1018 | usb@7d000000 { |
431b7be0 TR |
1019 | status = "okay"; |
1020 | }; | |
1021 | ||
b5896f67 | 1022 | usb-phy@7d000000 { |
431b7be0 TR |
1023 | status = "okay"; |
1024 | vbus-supply = <&vdd_usb1_vbus>; | |
1025 | }; | |
1026 | ||
b5896f67 | 1027 | usb@7d004000 { |
431b7be0 TR |
1028 | status = "okay"; |
1029 | }; | |
1030 | ||
b5896f67 | 1031 | usb-phy@7d004000 { |
431b7be0 TR |
1032 | status = "okay"; |
1033 | vbus-supply = <&vdd_run_cam>; | |
1034 | }; | |
1035 | ||
b5896f67 | 1036 | usb@7d008000 { |
431b7be0 TR |
1037 | status = "okay"; |
1038 | }; | |
1039 | ||
b5896f67 | 1040 | usb-phy@7d008000 { |
431b7be0 TR |
1041 | status = "okay"; |
1042 | vbus-supply = <&vdd_usb3_vbus>; | |
1043 | }; | |
1044 | ||
40e231c7 TR |
1045 | backlight: backlight { |
1046 | compatible = "pwm-backlight"; | |
1047 | ||
1048 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; | |
1049 | power-supply = <&vdd_led>; | |
1050 | pwms = <&pwm 1 1000000>; | |
1051 | ||
1052 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
1053 | default-brightness-level = <6>; | |
1054 | }; | |
1055 | ||
3b86baf2 JL |
1056 | clocks { |
1057 | compatible = "simple-bus"; | |
1058 | #address-cells = <1>; | |
1059 | #size-cells = <0>; | |
1060 | ||
1061 | clk32k_in: clock@0 { | |
1062 | compatible = "fixed-clock"; | |
4b356608 | 1063 | reg = <0>; |
3b86baf2 JL |
1064 | #clock-cells = <0>; |
1065 | clock-frequency = <32768>; | |
1066 | }; | |
1067 | }; | |
b0e1caee | 1068 | |
3f748d44 TR |
1069 | gpio-keys { |
1070 | compatible = "gpio-keys"; | |
1071 | ||
1072 | power { | |
1073 | label = "Power"; | |
1074 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | |
1075 | linux,code = <KEY_POWER>; | |
1076 | debounce-interval = <10>; | |
d1c04d30 | 1077 | wakeup-source; |
3f748d44 TR |
1078 | }; |
1079 | }; | |
1080 | ||
40e231c7 TR |
1081 | panel: panel { |
1082 | compatible = "lg,lp129qe", "simple-panel"; | |
1083 | ||
1084 | backlight = <&backlight>; | |
1085 | ddc-i2c-bus = <&dpaux>; | |
1086 | }; | |
1087 | ||
fcacaba7 LD |
1088 | regulators { |
1089 | compatible = "simple-bus"; | |
1090 | #address-cells = <1>; | |
1091 | #size-cells = <0>; | |
1092 | ||
af144b8d | 1093 | vdd_mux: regulator@0 { |
fcacaba7 LD |
1094 | compatible = "regulator-fixed"; |
1095 | reg = <0>; | |
af144b8d TR |
1096 | regulator-name = "+VDD_MUX"; |
1097 | regulator-min-microvolt = <12000000>; | |
1098 | regulator-max-microvolt = <12000000>; | |
fcacaba7 | 1099 | regulator-always-on; |
af144b8d | 1100 | regulator-boot-on; |
fcacaba7 LD |
1101 | }; |
1102 | ||
af144b8d | 1103 | vdd_5v0_sys: regulator@1 { |
fcacaba7 LD |
1104 | compatible = "regulator-fixed"; |
1105 | reg = <1>; | |
af144b8d TR |
1106 | regulator-name = "+5V_SYS"; |
1107 | regulator-min-microvolt = <5000000>; | |
1108 | regulator-max-microvolt = <5000000>; | |
fcacaba7 LD |
1109 | regulator-always-on; |
1110 | regulator-boot-on; | |
af144b8d | 1111 | vin-supply = <&vdd_mux>; |
fcacaba7 LD |
1112 | }; |
1113 | ||
af144b8d | 1114 | vdd_3v3_sys: regulator@2 { |
fcacaba7 LD |
1115 | compatible = "regulator-fixed"; |
1116 | reg = <2>; | |
af144b8d | 1117 | regulator-name = "+3.3V_SYS"; |
fcacaba7 LD |
1118 | regulator-min-microvolt = <3300000>; |
1119 | regulator-max-microvolt = <3300000>; | |
af144b8d TR |
1120 | regulator-always-on; |
1121 | regulator-boot-on; | |
1122 | vin-supply = <&vdd_mux>; | |
fcacaba7 LD |
1123 | }; |
1124 | ||
af144b8d | 1125 | vdd_3v3_run: regulator@3 { |
fcacaba7 LD |
1126 | compatible = "regulator-fixed"; |
1127 | reg = <3>; | |
af144b8d TR |
1128 | regulator-name = "+3.3V_RUN"; |
1129 | regulator-min-microvolt = <3300000>; | |
1130 | regulator-max-microvolt = <3300000>; | |
c7fe7672 SW |
1131 | regulator-always-on; |
1132 | regulator-boot-on; | |
fdc44f94 | 1133 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
fcacaba7 | 1134 | enable-active-high; |
af144b8d | 1135 | vin-supply = <&vdd_3v3_sys>; |
fcacaba7 LD |
1136 | }; |
1137 | ||
af144b8d | 1138 | vdd_3v3_hdmi: regulator@4 { |
fcacaba7 LD |
1139 | compatible = "regulator-fixed"; |
1140 | reg = <4>; | |
af144b8d | 1141 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; |
fcacaba7 LD |
1142 | regulator-min-microvolt = <3300000>; |
1143 | regulator-max-microvolt = <3300000>; | |
af144b8d | 1144 | vin-supply = <&vdd_3v3_run>; |
fcacaba7 LD |
1145 | }; |
1146 | ||
af144b8d | 1147 | vdd_led: regulator@5 { |
fcacaba7 LD |
1148 | compatible = "regulator-fixed"; |
1149 | reg = <5>; | |
af144b8d | 1150 | regulator-name = "+VDD_LED"; |
467b9b56 TR |
1151 | regulator-min-microvolt = <3300000>; |
1152 | regulator-max-microvolt = <3300000>; | |
af144b8d | 1153 | gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; |
fcacaba7 | 1154 | enable-active-high; |
af144b8d | 1155 | vin-supply = <&vdd_mux>; |
fcacaba7 LD |
1156 | }; |
1157 | ||
af144b8d | 1158 | vdd_5v0_ts: regulator@6 { |
fcacaba7 LD |
1159 | compatible = "regulator-fixed"; |
1160 | reg = <6>; | |
af144b8d | 1161 | regulator-name = "+5V_VDD_TS_SW"; |
fcacaba7 LD |
1162 | regulator-min-microvolt = <5000000>; |
1163 | regulator-max-microvolt = <5000000>; | |
1164 | regulator-boot-on; | |
af144b8d | 1165 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; |
fcacaba7 | 1166 | enable-active-high; |
af144b8d | 1167 | vin-supply = <&vdd_5v0_sys>; |
fcacaba7 LD |
1168 | }; |
1169 | ||
af144b8d | 1170 | vdd_usb1_vbus: regulator@7 { |
fcacaba7 LD |
1171 | compatible = "regulator-fixed"; |
1172 | reg = <7>; | |
af144b8d | 1173 | regulator-name = "+5V_USB_HS"; |
fcacaba7 LD |
1174 | regulator-min-microvolt = <5000000>; |
1175 | regulator-max-microvolt = <5000000>; | |
af144b8d | 1176 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; |
fcacaba7 | 1177 | enable-active-high; |
fcacaba7 | 1178 | gpio-open-drain; |
af144b8d | 1179 | vin-supply = <&vdd_5v0_sys>; |
fcacaba7 LD |
1180 | }; |
1181 | ||
af144b8d | 1182 | vdd_usb3_vbus: regulator@8 { |
fcacaba7 LD |
1183 | compatible = "regulator-fixed"; |
1184 | reg = <8>; | |
af144b8d TR |
1185 | regulator-name = "+5V_USB_SS"; |
1186 | regulator-min-microvolt = <5000000>; | |
1187 | regulator-max-microvolt = <5000000>; | |
1188 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; | |
1189 | enable-active-high; | |
1190 | gpio-open-drain; | |
1191 | vin-supply = <&vdd_5v0_sys>; | |
1192 | }; | |
1193 | ||
1194 | vdd_3v3_panel: regulator@9 { | |
1195 | compatible = "regulator-fixed"; | |
1196 | reg = <9>; | |
1197 | regulator-name = "+3.3V_PANEL"; | |
fcacaba7 LD |
1198 | regulator-min-microvolt = <3300000>; |
1199 | regulator-max-microvolt = <3300000>; | |
fdc44f94 | 1200 | gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; |
af144b8d TR |
1201 | enable-active-high; |
1202 | vin-supply = <&vdd_3v3_run>; | |
1203 | }; | |
1204 | ||
1205 | vdd_3v3_lp0: regulator@10 { | |
1206 | compatible = "regulator-fixed"; | |
1207 | reg = <10>; | |
1208 | regulator-name = "+3.3V_LP0"; | |
1209 | regulator-min-microvolt = <3300000>; | |
1210 | regulator-max-microvolt = <3300000>; | |
1211 | /* | |
1212 | * TODO: find a way to wire this up with the USB EHCI | |
1213 | * controllers so that it can be enabled on demand. | |
1214 | */ | |
1215 | regulator-always-on; | |
fdc44f94 | 1216 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; |
fcacaba7 | 1217 | enable-active-high; |
af144b8d | 1218 | vin-supply = <&vdd_3v3_sys>; |
fcacaba7 | 1219 | }; |
329c39f8 TR |
1220 | |
1221 | vdd_hdmi_pll: regulator@11 { | |
1222 | compatible = "regulator-fixed"; | |
1223 | reg = <11>; | |
1224 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; | |
1225 | regulator-min-microvolt = <1050000>; | |
1226 | regulator-max-microvolt = <1050000>; | |
1227 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; | |
1228 | vin-supply = <&vdd_1v05_run>; | |
1229 | }; | |
1230 | ||
1231 | vdd_5v0_hdmi: regulator@12 { | |
1232 | compatible = "regulator-fixed"; | |
1233 | reg = <12>; | |
1234 | regulator-name = "+5V_HDMI_CON"; | |
1235 | regulator-min-microvolt = <5000000>; | |
1236 | regulator-max-microvolt = <5000000>; | |
1237 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | |
1238 | enable-active-high; | |
1239 | vin-supply = <&vdd_5v0_sys>; | |
1240 | }; | |
fcacaba7 LD |
1241 | }; |
1242 | ||
b0e1caee SW |
1243 | sound { |
1244 | compatible = "nvidia,tegra-audio-max98090-venice2", | |
1245 | "nvidia,tegra-audio-max98090"; | |
1246 | nvidia,model = "NVIDIA Tegra Venice2"; | |
1247 | ||
1248 | nvidia,audio-routing = | |
1249 | "Headphones", "HPR", | |
1250 | "Headphones", "HPL", | |
1251 | "Speakers", "SPKR", | |
1252 | "Speakers", "SPKL", | |
1253 | "Mic Jack", "MICBIAS", | |
1254 | "IN34", "Mic Jack"; | |
1255 | ||
1256 | nvidia,i2s-controller = <&tegra_i2s1>; | |
1257 | nvidia,audio-codec = <&acodec>; | |
1258 | ||
1259 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | |
1260 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
1261 | <&tegra_car TEGRA124_CLK_EXTERN1>; | |
1262 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
1263 | }; | |
a1425d42 | 1264 | }; |
f01dd55a DA |
1265 | |
1266 | #include "cros-ec-keyboard.dtsi" |