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ARM: tegra: Overhaul Venice2 regulators
[linux-2.6-block.git] / arch / arm / boot / dts / tegra124-venice2.dts
CommitLineData
a1425d42
JL		 1/dts-v1/;
2
146db0ea 3#include <dt-bindings/input/input.h>
a1425d42
JL		 4#include "tegra124.dtsi"
5
6/ {
7 model = "NVIDIA Tegra124 Venice2";
8 compatible = "nvidia,venice2", "nvidia,tegra124";
9
b1afa782
SW		 10 aliases {
11 rtc0 = "/i2c@7000d000/as3722@40";
12 rtc1 = "/rtc@7000e000";
13 };
14
a1425d42
JL		 15 memory {
16 reg = <0x80000000 0x80000000>;
17 };
18
4b20bcbe
LD		 19 pinmux: pinmux@70000868 {
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinmux_default>;
22
23 pinmux_default: common {
24 dap_mclk1_pw4 {
25 nvidia,pins = "dap_mclk1_pw4";
26 nvidia,function = "extperiph1";
27 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
28 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
29 nvidia,tristate = <TEGRA_PIN_DISABLE>;
30 };
31 dap1_din_pn1 {
365c483f
LD		 32 nvidia,pins = "dap1_din_pn1";
33 nvidia,function = "i2s0";
34 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
36 nvidia,tristate = <TEGRA_PIN_ENABLE>;
37 };
38 dap1_dout_pn2 {
39 nvidia,pins = "dap1_dout_pn2",
4b20bcbe
LD		 40 "dap1_fs_pn0",
41 "dap1_sclk_pn3";
42 nvidia,function = "i2s0";
365c483f 43 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 44 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
45 nvidia,tristate = <TEGRA_PIN_ENABLE>;
46 };
47 dap2_din_pa4 {
365c483f 48 nvidia,pins = "dap2_din_pa4";
4b20bcbe
LD		 49 nvidia,function = "i2s1";
50 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4ffb9385 52 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe 53 };
365c483f
LD		 54 dap2_dout_pa5 {
55 nvidia,pins = "dap2_dout_pa5",
56 "dap2_fs_pa2",
57 "dap2_sclk_pa3";
58 nvidia,function = "i2s1";
4b20bcbe
LD		 59 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
365c483f 61 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe 62 };
365c483f
LD		 63 dvfs_pwm_px0 {
64 nvidia,pins = "dvfs_pwm_px0",
65 "dvfs_clk_px2";
4b20bcbe
LD		 66 nvidia,function = "cldvfs";
67 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
69 nvidia,tristate = <TEGRA_PIN_DISABLE>;
70 };
71 ulpi_clk_py0 {
72 nvidia,pins = "ulpi_clk_py0",
4b20bcbe
LD		 73 "ulpi_nxt_py2",
74 "ulpi_stp_py3";
75 nvidia,function = "spi1";
365c483f
LD		 76 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
77 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
79 };
80 ulpi_dir_py1 {
81 nvidia,pins = "ulpi_dir_py1";
82 nvidia,function = "spi1";
4b20bcbe 83 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
365c483f 84 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4b20bcbe
LD		 85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
86 };
87 cam_i2c_scl_pbb1 {
88 nvidia,pins = "cam_i2c_scl_pbb1",
89 "cam_i2c_sda_pbb2";
90 nvidia,function = "i2c3";
91 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93 nvidia,tristate = <TEGRA_PIN_DISABLE>;
94 nvidia,lock = <TEGRA_PIN_DISABLE>;
95 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
96 };
97 gen2_i2c_scl_pt5 {
98 nvidia,pins = "gen2_i2c_scl_pt5",
99 "gen2_i2c_sda_pt6";
100 nvidia,function = "i2c2";
101 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
102 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103 nvidia,tristate = <TEGRA_PIN_DISABLE>;
104 nvidia,lock = <TEGRA_PIN_DISABLE>;
105 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
106 };
107 pg4 {
108 nvidia,pins = "pg4",
109 "pg5",
110 "pg6",
4b20bcbe
LD		 111 "pi3";
112 nvidia,function = "spi4";
113 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
114 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
115 nvidia,tristate = <TEGRA_PIN_DISABLE>;
116 };
365c483f
LD		 117 pg7 {
118 nvidia,pins = "pg7";
119 nvidia,function = "spi4";
4b20bcbe 120 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
365c483f
LD		 121 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
122 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 123 };
124 ph1 {
125 nvidia,pins = "ph1";
126 nvidia,function = "pwm1";
127 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
128 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
129 nvidia,tristate = <TEGRA_PIN_DISABLE>;
130 };
365c483f
LD		 131 pk0 {
132 nvidia,pins = "pk0",
133 "kb_row15_ps7",
134 "clk_32k_out_pa0";
135 nvidia,function = "soc";
136 nvidia,pull = <TEGRA_PIN_PULL_UP>;
f5cb19b4 137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f 138 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
f5cb19b4 139 };
4b20bcbe
LD		 140 sdmmc1_clk_pz0 {
141 nvidia,pins = "sdmmc1_clk_pz0",
142 "sdmmc1_cmd_pz1",
143 "sdmmc1_dat0_py7",
144 "sdmmc1_dat1_py6",
145 "sdmmc1_dat2_py5",
146 "sdmmc1_dat3_py4";
147 nvidia,function = "sdmmc1";
148 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
149 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
150 nvidia,tristate = <TEGRA_PIN_DISABLE>;
151 };
365c483f
LD		 152 sdmmc1_cmd_pz1 {
153 nvidia,pins = "sdmmc1_cmd_pz1",
154 "sdmmc1_dat0_py7",
155 "sdmmc1_dat1_py6",
156 "sdmmc1_dat2_py5",
157 "sdmmc1_dat3_py4";
158 nvidia,function = "sdmmc1";
159 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
160 nvidia,pull = <TEGRA_PIN_PULL_UP>;
161 nvidia,tristate = <TEGRA_PIN_DISABLE>;
162 };
4b20bcbe
LD		 163 sdmmc3_clk_pa6 {
164 nvidia,pins = "sdmmc3_clk_pa6";
165 nvidia,function = "sdmmc3";
166 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
167 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 };
170 sdmmc3_cmd_pa7 {
171 nvidia,pins = "sdmmc3_cmd_pa7",
172 "sdmmc3_dat0_pb7",
173 "sdmmc3_dat1_pb6",
174 "sdmmc3_dat2_pb5",
175 "sdmmc3_dat3_pb4",
176 "sdmmc3_clk_lb_out_pee4",
177 "sdmmc3_clk_lb_in_pee5";
178 nvidia,function = "sdmmc3";
179 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
180 nvidia,pull = <TEGRA_PIN_PULL_UP>;
181 nvidia,tristate = <TEGRA_PIN_DISABLE>;
182 };
183 sdmmc4_clk_pcc4 {
184 nvidia,pins = "sdmmc4_clk_pcc4";
185 nvidia,function = "sdmmc4";
186 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
187 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
188 nvidia,tristate = <TEGRA_PIN_DISABLE>;
189 };
190 sdmmc4_cmd_pt7 {
191 nvidia,pins = "sdmmc4_cmd_pt7",
192 "sdmmc4_dat0_paa0",
193 "sdmmc4_dat1_paa1",
194 "sdmmc4_dat2_paa2",
195 "sdmmc4_dat3_paa3",
196 "sdmmc4_dat4_paa4",
197 "sdmmc4_dat5_paa5",
198 "sdmmc4_dat6_paa6",
199 "sdmmc4_dat7_paa7";
200 nvidia,function = "sdmmc4";
201 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
202 nvidia,pull = <TEGRA_PIN_PULL_UP>;
203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
204 };
205 pwr_i2c_scl_pz6 {
206 nvidia,pins = "pwr_i2c_scl_pz6",
207 "pwr_i2c_sda_pz7";
208 nvidia,function = "i2cpwr";
209 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
210 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
211 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f 212 nvidia,lock = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 213 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
214 };
215 jtag_rtck {
216 nvidia,pins = "jtag_rtck";
217 nvidia,function = "rtck";
218 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
219 nvidia,pull = <TEGRA_PIN_PULL_UP>;
220 nvidia,tristate = <TEGRA_PIN_DISABLE>;
221 };
222 clk_32k_in {
223 nvidia,pins = "clk_32k_in";
224 nvidia,function = "clk";
225 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 };
229 core_pwr_req {
230 nvidia,pins = "core_pwr_req";
231 nvidia,function = "pwron";
232 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
233 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 };
236 cpu_pwr_req {
237 nvidia,pins = "cpu_pwr_req";
238 nvidia,function = "cpu";
239 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
242 };
243 pwr_int_n {
244 nvidia,pins = "pwr_int_n";
245 nvidia,function = "pmi";
246 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
247 nvidia,pull = <TEGRA_PIN_PULL_UP>;
248 nvidia,tristate = <TEGRA_PIN_DISABLE>;
249 };
250 reset_out_n {
251 nvidia,pins = "reset_out_n";
252 nvidia,function = "reset_out_n";
253 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
254 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
256 };
257 clk3_out_pee0 {
258 nvidia,pins = "clk3_out_pee0";
259 nvidia,function = "extperiph3";
260 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
261 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
263 };
264 dap4_din_pp5 {
365c483f
LD		 265 nvidia,pins = "dap4_din_pp5";
266 nvidia,function = "i2s3";
267 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 nvidia,tristate = <TEGRA_PIN_ENABLE>;
270 };
271 dap4_dout_pp6 {
272 nvidia,pins = "dap4_dout_pp6",
4b20bcbe
LD		 273 "dap4_fs_pp4",
274 "dap4_sclk_pp7";
275 nvidia,function = "i2s3";
365c483f 276 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 277 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
278 nvidia,tristate = <TEGRA_PIN_ENABLE>;
279 };
280 gen1_i2c_sda_pc5 {
281 nvidia,pins = "gen1_i2c_sda_pc5",
282 "gen1_i2c_scl_pc4";
283 nvidia,function = "i2c1";
284 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
285 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
287 nvidia,lock = <TEGRA_PIN_DISABLE>;
365c483f 288 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4b20bcbe 289 };
365c483f
LD		 290 uart2_cts_n_pj5 {
291 nvidia,pins = "uart2_cts_n_pj5";
292 nvidia,function = "uartb";
4b20bcbe 293 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4ffb9385 294 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4b20bcbe
LD		 295 nvidia,tristate = <TEGRA_PIN_DISABLE>;
296 };
365c483f
LD		 297 uart2_rts_n_pj6 {
298 nvidia,pins = "uart2_rts_n_pj6";
4b20bcbe 299 nvidia,function = "uartb";
365c483f 300 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 301 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
302 nvidia,tristate = <TEGRA_PIN_DISABLE>;
303 };
304 uart2_rxd_pc3 {
365c483f 305 nvidia,pins = "uart2_rxd_pc3";
4b20bcbe
LD		 306 nvidia,function = "irda";
307 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
308 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
309 nvidia,tristate = <TEGRA_PIN_DISABLE>;
310 };
365c483f
LD		 311 uart2_txd_pc2 {
312 nvidia,pins = "uart2_txd_pc2";
313 nvidia,function = "irda";
314 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
315 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316 nvidia,tristate = <TEGRA_PIN_DISABLE>;
317 };
4b20bcbe
LD		 318 uart3_cts_n_pa1 {
319 nvidia,pins = "uart3_cts_n_pa1",
365c483f 320 "uart3_rxd_pw7";
4b20bcbe
LD		 321 nvidia,function = "uartc";
322 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
323 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
324 nvidia,tristate = <TEGRA_PIN_DISABLE>;
325 };
365c483f
LD		 326 uart3_rts_n_pc0 {
327 nvidia,pins = "uart3_rts_n_pc0",
328 "uart3_txd_pw6";
329 nvidia,function = "uartc";
330 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
331 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
332 nvidia,tristate = <TEGRA_PIN_DISABLE>;
333 };
4b20bcbe
LD		 334 hdmi_cec_pee3 {
335 nvidia,pins = "hdmi_cec_pee3";
336 nvidia,function = "cec";
337 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
338 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
339 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f
LD		 340 nvidia,lock = <TEGRA_PIN_DISABLE>;
341 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
342 };
343 hdmi_int_pn7 {
344 nvidia,pins = "hdmi_int_pn7";
345 nvidia,function = "rsvd1";
346 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
347 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
348 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 349 };
350 ddc_scl_pv4 {
351 nvidia,pins = "ddc_scl_pv4",
352 "ddc_sda_pv5";
353 nvidia,function = "i2c4";
354 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
355 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
356 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f
LD		 357 nvidia,lock = <TEGRA_PIN_DISABLE>;
358 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
359 };
360 pj7 {
361 nvidia,pins = "pj7",
362 "pk7";
363 nvidia,function = "uartd";
364 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
365 nvidia,tristate = <TEGRA_PIN_DISABLE>;
366 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
367 };
368 pb0 {
369 nvidia,pins = "pb0",
370 "pb1";
371 nvidia,function = "uartd";
372 nvidia,pull = <TEGRA_PIN_PULL_UP>;
373 nvidia,tristate = <TEGRA_PIN_DISABLE>;
374 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
375 };
376 ph0 {
377 nvidia,pins = "ph0";
378 nvidia,function = "pwm0";
379 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
380 nvidia,tristate = <TEGRA_PIN_DISABLE>;
381 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
382 };
383 kb_row10_ps2 {
384 nvidia,pins = "kb_row10_ps2";
385 nvidia,function = "uarta";
386 nvidia,pull = <TEGRA_PIN_PULL_UP>;
387 nvidia,tristate = <TEGRA_PIN_DISABLE>;
388 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
389 };
390 kb_row9_ps1 {
391 nvidia,pins = "kb_row9_ps1";
392 nvidia,function = "uarta";
393 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
394 nvidia,tristate = <TEGRA_PIN_DISABLE>;
395 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
396 };
397 kb_row6_pr6 {
398 nvidia,pins = "kb_row6_pr6";
399 nvidia,function = "displaya_alt";
400 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
401 nvidia,tristate = <TEGRA_PIN_DISABLE>;
402 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4b20bcbe
LD		 403 };
404 usb_vbus_en0_pn4 {
fa15ffaa
TR		 405 nvidia,pins = "usb_vbus_en0_pn4",
406 "usb_vbus_en1_pn5";
4b20bcbe
LD		 407 nvidia,function = "usb";
408 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
fa15ffaa 409 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4b20bcbe
LD		 410 nvidia,tristate = <TEGRA_PIN_DISABLE>;
411 nvidia,lock = <TEGRA_PIN_DISABLE>;
365c483f 412 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4b20bcbe
LD		 413 };
414 drive_sdio1 {
415 nvidia,pins = "drive_sdio1";
416 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
417 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
418 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
419 nvidia,pull-down-strength = <32>;
420 nvidia,pull-up-strength = <42>;
421 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
422 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
423 };
424 drive_sdio3 {
425 nvidia,pins = "drive_sdio3";
426 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
427 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
428 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
429 nvidia,pull-down-strength = <20>;
430 nvidia,pull-up-strength = <36>;
431 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
432 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
433 };
434 drive_gma {
435 nvidia,pins = "drive_gma";
436 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
437 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
438 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
439 nvidia,pull-down-strength = <1>;
440 nvidia,pull-up-strength = <2>;
441 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
442 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
443 nvidia,drive-type = <1>;
444 };
365c483f
LD		 445 als_irq_l {
446 nvidia,pins = "gpio_x3_aud_px3";
447 nvidia,function = "gmi";
448 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
449 nvidia,tristate = <TEGRA_PIN_ENABLE>;
450 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
451 };
452 codec_irq_l {
453 nvidia,pins = "ph4";
454 nvidia,function = "gmi";
455 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
456 nvidia,tristate = <TEGRA_PIN_DISABLE>;
457 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
458 };
459 lcd_bl_en {
460 nvidia,pins = "ph2";
461 nvidia,function = "gmi";
462 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
463 nvidia,tristate = <TEGRA_PIN_DISABLE>;
464 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
465 };
466 touch_irq_l {
467 nvidia,pins = "gpio_w3_aud_pw3";
468 nvidia,function = "spi6";
469 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
470 nvidia,tristate = <TEGRA_PIN_ENABLE>;
471 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
472 };
473 tpm_davint_l {
474 nvidia,pins = "ph6";
475 nvidia,function = "gmi";
476 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
477 nvidia,tristate = <TEGRA_PIN_ENABLE>;
478 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
479 };
480 ts_irq_l {
481 nvidia,pins = "pk2";
482 nvidia,function = "gmi";
483 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
484 nvidia,tristate = <TEGRA_PIN_ENABLE>;
485 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
486 };
487 ts_reset_l {
488 nvidia,pins = "pk4";
489 nvidia,function = "gmi";
490 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
491 nvidia,tristate = <TEGRA_PIN_DISABLE>;
492 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
493 };
494 ts_shdn_l {
495 nvidia,pins = "pk1";
496 nvidia,function = "gmi";
497 nvidia,pull = <TEGRA_PIN_PULL_UP>;
498 nvidia,tristate = <TEGRA_PIN_DISABLE>;
499 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
500 };
501 ph7 {
502 nvidia,pins = "ph7";
503 nvidia,function = "gmi";
504 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
505 nvidia,tristate = <TEGRA_PIN_DISABLE>;
506 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
507 };
508 kb_col0_ap {
509 nvidia,pins = "kb_col0_pq0";
510 nvidia,function = "rsvd4";
511 nvidia,pull = <TEGRA_PIN_PULL_UP>;
512 nvidia,tristate = <TEGRA_PIN_DISABLE>;
513 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
514 };
515 lid_open {
516 nvidia,pins = "kb_row4_pr4";
517 nvidia,function = "rsvd3";
518 nvidia,pull = <TEGRA_PIN_PULL_UP>;
519 nvidia,tristate = <TEGRA_PIN_DISABLE>;
520 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
521 };
522 en_vdd_sd {
523 nvidia,pins = "kb_row0_pr0";
524 nvidia,function = "rsvd4";
525 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
526 nvidia,tristate = <TEGRA_PIN_DISABLE>;
527 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
528 };
529 ac_ok {
530 nvidia,pins = "pj0";
531 nvidia,function = "gmi";
532 nvidia,pull = <TEGRA_PIN_PULL_UP>;
533 nvidia,tristate = <TEGRA_PIN_ENABLE>;
534 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
535 };
536 sensor_irq_l {
537 nvidia,pins = "pi6";
538 nvidia,function = "gmi";
539 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
540 nvidia,tristate = <TEGRA_PIN_DISABLE>;
541 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
542 };
543 wifi_en {
544 nvidia,pins = "gpio_x7_aud_px7";
545 nvidia,function = "rsvd4";
546 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
547 nvidia,tristate = <TEGRA_PIN_DISABLE>;
548 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
549 };
550 wifi_rst_l {
551 nvidia,pins = "clk2_req_pcc5";
552 nvidia,function = "dap";
553 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
554 nvidia,tristate = <TEGRA_PIN_DISABLE>;
555 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
556 };
557 hp_det_l {
558 nvidia,pins = "ulpi_data1_po2";
559 nvidia,function = "spi3";
560 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
561 nvidia,tristate = <TEGRA_PIN_DISABLE>;
562 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
563 };
4b20bcbe
LD		 564 };
565 };
566
a1425d42
JL		 567 serial@70006000 {
568 status = "okay";
569 };
570
e013485d
TR		 571 pwm: pwm@7000a000 {
572 status = "okay";
573 };
574
9d5b2505
SW		 575 i2c@7000c000 {
576 status = "okay";
577 clock-frequency = <100000>;
b0e1caee
SW		 578
579 acodec: audio-codec@10 {
580 compatible = "maxim,max98090";
581 reg = <0x10>;
582 interrupt-parent = <&gpio>;
583 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
584 };
9d5b2505
SW		 585 };
586
587 i2c@7000c400 {
588 status = "okay";
589 clock-frequency = <100000>;
590 };
591
592 i2c@7000c500 {
593 status = "okay";
594 clock-frequency = <100000>;
595 };
596
597 i2c@7000c700 {
598 status = "okay";
599 clock-frequency = <100000>;
600 };
601
602 i2c@7000d000 {
603 status = "okay";
fcacaba7
LD		 604 clock-frequency = <400000>;
605
606 as3722: as3722@40 {
607 compatible = "ams,as3722";
608 reg = <0x40>;
609 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
610
7be75df2
LD		 611 ams,system-power-controller;
612
fcacaba7
LD		 613 #interrupt-cells = <2>;
614 interrupt-controller;
615
616 gpio-controller;
617 #gpio-cells = <2>;
618
619 pinctrl-names = "default";
620 pinctrl-0 = <&as3722_default>;
621
622 as3722_default: pinmux {
623 gpio0 {
624 pins = "gpio0";
625 function = "gpio";
626 bias-pull-down;
627 };
628
629 gpio1_2_4_7 {
630 pins = "gpio1", "gpio2", "gpio4", "gpio7";
631 function = "gpio";
632 bias-pull-up;
633 };
634
635 gpio3_6 {
636 pins = "gpio3", "gpio6";
637 bias-high-impedance;
638 };
639
640 gpio5 {
641 pins = "gpio5";
642 function = "clk32k-out";
643 };
644 };
645
646 regulators {
af144b8d
TR		 647 vsup-sd2-supply = <&vdd_5v0_sys>;
648 vsup-sd3-supply = <&vdd_5v0_sys>;
649 vsup-sd4-supply = <&vdd_5v0_sys>;
650 vsup-sd5-supply = <&vdd_5v0_sys>;
651 vin-ldo0-supply = <&vdd_1v35_lp0>;
652 vin-ldo1-6-supply = <&vdd_3v3_run>;
653 vin-ldo2-5-7-supply = <&vddio_1v8>;
654 vin-ldo3-4-supply = <&vdd_3v3_sys>;
655 vin-ldo9-10-supply = <&vdd_5v0_sys>;
656 vin-ldo11-supply = <&vdd_3v3_run>;
fcacaba7
LD		 657
658 sd0 {
af144b8d 659 regulator-name = "+VDD_CPU_AP";
fcacaba7
LD		 660 regulator-min-microvolt = <700000>;
661 regulator-max-microvolt = <1400000>;
662 regulator-min-microamp = <3500000>;
663 regulator-max-microamp = <3500000>;
664 regulator-always-on;
665 regulator-boot-on;
666 ams,external-control = <2>;
667 };
668
669 sd1 {
af144b8d 670 regulator-name = "+VDD_CORE";
fcacaba7
LD		 671 regulator-min-microvolt = <700000>;
672 regulator-max-microvolt = <1350000>;
673 regulator-min-microamp = <2500000>;
674 regulator-max-microamp = <2500000>;
675 regulator-always-on;
676 regulator-boot-on;
677 ams,external-control = <1>;
678 };
679
af144b8d
TR		 680 vdd_1v35_lp0: sd2 {
681 regulator-name = "+1.35V_LP0(sd2)";
fcacaba7
LD		 682 regulator-min-microvolt = <1350000>;
683 regulator-max-microvolt = <1350000>;
684 regulator-always-on;
685 regulator-boot-on;
686 };
687
688 sd3 {
af144b8d 689 regulator-name = "+1.35V_LP0(sd3)";
fcacaba7
LD		 690 regulator-min-microvolt = <1350000>;
691 regulator-max-microvolt = <1350000>;
692 regulator-always-on;
693 regulator-boot-on;
694 };
695
696 sd4 {
af144b8d 697 regulator-name = "+1.05V_RUN";
fcacaba7
LD		 698 regulator-min-microvolt = <1050000>;
699 regulator-max-microvolt = <1050000>;
fcacaba7
LD		 700 };
701
af144b8d
TR		 702 vddio_1v8: sd5 {
703 regulator-name = "+1.8V_VDDIO";
fcacaba7
LD		 704 regulator-min-microvolt = <1800000>;
705 regulator-max-microvolt = <1800000>;
706 regulator-boot-on;
707 regulator-always-on;
708 };
709
710 sd6 {
af144b8d 711 regulator-name = "+VDD_GPU_AP";
fcacaba7
LD		 712 regulator-min-microvolt = <650000>;
713 regulator-max-microvolt = <1200000>;
714 regulator-min-microamp = <3500000>;
715 regulator-max-microamp = <3500000>;
716 regulator-boot-on;
717 regulator-always-on;
718 };
719
720 ldo0 {
af144b8d 721 regulator-name = "+1.05V_RUN_AVDD";
fcacaba7
LD		 722 regulator-min-microvolt = <1050000>;
723 regulator-max-microvolt = <1050000>;
724 regulator-boot-on;
725 regulator-always-on;
726 ams,external-control = <1>;
727 };
728
729 ldo1 {
af144b8d 730 regulator-name = "+1.8V_RUN_CAM";
fcacaba7
LD		 731 regulator-min-microvolt = <1800000>;
732 regulator-max-microvolt = <1800000>;
733 };
734
735 ldo2 {
af144b8d 736 regulator-name = "+1.2V_GEN_AVDD";
fcacaba7
LD		 737 regulator-min-microvolt = <1200000>;
738 regulator-max-microvolt = <1200000>;
739 regulator-boot-on;
740 regulator-always-on;
741 };
742
743 ldo3 {
af144b8d 744 regulator-name = "+1.00V_LP0_VDD_RTC";
fcacaba7
LD		 745 regulator-min-microvolt = <1000000>;
746 regulator-max-microvolt = <1000000>;
747 regulator-boot-on;
748 regulator-always-on;
749 ams,enable-tracking;
750 };
751
752 ldo4 {
af144b8d 753 regulator-name = "+3.3V_RUN_CAM";
fcacaba7
LD		 754 regulator-min-microvolt = <2800000>;
755 regulator-max-microvolt = <2800000>;
fcacaba7
LD		 756 };
757
758 ldo5 {
af144b8d 759 regulator-name = "+1.2V_RUN_CAM_FRONT";
fcacaba7
LD		 760 regulator-min-microvolt = <1200000>;
761 regulator-max-microvolt = <1200000>;
762 };
763
764 ldo6 {
af144b8d 765 regulator-name = "+VDDIO_SDMMC3";
fcacaba7
LD		 766 regulator-min-microvolt = <1800000>;
767 regulator-max-microvolt = <3300000>;
768 regulator-boot-on;
769 regulator-always-on;
770 };
771
772 ldo7 {
af144b8d 773 regulator-name = "+1.05V_RUN_CAM_REAR";
fcacaba7
LD		 774 regulator-min-microvolt = <1050000>;
775 regulator-max-microvolt = <1050000>;
776 };
777
778 ldo9 {
af144b8d 779 regulator-name = "+2.8V_RUN_TOUCH";
fcacaba7
LD		 780 regulator-min-microvolt = <2800000>;
781 regulator-max-microvolt = <2800000>;
782 };
783
784 ldo10 {
af144b8d 785 regulator-name = "+2.8V_RUN_CAM_AF";
fcacaba7
LD		 786 regulator-min-microvolt = <2800000>;
787 regulator-max-microvolt = <2800000>;
788 };
789
790 ldo11 {
af144b8d 791 regulator-name = "+1.8V_RUN_VPP_FUSE";
fcacaba7
LD		 792 regulator-min-microvolt = <1800000>;
793 regulator-max-microvolt = <1800000>;
794 };
795 };
796 };
9d5b2505
SW		 797 };
798
146db0ea
TR		 799 spi@7000d400 {
800 status = "okay";
801
802 cros-ec@0 {
803 compatible = "google,cros-ec-spi";
804 spi-max-frequency = <4000000>;
805 interrupt-parent = <&gpio>;
806 interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
807 reg = <0>;
808
809 google,cros-ec-spi-msg-delay = <2000>;
810
811 cros-ec-keyb {
812 compatible = "google,cros-ec-keyb";
813 keypad,num-rows = <8>;
814 keypad,num-columns = <13>;
815 google,needs-ghost-filter;
816
817 linux,keymap = <
818 MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
819 MATRIX_KEY(0x00, 0x02, KEY_F1)
820 MATRIX_KEY(0x00, 0x03, KEY_B)
821 MATRIX_KEY(0x00, 0x04, KEY_F10)
822 MATRIX_KEY(0x00, 0x06, KEY_N)
823 MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
824 MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
825
826 MATRIX_KEY(0x01, 0x01, KEY_ESC)
827 MATRIX_KEY(0x01, 0x02, KEY_F4)
828 MATRIX_KEY(0x01, 0x03, KEY_G)
829 MATRIX_KEY(0x01, 0x04, KEY_F7)
830 MATRIX_KEY(0x01, 0x06, KEY_H)
831 MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
832 MATRIX_KEY(0x01, 0x09, KEY_F9)
833 MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
834
835 MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
836 MATRIX_KEY(0x02, 0x01, KEY_TAB)
837 MATRIX_KEY(0x02, 0x02, KEY_F3)
838 MATRIX_KEY(0x02, 0x03, KEY_T)
839 MATRIX_KEY(0x02, 0x04, KEY_F6)
840 MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
841 MATRIX_KEY(0x02, 0x06, KEY_Y)
842 MATRIX_KEY(0x02, 0x07, KEY_102ND)
843 MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
844 MATRIX_KEY(0x02, 0x09, KEY_F8)
845
846 MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
847 MATRIX_KEY(0x03, 0x02, KEY_F2)
848 MATRIX_KEY(0x03, 0x03, KEY_5)
849 MATRIX_KEY(0x03, 0x04, KEY_F5)
850 MATRIX_KEY(0x03, 0x06, KEY_6)
851 MATRIX_KEY(0x03, 0x08, KEY_MINUS)
852 MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
853
854 MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
855 MATRIX_KEY(0x04, 0x01, KEY_A)
856 MATRIX_KEY(0x04, 0x02, KEY_D)
857 MATRIX_KEY(0x04, 0x03, KEY_F)
858 MATRIX_KEY(0x04, 0x04, KEY_S)
859 MATRIX_KEY(0x04, 0x05, KEY_K)
860 MATRIX_KEY(0x04, 0x06, KEY_J)
861 MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
862 MATRIX_KEY(0x04, 0x09, KEY_L)
863 MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
864 MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
865
866 MATRIX_KEY(0x05, 0x01, KEY_Z)
867 MATRIX_KEY(0x05, 0x02, KEY_C)
868 MATRIX_KEY(0x05, 0x03, KEY_V)
869 MATRIX_KEY(0x05, 0x04, KEY_X)
870 MATRIX_KEY(0x05, 0x05, KEY_COMMA)
871 MATRIX_KEY(0x05, 0x06, KEY_M)
872 MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
873 MATRIX_KEY(0x05, 0x08, KEY_SLASH)
874 MATRIX_KEY(0x05, 0x09, KEY_DOT)
875 MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
876
877 MATRIX_KEY(0x06, 0x01, KEY_1)
878 MATRIX_KEY(0x06, 0x02, KEY_3)
879 MATRIX_KEY(0x06, 0x03, KEY_4)
880 MATRIX_KEY(0x06, 0x04, KEY_2)
881 MATRIX_KEY(0x06, 0x05, KEY_8)
882 MATRIX_KEY(0x06, 0x06, KEY_7)
883 MATRIX_KEY(0x06, 0x08, KEY_0)
884 MATRIX_KEY(0x06, 0x09, KEY_9)
885 MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
886 MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
887 MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
888
889 MATRIX_KEY(0x07, 0x01, KEY_Q)
890 MATRIX_KEY(0x07, 0x02, KEY_E)
891 MATRIX_KEY(0x07, 0x03, KEY_R)
892 MATRIX_KEY(0x07, 0x04, KEY_W)
893 MATRIX_KEY(0x07, 0x05, KEY_I)
894 MATRIX_KEY(0x07, 0x06, KEY_U)
895 MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
896 MATRIX_KEY(0x07, 0x08, KEY_P)
897 MATRIX_KEY(0x07, 0x09, KEY_O)
898 MATRIX_KEY(0x07, 0x0b, KEY_UP)
899 MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
900 >;
901 };
902 };
903 };
904
11e5b4f9
SW		 905 spi@7000da00 {
906 status = "okay";
907 spi-max-frequency = <25000000>;
908 spi-flash@0 {
909 compatible = "winbond,w25q32dw";
910 reg = <0>;
911 spi-max-frequency = <20000000>;
912 };
913 };
914
a1425d42
JL		 915 pmc@7000e400 {
916 nvidia,invert-interrupt;
6ec1d127
JL		 917 nvidia,suspend-mode = <1>;
918 nvidia,cpu-pwr-good-time = <500>;
919 nvidia,cpu-pwr-off-time = <300>;
920 nvidia,core-pwr-good-time = <641 3845>;
921 nvidia,core-pwr-off-time = <61036>;
922 nvidia,core-power-req-active-high;
923 nvidia,sys-clock-req-active-high;
a1425d42 924 };
3b86baf2 925
784c7444
SW		 926 sdhci@700b0400 {
927 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
928 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
929 status = "okay";
930 bus-width = <4>;
931 };
932
933 sdhci@700b0600 {
934 status = "okay";
935 bus-width = <8>;
936 };
937
b0e1caee
SW		 938 ahub@70300000 {
939 i2s@70301100 {
940 status = "okay";
941 };
942 };
943
3b86baf2
JL		 944 clocks {
945 compatible = "simple-bus";
946 #address-cells = <1>;
947 #size-cells = <0>;
948
949 clk32k_in: clock@0 {
950 compatible = "fixed-clock";
951 reg=<0>;
952 #clock-cells = <0>;
953 clock-frequency = <32768>;
954 };
955 };
b0e1caee 956
3f748d44
TR		 957 gpio-keys {
958 compatible = "gpio-keys";
959
960 power {
961 label = "Power";
962 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
963 linux,code = <KEY_POWER>;
964 debounce-interval = <10>;
965 gpio-key,wakeup;
966 };
967 };
968
fcacaba7
LD		 969 regulators {
970 compatible = "simple-bus";
971 #address-cells = <1>;
972 #size-cells = <0>;
973
af144b8d 974 vdd_mux: regulator@0 {
fcacaba7
LD		 975 compatible = "regulator-fixed";
976 reg = <0>;
af144b8d
TR		 977 regulator-name = "+VDD_MUX";
978 regulator-min-microvolt = <12000000>;
979 regulator-max-microvolt = <12000000>;
fcacaba7 980 regulator-always-on;
af144b8d 981 regulator-boot-on;
fcacaba7
LD		 982 };
983
af144b8d 984 vdd_5v0_sys: regulator@1 {
fcacaba7
LD		 985 compatible = "regulator-fixed";
986 reg = <1>;
af144b8d
TR		 987 regulator-name = "+5V_SYS";
988 regulator-min-microvolt = <5000000>;
989 regulator-max-microvolt = <5000000>;
fcacaba7
LD		 990 regulator-always-on;
991 regulator-boot-on;
af144b8d 992 vin-supply = <&vdd_mux>;
fcacaba7
LD		 993 };
994
af144b8d 995 vdd_3v3_sys: regulator@2 {
fcacaba7
LD		 996 compatible = "regulator-fixed";
997 reg = <2>;
af144b8d 998 regulator-name = "+3.3V_SYS";
fcacaba7
LD		 999 regulator-min-microvolt = <3300000>;
1000 regulator-max-microvolt = <3300000>;
af144b8d
TR		 1001 regulator-always-on;
1002 regulator-boot-on;
1003 vin-supply = <&vdd_mux>;
fcacaba7
LD		 1004 };
1005
af144b8d 1006 vdd_3v3_run: regulator@3 {
fcacaba7
LD		 1007 compatible = "regulator-fixed";
1008 reg = <3>;
af144b8d
TR		 1009 regulator-name = "+3.3V_RUN";
1010 regulator-min-microvolt = <3300000>;
1011 regulator-max-microvolt = <3300000>;
1012 gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
fcacaba7 1013 enable-active-high;
af144b8d 1014 vin-supply = <&vdd_3v3_sys>;
fcacaba7
LD		 1015 };
1016
af144b8d 1017 vdd_3v3_hdmi: regulator@4 {
fcacaba7
LD		 1018 compatible = "regulator-fixed";
1019 reg = <4>;
af144b8d 1020 regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
fcacaba7
LD		 1021 regulator-min-microvolt = <3300000>;
1022 regulator-max-microvolt = <3300000>;
af144b8d 1023 vin-supply = <&vdd_3v3_run>;
fcacaba7
LD		 1024 };
1025
af144b8d 1026 vdd_led: regulator@5 {
fcacaba7
LD		 1027 compatible = "regulator-fixed";
1028 reg = <5>;
af144b8d
TR		 1029 regulator-name = "+VDD_LED";
1030 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
fcacaba7 1031 enable-active-high;
af144b8d 1032 vin-supply = <&vdd_mux>;
fcacaba7
LD		 1033 };
1034
af144b8d 1035 vdd_5v0_ts: regulator@6 {
fcacaba7
LD		 1036 compatible = "regulator-fixed";
1037 reg = <6>;
af144b8d 1038 regulator-name = "+5V_VDD_TS_SW";
fcacaba7
LD		 1039 regulator-min-microvolt = <5000000>;
1040 regulator-max-microvolt = <5000000>;
1041 regulator-boot-on;
af144b8d 1042 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
fcacaba7 1043 enable-active-high;
af144b8d 1044 vin-supply = <&vdd_5v0_sys>;
fcacaba7
LD		 1045 };
1046
af144b8d 1047 vdd_usb1_vbus: regulator@7 {
fcacaba7
LD		 1048 compatible = "regulator-fixed";
1049 reg = <7>;
af144b8d 1050 regulator-name = "+5V_USB_HS";
fcacaba7
LD		 1051 regulator-min-microvolt = <5000000>;
1052 regulator-max-microvolt = <5000000>;
af144b8d 1053 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
fcacaba7 1054 enable-active-high;
fcacaba7 1055 gpio-open-drain;
af144b8d 1056 vin-supply = <&vdd_5v0_sys>;
fcacaba7
LD		 1057 };
1058
af144b8d 1059 vdd_usb3_vbus: regulator@8 {
fcacaba7
LD		 1060 compatible = "regulator-fixed";
1061 reg = <8>;
af144b8d
TR		 1062 regulator-name = "+5V_USB_SS";
1063 regulator-min-microvolt = <5000000>;
1064 regulator-max-microvolt = <5000000>;
1065 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1066 enable-active-high;
1067 gpio-open-drain;
1068 vin-supply = <&vdd_5v0_sys>;
1069 };
1070
1071 vdd_3v3_panel: regulator@9 {
1072 compatible = "regulator-fixed";
1073 reg = <9>;
1074 regulator-name = "+3.3V_PANEL";
fcacaba7
LD		 1075 regulator-min-microvolt = <3300000>;
1076 regulator-max-microvolt = <3300000>;
fcacaba7 1077 gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
af144b8d
TR		 1078 enable-active-high;
1079 vin-supply = <&vdd_3v3_run>;
1080 };
1081
1082 vdd_3v3_lp0: regulator@10 {
1083 compatible = "regulator-fixed";
1084 reg = <10>;
1085 regulator-name = "+3.3V_LP0";
1086 regulator-min-microvolt = <3300000>;
1087 regulator-max-microvolt = <3300000>;
1088 /*
1089 * TODO: find a way to wire this up with the USB EHCI
1090 * controllers so that it can be enabled on demand.
1091 */
1092 regulator-always-on;
1093 gpio = <&as3722 2 GPIO_ACTIVE_HIGH>;
1094 enable-active-high;
1095 vin-supply = <&vdd_3v3_sys>;
fcacaba7
LD		 1096 };
1097 };
1098
b0e1caee
SW		 1099 sound {
1100 compatible = "nvidia,tegra-audio-max98090-venice2",
1101 "nvidia,tegra-audio-max98090";
1102 nvidia,model = "NVIDIA Tegra Venice2";
1103
1104 nvidia,audio-routing =
1105 "Headphones", "HPR",
1106 "Headphones", "HPL",
1107 "Speakers", "SPKR",
1108 "Speakers", "SPKL",
1109 "Mic Jack", "MICBIAS",
1110 "IN34", "Mic Jack";
1111
1112 nvidia,i2s-controller = <&tegra_i2s1>;
1113 nvidia,audio-codec = <&acodec>;
1114
1115 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1116 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1117 <&tegra_car TEGRA124_CLK_EXTERN1>;
1118 clock-names = "pll_a", "pll_a_out0", "mclk";
1119 };
a1425d42 1120};
Linux 6.x block layer and io_uring tree(s)