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ARM: tegra: Add MIPI calibration DT entries for Tegra114
[linux-2.6-block.git] / arch / arm / boot / dts / tegra114.dtsi
CommitLineData
a1c85860 1#include <dt-bindings/clock/tegra114-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
5fc6b0dd 3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 4#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 5
1bd0bd49 6#include "skeleton.dtsi"
18a4df70
HD		 7
8/ {
9 compatible = "nvidia,tegra114";
10 interrupt-parent = <&gic>;
11
0fb22096
LD		 12 aliases {
13 serial0 = &uarta;
14 serial1 = &uartb;
15 serial2 = &uartc;
16 serial3 = &uartd;
17 };
18
58ecb23f 19 gic: interrupt-controller@50041000 {
18a4df70
HD		 20 compatible = "arm,cortex-a15-gic";
21 #interrupt-cells = <3>;
22 interrupt-controller;
23 reg = <0x50041000 0x1000>,
24 <0x50042000 0x1000>,
25 <0x50044000 0x2000>,
26 <0x50046000 0x2000>;
6cecf916
SW		 27 interrupts = <GIC_PPI 9
28 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
18a4df70
HD		 29 };
30
31 timer@60005000 {
32 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
33 reg = <0x60005000 0x400>;
6cecf916
SW		 34 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
35 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 40 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
18a4df70
HD		 41 };
42
58ecb23f 43 tegra_car: clock@60006000 {
672d889c 44 compatible = "nvidia,tegra114-car";
18a4df70
HD		 45 reg = <0x60006000 0x1000>;
46 #clock-cells = <1>;
3393d422 47 #reset-cells = <1>;
18a4df70
HD		 48 };
49
58ecb23f 50 apbdma: dma@6000a000 {
c5d9da4a
LD		 51 compatible = "nvidia,tegra114-apbdma";
52 reg = <0x6000a000 0x1400>;
6cecf916
SW		 53 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
57 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 85 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
3393d422
SW		 86 resets = <&tegra_car 34>;
87 reset-names = "dma";
034d023f 88 #dma-cells = <1>;
c5d9da4a
LD		 89 };
90
58ecb23f 91 ahb: ahb@6000c004 {
0dfe42ed
HD		 92 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
93 reg = <0x6000c004 0x14c>;
94 };
95
58ecb23f 96 gpio: gpio@6000d000 {
b16f9183
LD		 97 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
98 reg = <0x6000d000 0x1000>;
6cecf916
SW		 99 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
b16f9183
LD		 107 #gpio-cells = <2>;
108 gpio-controller;
109 #interrupt-cells = <2>;
110 interrupt-controller;
111 };
112
58ecb23f 113 pinmux: pinmux@70000868 {
031b77af
LD		 114 compatible = "nvidia,tegra114-pinmux";
115 reg = <0x70000868 0x148 /* Pad control registers */
116 0x70003000 0x40c>; /* Mux registers */
117 };
118
0fb22096
LD		 119 /*
120 * There are two serial driver i.e. 8250 based simple serial
121 * driver and APB DMA based serial driver for higher baudrate
122 * and performace. To enable the 8250 based driver, the compatible
123 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
124 * the APB DMA based serial driver, the comptible is
125 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
126 */
127 uarta: serial@70006000 {
18a4df70
HD		 128 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
129 reg = <0x70006000 0x40>;
130 reg-shift = <2>;
6cecf916 131 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 132 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
3393d422
SW		 133 resets = <&tegra_car 6>;
134 reset-names = "serial";
034d023f
SW		 135 dmas = <&apbdma 8>, <&apbdma 8>;
136 dma-names = "rx", "tx";
3393d422 137 status = "disabled";
18a4df70
HD		 138 };
139
0fb22096 140 uartb: serial@70006040 {
18a4df70
HD		 141 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
142 reg = <0x70006040 0x40>;
143 reg-shift = <2>;
6cecf916 144 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 145 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
3393d422
SW		 146 resets = <&tegra_car 7>;
147 reset-names = "serial";
034d023f
SW		 148 dmas = <&apbdma 9>, <&apbdma 9>;
149 dma-names = "rx", "tx";
3393d422 150 status = "disabled";
18a4df70
HD		 151 };
152
0fb22096 153 uartc: serial@70006200 {
18a4df70
HD		 154 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
155 reg = <0x70006200 0x100>;
156 reg-shift = <2>;
6cecf916 157 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 158 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
3393d422
SW		 159 resets = <&tegra_car 55>;
160 reset-names = "serial";
034d023f
SW		 161 dmas = <&apbdma 10>, <&apbdma 10>;
162 dma-names = "rx", "tx";
3393d422 163 status = "disabled";
18a4df70
HD		 164 };
165
0fb22096 166 uartd: serial@70006300 {
18a4df70
HD		 167 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
168 reg = <0x70006300 0x100>;
169 reg-shift = <2>;
6cecf916 170 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 171 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
3393d422
SW		 172 resets = <&tegra_car 65>;
173 reset-names = "serial";
034d023f
SW		 174 dmas = <&apbdma 19>, <&apbdma 19>;
175 dma-names = "rx", "tx";
3393d422 176 status = "disabled";
18a4df70
HD		 177 };
178
58ecb23f 179 pwm: pwm@7000a000 {
6c716db5
AC		 180 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
181 reg = <0x7000a000 0x100>;
182 #pwm-cells = <2>;
a1c85860 183 clocks = <&tegra_car TEGRA114_CLK_PWM>;
3393d422
SW		 184 resets = <&tegra_car 17>;
185 reset-names = "pwm";
6c716db5
AC		 186 status = "disabled";
187 };
188
3fc2f94e
LD		 189 i2c@7000c000 {
190 compatible = "nvidia,tegra114-i2c";
191 reg = <0x7000c000 0x100>;
6cecf916 192 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 193 #address-cells = <1>;
194 #size-cells = <0>;
a1c85860 195 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
3fc2f94e 196 clock-names = "div-clk";
3393d422
SW		 197 resets = <&tegra_car 12>;
198 reset-names = "i2c";
034d023f
SW		 199 dmas = <&apbdma 21>, <&apbdma 21>;
200 dma-names = "rx", "tx";
3fc2f94e
LD		 201 status = "disabled";
202 };
203
204 i2c@7000c400 {
205 compatible = "nvidia,tegra114-i2c";
206 reg = <0x7000c400 0x100>;
6cecf916 207 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 208 #address-cells = <1>;
209 #size-cells = <0>;
a1c85860 210 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
3fc2f94e 211 clock-names = "div-clk";
3393d422
SW		 212 resets = <&tegra_car 54>;
213 reset-names = "i2c";
034d023f
SW		 214 dmas = <&apbdma 22>, <&apbdma 22>;
215 dma-names = "rx", "tx";
3fc2f94e
LD		 216 status = "disabled";
217 };
218
219 i2c@7000c500 {
220 compatible = "nvidia,tegra114-i2c";
221 reg = <0x7000c500 0x100>;
6cecf916 222 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 223 #address-cells = <1>;
224 #size-cells = <0>;
a1c85860 225 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
3fc2f94e 226 clock-names = "div-clk";
3393d422
SW		 227 resets = <&tegra_car 67>;
228 reset-names = "i2c";
034d023f
SW		 229 dmas = <&apbdma 23>, <&apbdma 23>;
230 dma-names = "rx", "tx";
3fc2f94e
LD		 231 status = "disabled";
232 };
233
234 i2c@7000c700 {
235 compatible = "nvidia,tegra114-i2c";
236 reg = <0x7000c700 0x100>;
6cecf916 237 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 238 #address-cells = <1>;
239 #size-cells = <0>;
a1c85860 240 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
3fc2f94e 241 clock-names = "div-clk";
3393d422
SW		 242 resets = <&tegra_car 103>;
243 reset-names = "i2c";
034d023f
SW		 244 dmas = <&apbdma 26>, <&apbdma 26>;
245 dma-names = "rx", "tx";
3fc2f94e
LD		 246 status = "disabled";
247 };
248
249 i2c@7000d000 {
250 compatible = "nvidia,tegra114-i2c";
251 reg = <0x7000d000 0x100>;
6cecf916 252 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 253 #address-cells = <1>;
254 #size-cells = <0>;
a1c85860 255 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
3fc2f94e 256 clock-names = "div-clk";
3393d422
SW		 257 resets = <&tegra_car 47>;
258 reset-names = "i2c";
034d023f
SW		 259 dmas = <&apbdma 24>, <&apbdma 24>;
260 dma-names = "rx", "tx";
3fc2f94e
LD		 261 status = "disabled";
262 };
263
6ea0297e
LD		 264 spi@7000d400 {
265 compatible = "nvidia,tegra114-spi";
266 reg = <0x7000d400 0x200>;
6cecf916 267 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 268 #address-cells = <1>;
269 #size-cells = <0>;
a1c85860 270 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
6ea0297e 271 clock-names = "spi";
3393d422
SW		 272 resets = <&tegra_car 41>;
273 reset-names = "spi";
034d023f
SW		 274 dmas = <&apbdma 15>, <&apbdma 15>;
275 dma-names = "rx", "tx";
6ea0297e
LD		 276 status = "disabled";
277 };
278
279 spi@7000d600 {
280 compatible = "nvidia,tegra114-spi";
281 reg = <0x7000d600 0x200>;
6cecf916 282 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 283 #address-cells = <1>;
284 #size-cells = <0>;
a1c85860 285 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
6ea0297e 286 clock-names = "spi";
3393d422
SW		 287 resets = <&tegra_car 44>;
288 reset-names = "spi";
034d023f
SW		 289 dmas = <&apbdma 16>, <&apbdma 16>;
290 dma-names = "rx", "tx";
6ea0297e
LD		 291 status = "disabled";
292 };
293
294 spi@7000d800 {
295 compatible = "nvidia,tegra114-spi";
296 reg = <0x7000d800 0x200>;
6cecf916 297 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 298 #address-cells = <1>;
299 #size-cells = <0>;
a1c85860 300 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
6ea0297e 301 clock-names = "spi";
3393d422
SW		 302 resets = <&tegra_car 46>;
303 reset-names = "spi";
034d023f
SW		 304 dmas = <&apbdma 17>, <&apbdma 17>;
305 dma-names = "rx", "tx";
6ea0297e
LD		 306 status = "disabled";
307 };
308
309 spi@7000da00 {
310 compatible = "nvidia,tegra114-spi";
311 reg = <0x7000da00 0x200>;
6cecf916 312 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 313 #address-cells = <1>;
314 #size-cells = <0>;
a1c85860 315 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
6ea0297e 316 clock-names = "spi";
3393d422
SW		 317 resets = <&tegra_car 68>;
318 reset-names = "spi";
034d023f
SW		 319 dmas = <&apbdma 18>, <&apbdma 18>;
320 dma-names = "rx", "tx";
6ea0297e
LD		 321 status = "disabled";
322 };
323
324 spi@7000dc00 {
325 compatible = "nvidia,tegra114-spi";
326 reg = <0x7000dc00 0x200>;
6cecf916 327 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 328 #address-cells = <1>;
329 #size-cells = <0>;
a1c85860 330 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
6ea0297e 331 clock-names = "spi";
3393d422
SW		 332 resets = <&tegra_car 104>;
333 reset-names = "spi";
034d023f
SW		 334 dmas = <&apbdma 27>, <&apbdma 27>;
335 dma-names = "rx", "tx";
6ea0297e
LD		 336 status = "disabled";
337 };
338
339 spi@7000de00 {
340 compatible = "nvidia,tegra114-spi";
341 reg = <0x7000de00 0x200>;
6cecf916 342 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 343 #address-cells = <1>;
344 #size-cells = <0>;
a1c85860 345 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
6ea0297e 346 clock-names = "spi";
3393d422
SW		 347 resets = <&tegra_car 105>;
348 reset-names = "spi";
034d023f
SW		 349 dmas = <&apbdma 28>, <&apbdma 28>;
350 dma-names = "rx", "tx";
6ea0297e
LD		 351 status = "disabled";
352 };
353
58ecb23f 354 rtc@7000e000 {
18a4df70
HD		 355 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
356 reg = <0x7000e000 0x100>;
6cecf916 357 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 358 clocks = <&tegra_car TEGRA114_CLK_RTC>;
18a4df70
HD		 359 };
360
58ecb23f 361 kbc@7000e200 {
cd467b7d
LD		 362 compatible = "nvidia,tegra114-kbc";
363 reg = <0x7000e200 0x100>;
6cecf916 364 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 365 clocks = <&tegra_car TEGRA114_CLK_KBC>;
3393d422
SW		 366 resets = <&tegra_car 36>;
367 reset-names = "kbc";
cd467b7d
LD		 368 status = "disabled";
369 };
370
58ecb23f 371 pmc@7000e400 {
2b84e53b 372 compatible = "nvidia,tegra114-pmc";
18a4df70 373 reg = <0x7000e400 0x400>;
a1c85860 374 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
7021d122 375 clock-names = "pclk", "clk32k_in";
18a4df70
HD		 376 };
377
58ecb23f 378 iommu@70019010 {
2da13965 379 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
4cca9593
HD		 380 reg = <0x70019010 0x02c
381 0x700191f0 0x010
382 0x70019228 0x074>;
2da13965
HD		 383 nvidia,#asids = <4>;
384 dma-window = <0 0x40000000>;
385 nvidia,swgroups = <0x18659fe>;
386 nvidia,ahb = <&ahb>;
387 };
388
58ecb23f 389 ahub@70080000 {
15e5c647
SW		 390 compatible = "nvidia,tegra114-ahub";
391 reg = <0x70080000 0x200>,
392 <0x70080200 0x100>,
393 <0x70081000 0x200>;
394 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
15e5c647 395 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
2bd541ff
SW		 396 <&tegra_car TEGRA114_CLK_APBIF>;
397 clock-names = "d_audio", "apbif";
3393d422
SW		 398 resets = <&tegra_car 106>, /* d_audio */
399 <&tegra_car 107>, /* apbif */
400 <&tegra_car 30>, /* i2s0 */
401 <&tegra_car 11>, /* i2s1 */
402 <&tegra_car 18>, /* i2s2 */
403 <&tegra_car 101>, /* i2s3 */
404 <&tegra_car 102>, /* i2s4 */
405 <&tegra_car 108>, /* dam0 */
406 <&tegra_car 109>, /* dam1 */
407 <&tegra_car 110>, /* dam2 */
408 <&tegra_car 10>, /* spdif */
409 <&tegra_car 153>, /* amx */
410 <&tegra_car 154>; /* adx */
411 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
412 "i2s3", "i2s4", "dam0", "dam1", "dam2",
413 "spdif", "amx", "adx";
034d023f
SW		 414 dmas = <&apbdma 1>, <&apbdma 1>,
415 <&apbdma 2>, <&apbdma 2>,
416 <&apbdma 3>, <&apbdma 3>,
417 <&apbdma 4>, <&apbdma 4>,
418 <&apbdma 6>, <&apbdma 6>,
419 <&apbdma 7>, <&apbdma 7>,
420 <&apbdma 12>, <&apbdma 12>,
421 <&apbdma 13>, <&apbdma 13>,
422 <&apbdma 14>, <&apbdma 14>,
423 <&apbdma 29>, <&apbdma 29>;
424 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
425 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
426 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
427 "rx9", "tx9";
15e5c647
SW		 428 ranges;
429 #address-cells = <1>;
430 #size-cells = <1>;
431
432 tegra_i2s0: i2s@70080300 {
433 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
434 reg = <0x70080300 0x100>;
435 nvidia,ahub-cif-ids = <4 4>;
436 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
3393d422
SW		 437 resets = <&tegra_car 30>;
438 reset-names = "i2s";
15e5c647
SW		 439 status = "disabled";
440 };
441
442 tegra_i2s1: i2s@70080400 {
443 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
444 reg = <0x70080400 0x100>;
445 nvidia,ahub-cif-ids = <5 5>;
446 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
3393d422
SW		 447 resets = <&tegra_car 11>;
448 reset-names = "i2s";
15e5c647
SW		 449 status = "disabled";
450 };
451
452 tegra_i2s2: i2s@70080500 {
453 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
454 reg = <0x70080500 0x100>;
455 nvidia,ahub-cif-ids = <6 6>;
456 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
3393d422
SW		 457 resets = <&tegra_car 18>;
458 reset-names = "i2s";
15e5c647
SW		 459 status = "disabled";
460 };
461
462 tegra_i2s3: i2s@70080600 {
463 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
464 reg = <0x70080600 0x100>;
465 nvidia,ahub-cif-ids = <7 7>;
466 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
3393d422
SW		 467 resets = <&tegra_car 101>;
468 reset-names = "i2s";
15e5c647
SW		 469 status = "disabled";
470 };
471
472 tegra_i2s4: i2s@70080700 {
473 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
474 reg = <0x70080700 0x100>;
475 nvidia,ahub-cif-ids = <8 8>;
476 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
3393d422
SW		 477 resets = <&tegra_car 102>;
478 reset-names = "i2s";
15e5c647
SW		 479 status = "disabled";
480 };
481 };
482
e3d04d17
TR		 483 mipi: mipi@700e3000 {
484 compatible = "nvidia,tegra114-mipi";
485 reg = <0x700e3000 0x100>;
486 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
487 #nvidia,mipi-calibrate-cells = <1>;
488 };
489
933d87a5
PR		 490 sdhci@78000000 {
491 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
492 reg = <0x78000000 0x200>;
6cecf916 493 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 494 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
3393d422
SW		 495 resets = <&tegra_car 14>;
496 reset-names = "sdhci";
933d87a5
PR		 497 status = "disable";
498 };
499
500 sdhci@78000200 {
501 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
502 reg = <0x78000200 0x200>;
6cecf916 503 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 504 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
3393d422
SW		 505 resets = <&tegra_car 9>;
506 reset-names = "sdhci";
933d87a5
PR		 507 status = "disable";
508 };
509
510 sdhci@78000400 {
511 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
512 reg = <0x78000400 0x200>;
6cecf916 513 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 514 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
3393d422
SW		 515 resets = <&tegra_car 69>;
516 reset-names = "sdhci";
933d87a5
PR		 517 status = "disable";
518 };
519
520 sdhci@78000600 {
521 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
522 reg = <0x78000600 0x200>;
6cecf916 523 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 524 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
3393d422
SW		 525 resets = <&tegra_car 15>;
526 reset-names = "sdhci";
933d87a5
PR		 527 status = "disable";
528 };
529
328dc0ec
MP		 530 usb@7d000000 {
531 compatible = "nvidia,tegra30-ehci", "usb-ehci";
532 reg = <0x7d000000 0x4000>;
533 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
534 phy_type = "utmi";
535 clocks = <&tegra_car TEGRA114_CLK_USBD>;
3393d422
SW		 536 resets = <&tegra_car 22>;
537 reset-names = "usb";
328dc0ec
MP		 538 nvidia,phy = <&phy1>;
539 status = "disabled";
540 };
541
542 phy1: usb-phy@7d000000 {
543 compatible = "nvidia,tegra30-usb-phy";
544 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
545 phy_type = "utmi";
546 clocks = <&tegra_car TEGRA114_CLK_USBD>,
547 <&tegra_car TEGRA114_CLK_PLL_U>,
548 <&tegra_car TEGRA114_CLK_USBD>;
549 clock-names = "reg", "pll_u", "utmi-pads";
550 nvidia,hssync-start-delay = <0>;
551 nvidia,idle-wait-delay = <17>;
552 nvidia,elastic-limit = <16>;
553 nvidia,term-range-adj = <6>;
554 nvidia,xcvr-setup = <9>;
555 nvidia,xcvr-lsfslew = <0>;
556 nvidia,xcvr-lsrslew = <3>;
557 nvidia,hssquelch-level = <2>;
558 nvidia,hsdiscon-level = <5>;
559 nvidia,xcvr-hsslew = <12>;
560 status = "disabled";
561 };
562
563 usb@7d008000 {
564 compatible = "nvidia,tegra30-ehci", "usb-ehci";
565 reg = <0x7d008000 0x4000>;
566 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
567 phy_type = "utmi";
568 clocks = <&tegra_car TEGRA114_CLK_USB3>;
3393d422
SW		 569 resets = <&tegra_car 59>;
570 reset-names = "usb";
328dc0ec
MP		 571 nvidia,phy = <&phy3>;
572 status = "disabled";
573 };
574
575 phy3: usb-phy@7d008000 {
576 compatible = "nvidia,tegra30-usb-phy";
577 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
578 phy_type = "utmi";
579 clocks = <&tegra_car TEGRA114_CLK_USB3>,
580 <&tegra_car TEGRA114_CLK_PLL_U>,
581 <&tegra_car TEGRA114_CLK_USBD>;
582 clock-names = "reg", "pll_u", "utmi-pads";
583 nvidia,hssync-start-delay = <0>;
584 nvidia,idle-wait-delay = <17>;
585 nvidia,elastic-limit = <16>;
586 nvidia,term-range-adj = <6>;
587 nvidia,xcvr-setup = <9>;
588 nvidia,xcvr-lsfslew = <0>;
589 nvidia,xcvr-lsrslew = <3>;
590 nvidia,hssquelch-level = <2>;
591 nvidia,hsdiscon-level = <5>;
592 nvidia,xcvr-hsslew = <12>;
593 status = "disabled";
594 };
595
18a4df70
HD		 596 cpus {
597 #address-cells = <1>;
598 #size-cells = <0>;
599
600 cpu@0 {
601 device_type = "cpu";
602 compatible = "arm,cortex-a15";
603 reg = <0>;
604 };
605
606 cpu@1 {
607 device_type = "cpu";
608 compatible = "arm,cortex-a15";
609 reg = <1>;
610 };
611
612 cpu@2 {
613 device_type = "cpu";
614 compatible = "arm,cortex-a15";
615 reg = <2>;
616 };
617
618 cpu@3 {
619 device_type = "cpu";
620 compatible = "arm,cortex-a15";
621 reg = <3>;
622 };
623 };
624
625 timer {
626 compatible = "arm,armv7-timer";
6cecf916
SW		 627 interrupts =
628 <GIC_PPI 13
629 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
630 <GIC_PPI 14
631 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
632 <GIC_PPI 11
633 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
634 <GIC_PPI 10
635 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
18a4df70
HD		 636 };
637};
Linux 6.x block layer and io_uring tree(s)