[linux-2.6-block.git] / arch / arm / boot / dts / tegra114.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra114";
	interrupt-parent = <&gic>;

	gic: interrupt-controller {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x50041000 0x1000>,
		      <0x50042000 0x1000>,
		      <0x50044000 0x2000>,
		      <0x50046000 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
		reg = <0x60005000 0x400>;
		interrupts = <0 0 0x04
			      0 1 0x04
			      0 41 0x04
			      0 42 0x04
			      0 121 0x04
			      0 122 0x04>;
		clocks = <&tegra_car 5>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra114-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra114-apbdma";
		reg = <0x6000a000 0x1400>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04
			      0 128 0x04
			      0 129 0x04
			      0 130 0x04
			      0 131 0x04
			      0 132 0x04
			      0 133 0x04
			      0 134 0x04
			      0 135 0x04
			      0 136 0x04
			      0 137 0x04
			      0 138 0x04
			      0 139 0x04
			      0 140 0x04
			      0 141 0x04
			      0 142 0x04
			      0 143 0x04>;
		clocks = <&tegra_car 34>;
	};

	ahb: ahb {
		compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
		reg = <0x6000c004 0x14c>;
	};

	gpio: gpio {
		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04
			      0 125 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra114-pinmux";
		reg = <0x70000868 0x148		/* Pad control registers */
		       0x70003000 0x40c>;	/* Mux registers */
	};

	serial@70006000 {
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
		status = "disabled";
		clocks = <&tegra_car 6>;
	};

	serial@70006040 {
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
		status = "disabled";
		clocks = <&tegra_car 192>;
	};

	serial@70006200 {
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
		status = "disabled";
		clocks = <&tegra_car 55>;
	};

	serial@70006300 {
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
		status = "disabled";
		clocks = <&tegra_car 65>;
	};

	pwm: pwm {
		compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
		status = "disabled";
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>;
		clock-names = "div-clk";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>;
		clock-names = "div-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>;
		clock-names = "div-clk";
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c700 0x100>;
		interrupts = <0 120 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 103>;
		clock-names = "div-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000d000 0x100>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>;
		clock-names = "div-clk";
		status = "disabled";
	};

	rtc {
		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <0 2 0x04>;
		clocks = <&tegra_car 4>;
	};

	pmc {
		compatible = "nvidia,tegra114-pmc";
		reg = <0x7000e400 0x400>;
		clocks = <&tegra_car 261>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
	};

	iommu {
		compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
		reg = <0x7000f010 0x02c
		       0x7000f1f0 0x010
		       0x7000f228 0x074>;
		nvidia,#asids = <4>;
		dma-window = <0 0x40000000>;
		nvidia,swgroups = <0x18659fe>;
		nvidia,ahb = <&ahb>;
	};

	sdhci@78000000 {
		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
		reg = <0x78000000 0x200>;
		interrupts = <0 14 0x04>;
		clocks = <&tegra_car 14>;
		status = "disable";
	};

	sdhci@78000200 {
		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
		reg = <0x78000200 0x200>;
		interrupts = <0 15 0x04>;
		clocks = <&tegra_car 9>;
		status = "disable";
	};

	sdhci@78000400 {
		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
		reg = <0x78000400 0x200>;
		interrupts = <0 19 0x04>;
		clocks = <&tegra_car 69>;
		status = "disable";
	};

	sdhci@78000600 {
		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
		reg = <0x78000600 0x200>;
		interrupts = <0 31 0x04>;
		clocks = <&tegra_car 15>;
		status = "disable";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
	};
};
Commit	Line	Data
18a4df70 HD	1	/include/ "skeleton.dtsi"
	2
	3	/ {
	4	compatible = "nvidia,tegra114";
	5	interrupt-parent = <&gic>;
	6
	7	gic: interrupt-controller {
	8	compatible = "arm,cortex-a15-gic";
	9	#interrupt-cells = <3>;
	10	interrupt-controller;
	11	reg = <0x50041000 0x1000>,
	12	<0x50042000 0x1000>,
	13	<0x50044000 0x2000>,
	14	<0x50046000 0x2000>;
	15	interrupts = <1 9 0xf04>;
	16	};
	17
	18	timer@60005000 {
	19	compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
	20	reg = <0x60005000 0x400>;
	21	interrupts = <0 0 0x04
	22	0 1 0x04
	23	0 41 0x04
	24	0 42 0x04
	25	0 121 0x04
	26	0 122 0x04>;
672d889c	27	clocks = <&tegra_car 5>;
18a4df70 HD	28	};
	29
	30	tegra_car: clock {
672d889c	31	compatible = "nvidia,tegra114-car";
18a4df70 HD	32	reg = <0x60006000 0x1000>;
	33	#clock-cells = <1>;
	34	};
	35
c5d9da4a LD	36	apbdma: dma {
	37	compatible = "nvidia,tegra114-apbdma";
	38	reg = <0x6000a000 0x1400>;
	39	interrupts = <0 104 0x04
	40	0 105 0x04
	41	0 106 0x04
	42	0 107 0x04
	43	0 108 0x04
	44	0 109 0x04
	45	0 110 0x04
	46	0 111 0x04
	47	0 112 0x04
	48	0 113 0x04
	49	0 114 0x04
	50	0 115 0x04
	51	0 116 0x04
	52	0 117 0x04
	53	0 118 0x04
	54	0 119 0x04
	55	0 128 0x04
	56	0 129 0x04
	57	0 130 0x04
	58	0 131 0x04
	59	0 132 0x04
	60	0 133 0x04
	61	0 134 0x04
	62	0 135 0x04
	63	0 136 0x04
	64	0 137 0x04
	65	0 138 0x04
	66	0 139 0x04
	67	0 140 0x04
	68	0 141 0x04
	69	0 142 0x04
	70	0 143 0x04>;
	71	clocks = <&tegra_car 34>;
	72	};
	73
0dfe42ed HD	74	ahb: ahb {
	75	compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
	76	reg = <0x6000c004 0x14c>;
	77	};
	78
b16f9183 LD	79	gpio: gpio {
	80	compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
	81	reg = <0x6000d000 0x1000>;
	82	interrupts = <0 32 0x04
	83	0 33 0x04
	84	0 34 0x04
	85	0 35 0x04
	86	0 55 0x04
	87	0 87 0x04
	88	0 89 0x04
	89	0 125 0x04>;
	90	#gpio-cells = <2>;
	91	gpio-controller;
	92	#interrupt-cells = <2>;
	93	interrupt-controller;
	94	};
	95
031b77af LD	96	pinmux: pinmux {
	97	compatible = "nvidia,tegra114-pinmux";
	98	reg = <0x70000868 0x148 /* Pad control registers */
	99	0x70003000 0x40c>; /* Mux registers */
	100	};
	101
18a4df70 HD	102	serial@70006000 {
	103	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	104	reg = <0x70006000 0x40>;
	105	reg-shift = <2>;
	106	interrupts = <0 36 0x04>;
	107	status = "disabled";
672d889c	108	clocks = <&tegra_car 6>;
18a4df70 HD	109	};
	110
	111	serial@70006040 {
	112	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	113	reg = <0x70006040 0x40>;
	114	reg-shift = <2>;
	115	interrupts = <0 37 0x04>;
	116	status = "disabled";
672d889c	117	clocks = <&tegra_car 192>;
18a4df70 HD	118	};
	119
	120	serial@70006200 {
	121	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	122	reg = <0x70006200 0x100>;
	123	reg-shift = <2>;
	124	interrupts = <0 46 0x04>;
	125	status = "disabled";
672d889c	126	clocks = <&tegra_car 55>;
18a4df70 HD	127	};
	128
	129	serial@70006300 {
	130	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	131	reg = <0x70006300 0x100>;
	132	reg-shift = <2>;
	133	interrupts = <0 90 0x04>;
	134	status = "disabled";
672d889c	135	clocks = <&tegra_car 65>;
18a4df70 HD	136	};
18a4df70 HD	137
6c716db5 AC	138	pwm: pwm {
	139	compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
	140	reg = <0x7000a000 0x100>;
	141	#pwm-cells = <2>;
	142	clocks = <&tegra_car 17>;
	143	status = "disabled";
	144	};
	145
3fc2f94e LD	146	i2c@7000c000 {
	147	compatible = "nvidia,tegra114-i2c";
	148	reg = <0x7000c000 0x100>;
	149	interrupts = <0 38 0x04>;
	150	#address-cells = <1>;
	151	#size-cells = <0>;
	152	clocks = <&tegra_car 12>;
	153	clock-names = "div-clk";
	154	status = "disabled";
	155	};
	156
	157	i2c@7000c400 {
	158	compatible = "nvidia,tegra114-i2c";
	159	reg = <0x7000c400 0x100>;
	160	interrupts = <0 84 0x04>;
	161	#address-cells = <1>;
	162	#size-cells = <0>;
	163	clocks = <&tegra_car 54>;
	164	clock-names = "div-clk";
	165	status = "disabled";
	166	};
	167
	168	i2c@7000c500 {
	169	compatible = "nvidia,tegra114-i2c";
	170	reg = <0x7000c500 0x100>;
	171	interrupts = <0 92 0x04>;
	172	#address-cells = <1>;
	173	#size-cells = <0>;
	174	clocks = <&tegra_car 67>;
	175	clock-names = "div-clk";
	176	status = "disabled";
	177	};
	178
	179	i2c@7000c700 {
	180	compatible = "nvidia,tegra114-i2c";
	181	reg = <0x7000c700 0x100>;
	182	interrupts = <0 120 0x04>;
	183	#address-cells = <1>;
	184	#size-cells = <0>;
	185	clocks = <&tegra_car 103>;
	186	clock-names = "div-clk";
	187	status = "disabled";
	188	};
	189
	190	i2c@7000d000 {
	191	compatible = "nvidia,tegra114-i2c";
	192	reg = <0x7000d000 0x100>;
	193	interrupts = <0 53 0x04>;
	194	#address-cells = <1>;
	195	#size-cells = <0>;
	196	clocks = <&tegra_car 47>;
	197	clock-names = "div-clk";
	198	status = "disabled";
	199	};
	200
18a4df70 HD	201	rtc {
	202	compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
	203	reg = <0x7000e000 0x100>;
	204	interrupts = <0 2 0x04>;
672d889c	205	clocks = <&tegra_car 4>;
18a4df70 HD	206	};
	207
	208	pmc {
2b84e53b	209	compatible = "nvidia,tegra114-pmc";
18a4df70	210	reg = <0x7000e400 0x400>;
7021d122 JL	211	clocks = <&tegra_car 261>, <&clk32k_in>;
7021d122 JL	212	clock-names = "pclk", "clk32k_in";
18a4df70 HD	213	};
18a4df70 HD	214
2da13965 HD	215	iommu {
	216	compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
	217	reg = <0x7000f010 0x02c
	218	0x7000f1f0 0x010
	219	0x7000f228 0x074>;
	220	nvidia,#asids = <4>;
	221	dma-window = <0 0x40000000>;
	222	nvidia,swgroups = <0x18659fe>;
	223	nvidia,ahb = <&ahb>;
	224	};
	225
933d87a5 PR	226	sdhci@78000000 {
	227	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	228	reg = <0x78000000 0x200>;
	229	interrupts = <0 14 0x04>;
	230	clocks = <&tegra_car 14>;
	231	status = "disable";
	232	};
	233
	234	sdhci@78000200 {
	235	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	236	reg = <0x78000200 0x200>;
	237	interrupts = <0 15 0x04>;
	238	clocks = <&tegra_car 9>;
	239	status = "disable";
	240	};
	241
	242	sdhci@78000400 {
	243	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	244	reg = <0x78000400 0x200>;
	245	interrupts = <0 19 0x04>;
	246	clocks = <&tegra_car 69>;
	247	status = "disable";
	248	};
	249
	250	sdhci@78000600 {
	251	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	252	reg = <0x78000600 0x200>;
	253	interrupts = <0 31 0x04>;
	254	clocks = <&tegra_car 15>;
	255	status = "disable";
	256	};
	257
18a4df70 HD	258	cpus {
	259	#address-cells = <1>;
	260	#size-cells = <0>;
	261
	262	cpu@0 {
	263	device_type = "cpu";
	264	compatible = "arm,cortex-a15";
	265	reg = <0>;
	266	};
	267
	268	cpu@1 {
	269	device_type = "cpu";
	270	compatible = "arm,cortex-a15";
	271	reg = <1>;
	272	};
	273
	274	cpu@2 {
	275	device_type = "cpu";
	276	compatible = "arm,cortex-a15";
	277	reg = <2>;
	278	};
	279
	280	cpu@3 {
	281	device_type = "cpu";
	282	compatible = "arm,cortex-a15";
	283	reg = <3>;
	284	};
	285	};
	286
	287	timer {
	288	compatible = "arm,armv7-timer";
	289	interrupts = <1 13 0xf08>,
	290	<1 14 0xf08>,
	291	<1 11 0xf08>,
	292	<1 10 0xf08>;
	293	};
	294	};