Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
a1c85860 | 2 | #include <dt-bindings/clock/tegra114-car.h> |
3325f1bc | 3 | #include <dt-bindings/gpio/tegra-gpio.h> |
32215e71 | 4 | #include <dt-bindings/memory/tegra114-mc.h> |
5fc6b0dd | 5 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
6cecf916 | 6 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
3325f1bc | 7 | |
1bd0bd49 | 8 | #include "skeleton.dtsi" |
18a4df70 HD |
9 | |
10 | / { | |
11 | compatible = "nvidia,tegra114"; | |
870c81a4 | 12 | interrupt-parent = <&lic>; |
18a4df70 | 13 | |
65344b93 MP |
14 | host1x@50000000 { |
15 | compatible = "nvidia,tegra114-host1x", "simple-bus"; | |
16 | reg = <0x50000000 0x00028000>; | |
17 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ | |
18 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
19 | clocks = <&tegra_car TEGRA114_CLK_HOST1X>; | |
20 | resets = <&tegra_car 28>; | |
21 | reset-names = "host1x"; | |
22 | ||
23 | #address-cells = <1>; | |
24 | #size-cells = <1>; | |
25 | ||
26 | ranges = <0x54000000 0x54000000 0x01000000>; | |
27 | ||
5648b260 TR |
28 | gr2d@54140000 { |
29 | compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d"; | |
30 | reg = <0x54140000 0x00040000>; | |
31 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
32 | clocks = <&tegra_car TEGRA114_CLK_GR2D>; | |
33 | resets = <&tegra_car 21>; | |
34 | reset-names = "2d"; | |
35 | }; | |
36 | ||
032f11f3 TR |
37 | gr3d@54180000 { |
38 | compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d"; | |
39 | reg = <0x54180000 0x00040000>; | |
40 | clocks = <&tegra_car TEGRA114_CLK_GR3D>; | |
41 | resets = <&tegra_car 24>; | |
42 | reset-names = "3d"; | |
43 | }; | |
44 | ||
65344b93 MP |
45 | dc@54200000 { |
46 | compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; | |
47 | reg = <0x54200000 0x00040000>; | |
48 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
49 | clocks = <&tegra_car TEGRA114_CLK_DISP1>, | |
50 | <&tegra_car TEGRA114_CLK_PLL_P>; | |
51 | clock-names = "dc", "parent"; | |
52 | resets = <&tegra_car 27>; | |
53 | reset-names = "dc"; | |
54 | ||
32215e71 TR |
55 | iommus = <&mc TEGRA_SWGROUP_DC>; |
56 | ||
688b56b4 TR |
57 | nvidia,head = <0>; |
58 | ||
65344b93 MP |
59 | rgb { |
60 | status = "disabled"; | |
61 | }; | |
62 | }; | |
63 | ||
64 | dc@54240000 { | |
65 | compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; | |
66 | reg = <0x54240000 0x00040000>; | |
67 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
68 | clocks = <&tegra_car TEGRA114_CLK_DISP2>, | |
69 | <&tegra_car TEGRA114_CLK_PLL_P>; | |
70 | clock-names = "dc", "parent"; | |
71 | resets = <&tegra_car 26>; | |
72 | reset-names = "dc"; | |
73 | ||
32215e71 TR |
74 | iommus = <&mc TEGRA_SWGROUP_DCB>; |
75 | ||
688b56b4 TR |
76 | nvidia,head = <1>; |
77 | ||
65344b93 MP |
78 | rgb { |
79 | status = "disabled"; | |
80 | }; | |
81 | }; | |
82 | ||
83 | hdmi@54280000 { | |
84 | compatible = "nvidia,tegra114-hdmi"; | |
85 | reg = <0x54280000 0x00040000>; | |
86 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
87 | clocks = <&tegra_car TEGRA114_CLK_HDMI>, | |
88 | <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; | |
89 | clock-names = "hdmi", "parent"; | |
90 | resets = <&tegra_car 51>; | |
91 | reset-names = "hdmi"; | |
92 | status = "disabled"; | |
93 | }; | |
7e4ba90f TR |
94 | |
95 | dsi@54300000 { | |
96 | compatible = "nvidia,tegra114-dsi"; | |
97 | reg = <0x54300000 0x00040000>; | |
98 | clocks = <&tegra_car TEGRA114_CLK_DSIA>, | |
99 | <&tegra_car TEGRA114_CLK_DSIALP>, | |
100 | <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; | |
101 | clock-names = "dsi", "lp", "parent"; | |
102 | resets = <&tegra_car 48>; | |
103 | reset-names = "dsi"; | |
104 | nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ | |
105 | status = "disabled"; | |
106 | ||
107 | #address-cells = <1>; | |
108 | #size-cells = <0>; | |
109 | }; | |
110 | ||
111 | dsi@54400000 { | |
112 | compatible = "nvidia,tegra114-dsi"; | |
113 | reg = <0x54400000 0x00040000>; | |
114 | clocks = <&tegra_car TEGRA114_CLK_DSIB>, | |
115 | <&tegra_car TEGRA114_CLK_DSIBLP>, | |
116 | <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; | |
117 | clock-names = "dsi", "lp", "parent"; | |
118 | resets = <&tegra_car 82>; | |
119 | reset-names = "dsi"; | |
120 | nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ | |
121 | status = "disabled"; | |
122 | ||
123 | #address-cells = <1>; | |
124 | #size-cells = <0>; | |
125 | }; | |
65344b93 MP |
126 | }; |
127 | ||
58ecb23f | 128 | gic: interrupt-controller@50041000 { |
18a4df70 HD |
129 | compatible = "arm,cortex-a15-gic"; |
130 | #interrupt-cells = <3>; | |
131 | interrupt-controller; | |
132 | reg = <0x50041000 0x1000>, | |
133 | <0x50042000 0x1000>, | |
134 | <0x50044000 0x2000>, | |
135 | <0x50046000 0x2000>; | |
6cecf916 SW |
136 | interrupts = <GIC_PPI 9 |
137 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
870c81a4 MZ |
138 | interrupt-parent = <&gic>; |
139 | }; | |
140 | ||
141 | lic: interrupt-controller@60004000 { | |
142 | compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; | |
143 | reg = <0x60004000 0x100>, | |
144 | <0x60004100 0x50>, | |
145 | <0x60004200 0x50>, | |
146 | <0x60004300 0x50>, | |
147 | <0x60004400 0x50>; | |
148 | interrupt-controller; | |
149 | #interrupt-cells = <3>; | |
150 | interrupt-parent = <&gic>; | |
18a4df70 HD |
151 | }; |
152 | ||
153 | timer@60005000 { | |
b6641294 | 154 | compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; |
18a4df70 | 155 | reg = <0x60005000 0x400>; |
6cecf916 SW |
156 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
157 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
158 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
159 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
160 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
161 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
a1c85860 | 162 | clocks = <&tegra_car TEGRA114_CLK_TIMER>; |
18a4df70 HD |
163 | }; |
164 | ||
58ecb23f | 165 | tegra_car: clock@60006000 { |
672d889c | 166 | compatible = "nvidia,tegra114-car"; |
18a4df70 HD |
167 | reg = <0x60006000 0x1000>; |
168 | #clock-cells = <1>; | |
3393d422 | 169 | #reset-cells = <1>; |
18a4df70 HD |
170 | }; |
171 | ||
b1023134 TR |
172 | flow-controller@60007000 { |
173 | compatible = "nvidia,tegra114-flowctrl"; | |
174 | reg = <0x60007000 0x1000>; | |
175 | }; | |
176 | ||
58ecb23f | 177 | apbdma: dma@6000a000 { |
c5d9da4a LD |
178 | compatible = "nvidia,tegra114-apbdma"; |
179 | reg = <0x6000a000 0x1400>; | |
6cecf916 SW |
180 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
181 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
182 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
183 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
184 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
185 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
186 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
187 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
188 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
189 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
190 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
191 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
192 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
193 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
194 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
195 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
196 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
197 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
198 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
199 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
200 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
201 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
202 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
203 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
204 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
205 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
206 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
207 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
208 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
209 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
210 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
211 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
a1c85860 | 212 | clocks = <&tegra_car TEGRA114_CLK_APBDMA>; |
3393d422 SW |
213 | resets = <&tegra_car 34>; |
214 | reset-names = "dma"; | |
034d023f | 215 | #dma-cells = <1>; |
c5d9da4a LD |
216 | }; |
217 | ||
0d5ccb38 | 218 | ahb: ahb@6000c000 { |
0dfe42ed | 219 | compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; |
0d5ccb38 | 220 | reg = <0x6000c000 0x150>; |
0dfe42ed HD |
221 | }; |
222 | ||
58ecb23f | 223 | gpio: gpio@6000d000 { |
b16f9183 LD |
224 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; |
225 | reg = <0x6000d000 0x1000>; | |
6cecf916 SW |
226 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
227 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
228 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
229 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
230 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
231 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
232 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
233 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
b16f9183 LD |
234 | #gpio-cells = <2>; |
235 | gpio-controller; | |
236 | #interrupt-cells = <2>; | |
237 | interrupt-controller; | |
4f1d8414 | 238 | /* |
17cdddf0 | 239 | gpio-ranges = <&pinmux 0 0 246>; |
4f1d8414 | 240 | */ |
b16f9183 LD |
241 | }; |
242 | ||
155dfc7b PDS |
243 | apbmisc@70000800 { |
244 | compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; | |
245 | reg = <0x70000800 0x64 /* Chip revision */ | |
246 | 0x70000008 0x04>; /* Strapping options */ | |
247 | }; | |
248 | ||
58ecb23f | 249 | pinmux: pinmux@70000868 { |
031b77af LD |
250 | compatible = "nvidia,tegra114-pinmux"; |
251 | reg = <0x70000868 0x148 /* Pad control registers */ | |
252 | 0x70003000 0x40c>; /* Mux registers */ | |
253 | }; | |
254 | ||
0fb22096 LD |
255 | /* |
256 | * There are two serial driver i.e. 8250 based simple serial | |
257 | * driver and APB DMA based serial driver for higher baudrate | |
258 | * and performace. To enable the 8250 based driver, the compatible | |
259 | * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable | |
e1098248 | 260 | * the APB DMA based serial driver, the compatible is |
0fb22096 LD |
261 | * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". |
262 | */ | |
263 | uarta: serial@70006000 { | |
18a4df70 HD |
264 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
265 | reg = <0x70006000 0x40>; | |
266 | reg-shift = <2>; | |
6cecf916 | 267 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 268 | clocks = <&tegra_car TEGRA114_CLK_UARTA>; |
3393d422 SW |
269 | resets = <&tegra_car 6>; |
270 | reset-names = "serial"; | |
034d023f SW |
271 | dmas = <&apbdma 8>, <&apbdma 8>; |
272 | dma-names = "rx", "tx"; | |
3393d422 | 273 | status = "disabled"; |
18a4df70 HD |
274 | }; |
275 | ||
0fb22096 | 276 | uartb: serial@70006040 { |
18a4df70 HD |
277 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
278 | reg = <0x70006040 0x40>; | |
279 | reg-shift = <2>; | |
6cecf916 | 280 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 281 | clocks = <&tegra_car TEGRA114_CLK_UARTB>; |
3393d422 SW |
282 | resets = <&tegra_car 7>; |
283 | reset-names = "serial"; | |
034d023f SW |
284 | dmas = <&apbdma 9>, <&apbdma 9>; |
285 | dma-names = "rx", "tx"; | |
3393d422 | 286 | status = "disabled"; |
18a4df70 HD |
287 | }; |
288 | ||
0fb22096 | 289 | uartc: serial@70006200 { |
18a4df70 HD |
290 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
291 | reg = <0x70006200 0x100>; | |
292 | reg-shift = <2>; | |
6cecf916 | 293 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 294 | clocks = <&tegra_car TEGRA114_CLK_UARTC>; |
3393d422 SW |
295 | resets = <&tegra_car 55>; |
296 | reset-names = "serial"; | |
034d023f SW |
297 | dmas = <&apbdma 10>, <&apbdma 10>; |
298 | dma-names = "rx", "tx"; | |
3393d422 | 299 | status = "disabled"; |
18a4df70 HD |
300 | }; |
301 | ||
0fb22096 | 302 | uartd: serial@70006300 { |
18a4df70 HD |
303 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
304 | reg = <0x70006300 0x100>; | |
305 | reg-shift = <2>; | |
6cecf916 | 306 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 307 | clocks = <&tegra_car TEGRA114_CLK_UARTD>; |
3393d422 SW |
308 | resets = <&tegra_car 65>; |
309 | reset-names = "serial"; | |
034d023f SW |
310 | dmas = <&apbdma 19>, <&apbdma 19>; |
311 | dma-names = "rx", "tx"; | |
3393d422 | 312 | status = "disabled"; |
18a4df70 HD |
313 | }; |
314 | ||
58ecb23f | 315 | pwm: pwm@7000a000 { |
6c716db5 AC |
316 | compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; |
317 | reg = <0x7000a000 0x100>; | |
318 | #pwm-cells = <2>; | |
a1c85860 | 319 | clocks = <&tegra_car TEGRA114_CLK_PWM>; |
3393d422 SW |
320 | resets = <&tegra_car 17>; |
321 | reset-names = "pwm"; | |
6c716db5 AC |
322 | status = "disabled"; |
323 | }; | |
324 | ||
3fc2f94e LD |
325 | i2c@7000c000 { |
326 | compatible = "nvidia,tegra114-i2c"; | |
327 | reg = <0x7000c000 0x100>; | |
6cecf916 | 328 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
329 | #address-cells = <1>; |
330 | #size-cells = <0>; | |
a1c85860 | 331 | clocks = <&tegra_car TEGRA114_CLK_I2C1>; |
3fc2f94e | 332 | clock-names = "div-clk"; |
3393d422 SW |
333 | resets = <&tegra_car 12>; |
334 | reset-names = "i2c"; | |
034d023f SW |
335 | dmas = <&apbdma 21>, <&apbdma 21>; |
336 | dma-names = "rx", "tx"; | |
3fc2f94e LD |
337 | status = "disabled"; |
338 | }; | |
339 | ||
340 | i2c@7000c400 { | |
341 | compatible = "nvidia,tegra114-i2c"; | |
342 | reg = <0x7000c400 0x100>; | |
6cecf916 | 343 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
344 | #address-cells = <1>; |
345 | #size-cells = <0>; | |
a1c85860 | 346 | clocks = <&tegra_car TEGRA114_CLK_I2C2>; |
3fc2f94e | 347 | clock-names = "div-clk"; |
3393d422 SW |
348 | resets = <&tegra_car 54>; |
349 | reset-names = "i2c"; | |
034d023f SW |
350 | dmas = <&apbdma 22>, <&apbdma 22>; |
351 | dma-names = "rx", "tx"; | |
3fc2f94e LD |
352 | status = "disabled"; |
353 | }; | |
354 | ||
355 | i2c@7000c500 { | |
356 | compatible = "nvidia,tegra114-i2c"; | |
357 | reg = <0x7000c500 0x100>; | |
6cecf916 | 358 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
359 | #address-cells = <1>; |
360 | #size-cells = <0>; | |
a1c85860 | 361 | clocks = <&tegra_car TEGRA114_CLK_I2C3>; |
3fc2f94e | 362 | clock-names = "div-clk"; |
3393d422 SW |
363 | resets = <&tegra_car 67>; |
364 | reset-names = "i2c"; | |
034d023f SW |
365 | dmas = <&apbdma 23>, <&apbdma 23>; |
366 | dma-names = "rx", "tx"; | |
3fc2f94e LD |
367 | status = "disabled"; |
368 | }; | |
369 | ||
370 | i2c@7000c700 { | |
371 | compatible = "nvidia,tegra114-i2c"; | |
372 | reg = <0x7000c700 0x100>; | |
6cecf916 | 373 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
374 | #address-cells = <1>; |
375 | #size-cells = <0>; | |
a1c85860 | 376 | clocks = <&tegra_car TEGRA114_CLK_I2C4>; |
3fc2f94e | 377 | clock-names = "div-clk"; |
3393d422 SW |
378 | resets = <&tegra_car 103>; |
379 | reset-names = "i2c"; | |
034d023f SW |
380 | dmas = <&apbdma 26>, <&apbdma 26>; |
381 | dma-names = "rx", "tx"; | |
3fc2f94e LD |
382 | status = "disabled"; |
383 | }; | |
384 | ||
385 | i2c@7000d000 { | |
386 | compatible = "nvidia,tegra114-i2c"; | |
387 | reg = <0x7000d000 0x100>; | |
6cecf916 | 388 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
389 | #address-cells = <1>; |
390 | #size-cells = <0>; | |
a1c85860 | 391 | clocks = <&tegra_car TEGRA114_CLK_I2C5>; |
3fc2f94e | 392 | clock-names = "div-clk"; |
3393d422 SW |
393 | resets = <&tegra_car 47>; |
394 | reset-names = "i2c"; | |
034d023f SW |
395 | dmas = <&apbdma 24>, <&apbdma 24>; |
396 | dma-names = "rx", "tx"; | |
3fc2f94e LD |
397 | status = "disabled"; |
398 | }; | |
399 | ||
6ea0297e LD |
400 | spi@7000d400 { |
401 | compatible = "nvidia,tegra114-spi"; | |
402 | reg = <0x7000d400 0x200>; | |
6cecf916 | 403 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
404 | #address-cells = <1>; |
405 | #size-cells = <0>; | |
a1c85860 | 406 | clocks = <&tegra_car TEGRA114_CLK_SBC1>; |
6ea0297e | 407 | clock-names = "spi"; |
3393d422 SW |
408 | resets = <&tegra_car 41>; |
409 | reset-names = "spi"; | |
034d023f SW |
410 | dmas = <&apbdma 15>, <&apbdma 15>; |
411 | dma-names = "rx", "tx"; | |
6ea0297e LD |
412 | status = "disabled"; |
413 | }; | |
414 | ||
415 | spi@7000d600 { | |
416 | compatible = "nvidia,tegra114-spi"; | |
417 | reg = <0x7000d600 0x200>; | |
6cecf916 | 418 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
419 | #address-cells = <1>; |
420 | #size-cells = <0>; | |
a1c85860 | 421 | clocks = <&tegra_car TEGRA114_CLK_SBC2>; |
6ea0297e | 422 | clock-names = "spi"; |
3393d422 SW |
423 | resets = <&tegra_car 44>; |
424 | reset-names = "spi"; | |
034d023f SW |
425 | dmas = <&apbdma 16>, <&apbdma 16>; |
426 | dma-names = "rx", "tx"; | |
6ea0297e LD |
427 | status = "disabled"; |
428 | }; | |
429 | ||
430 | spi@7000d800 { | |
431 | compatible = "nvidia,tegra114-spi"; | |
432 | reg = <0x7000d800 0x200>; | |
6cecf916 | 433 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
434 | #address-cells = <1>; |
435 | #size-cells = <0>; | |
a1c85860 | 436 | clocks = <&tegra_car TEGRA114_CLK_SBC3>; |
6ea0297e | 437 | clock-names = "spi"; |
3393d422 SW |
438 | resets = <&tegra_car 46>; |
439 | reset-names = "spi"; | |
034d023f SW |
440 | dmas = <&apbdma 17>, <&apbdma 17>; |
441 | dma-names = "rx", "tx"; | |
6ea0297e LD |
442 | status = "disabled"; |
443 | }; | |
444 | ||
445 | spi@7000da00 { | |
446 | compatible = "nvidia,tegra114-spi"; | |
447 | reg = <0x7000da00 0x200>; | |
6cecf916 | 448 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
449 | #address-cells = <1>; |
450 | #size-cells = <0>; | |
a1c85860 | 451 | clocks = <&tegra_car TEGRA114_CLK_SBC4>; |
6ea0297e | 452 | clock-names = "spi"; |
3393d422 SW |
453 | resets = <&tegra_car 68>; |
454 | reset-names = "spi"; | |
034d023f SW |
455 | dmas = <&apbdma 18>, <&apbdma 18>; |
456 | dma-names = "rx", "tx"; | |
6ea0297e LD |
457 | status = "disabled"; |
458 | }; | |
459 | ||
460 | spi@7000dc00 { | |
461 | compatible = "nvidia,tegra114-spi"; | |
462 | reg = <0x7000dc00 0x200>; | |
6cecf916 | 463 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
464 | #address-cells = <1>; |
465 | #size-cells = <0>; | |
a1c85860 | 466 | clocks = <&tegra_car TEGRA114_CLK_SBC5>; |
6ea0297e | 467 | clock-names = "spi"; |
3393d422 SW |
468 | resets = <&tegra_car 104>; |
469 | reset-names = "spi"; | |
034d023f SW |
470 | dmas = <&apbdma 27>, <&apbdma 27>; |
471 | dma-names = "rx", "tx"; | |
6ea0297e LD |
472 | status = "disabled"; |
473 | }; | |
474 | ||
475 | spi@7000de00 { | |
476 | compatible = "nvidia,tegra114-spi"; | |
477 | reg = <0x7000de00 0x200>; | |
6cecf916 | 478 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
479 | #address-cells = <1>; |
480 | #size-cells = <0>; | |
a1c85860 | 481 | clocks = <&tegra_car TEGRA114_CLK_SBC6>; |
6ea0297e | 482 | clock-names = "spi"; |
3393d422 SW |
483 | resets = <&tegra_car 105>; |
484 | reset-names = "spi"; | |
034d023f SW |
485 | dmas = <&apbdma 28>, <&apbdma 28>; |
486 | dma-names = "rx", "tx"; | |
6ea0297e LD |
487 | status = "disabled"; |
488 | }; | |
489 | ||
58ecb23f | 490 | rtc@7000e000 { |
18a4df70 HD |
491 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; |
492 | reg = <0x7000e000 0x100>; | |
6cecf916 | 493 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 494 | clocks = <&tegra_car TEGRA114_CLK_RTC>; |
18a4df70 HD |
495 | }; |
496 | ||
58ecb23f | 497 | kbc@7000e200 { |
cd467b7d LD |
498 | compatible = "nvidia,tegra114-kbc"; |
499 | reg = <0x7000e200 0x100>; | |
6cecf916 | 500 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 501 | clocks = <&tegra_car TEGRA114_CLK_KBC>; |
3393d422 SW |
502 | resets = <&tegra_car 36>; |
503 | reset-names = "kbc"; | |
cd467b7d LD |
504 | status = "disabled"; |
505 | }; | |
506 | ||
58ecb23f | 507 | pmc@7000e400 { |
2b84e53b | 508 | compatible = "nvidia,tegra114-pmc"; |
18a4df70 | 509 | reg = <0x7000e400 0x400>; |
a1c85860 | 510 | clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; |
7021d122 | 511 | clock-names = "pclk", "clk32k_in"; |
18a4df70 HD |
512 | }; |
513 | ||
155dfc7b PDS |
514 | fuse@7000f800 { |
515 | compatible = "nvidia,tegra114-efuse"; | |
516 | reg = <0x7000f800 0x400>; | |
517 | clocks = <&tegra_car TEGRA114_CLK_FUSE>; | |
518 | clock-names = "fuse"; | |
519 | resets = <&tegra_car 39>; | |
520 | reset-names = "fuse"; | |
521 | }; | |
522 | ||
c6f70a4d TR |
523 | mc: memory-controller@70019000 { |
524 | compatible = "nvidia,tegra114-mc"; | |
525 | reg = <0x70019000 0x1000>; | |
526 | clocks = <&tegra_car TEGRA114_CLK_MC>; | |
527 | clock-names = "mc"; | |
528 | ||
529 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
530 | ||
531 | #iommu-cells = <1>; | |
2da13965 HD |
532 | }; |
533 | ||
58ecb23f | 534 | ahub@70080000 { |
15e5c647 SW |
535 | compatible = "nvidia,tegra114-ahub"; |
536 | reg = <0x70080000 0x200>, | |
537 | <0x70080200 0x100>, | |
538 | <0x70081000 0x200>; | |
539 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
15e5c647 | 540 | clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, |
2bd541ff SW |
541 | <&tegra_car TEGRA114_CLK_APBIF>; |
542 | clock-names = "d_audio", "apbif"; | |
3393d422 SW |
543 | resets = <&tegra_car 106>, /* d_audio */ |
544 | <&tegra_car 107>, /* apbif */ | |
545 | <&tegra_car 30>, /* i2s0 */ | |
546 | <&tegra_car 11>, /* i2s1 */ | |
547 | <&tegra_car 18>, /* i2s2 */ | |
548 | <&tegra_car 101>, /* i2s3 */ | |
549 | <&tegra_car 102>, /* i2s4 */ | |
550 | <&tegra_car 108>, /* dam0 */ | |
551 | <&tegra_car 109>, /* dam1 */ | |
552 | <&tegra_car 110>, /* dam2 */ | |
553 | <&tegra_car 10>, /* spdif */ | |
554 | <&tegra_car 153>, /* amx */ | |
555 | <&tegra_car 154>; /* adx */ | |
556 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
557 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
558 | "spdif", "amx", "adx"; | |
034d023f SW |
559 | dmas = <&apbdma 1>, <&apbdma 1>, |
560 | <&apbdma 2>, <&apbdma 2>, | |
561 | <&apbdma 3>, <&apbdma 3>, | |
562 | <&apbdma 4>, <&apbdma 4>, | |
563 | <&apbdma 6>, <&apbdma 6>, | |
564 | <&apbdma 7>, <&apbdma 7>, | |
565 | <&apbdma 12>, <&apbdma 12>, | |
566 | <&apbdma 13>, <&apbdma 13>, | |
567 | <&apbdma 14>, <&apbdma 14>, | |
568 | <&apbdma 29>, <&apbdma 29>; | |
569 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", | |
570 | "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", | |
571 | "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", | |
572 | "rx9", "tx9"; | |
15e5c647 SW |
573 | ranges; |
574 | #address-cells = <1>; | |
575 | #size-cells = <1>; | |
576 | ||
577 | tegra_i2s0: i2s@70080300 { | |
578 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
579 | reg = <0x70080300 0x100>; | |
580 | nvidia,ahub-cif-ids = <4 4>; | |
581 | clocks = <&tegra_car TEGRA114_CLK_I2S0>; | |
3393d422 SW |
582 | resets = <&tegra_car 30>; |
583 | reset-names = "i2s"; | |
15e5c647 SW |
584 | status = "disabled"; |
585 | }; | |
586 | ||
587 | tegra_i2s1: i2s@70080400 { | |
588 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
589 | reg = <0x70080400 0x100>; | |
590 | nvidia,ahub-cif-ids = <5 5>; | |
591 | clocks = <&tegra_car TEGRA114_CLK_I2S1>; | |
3393d422 SW |
592 | resets = <&tegra_car 11>; |
593 | reset-names = "i2s"; | |
15e5c647 SW |
594 | status = "disabled"; |
595 | }; | |
596 | ||
597 | tegra_i2s2: i2s@70080500 { | |
598 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
599 | reg = <0x70080500 0x100>; | |
600 | nvidia,ahub-cif-ids = <6 6>; | |
601 | clocks = <&tegra_car TEGRA114_CLK_I2S2>; | |
3393d422 SW |
602 | resets = <&tegra_car 18>; |
603 | reset-names = "i2s"; | |
15e5c647 SW |
604 | status = "disabled"; |
605 | }; | |
606 | ||
607 | tegra_i2s3: i2s@70080600 { | |
608 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
609 | reg = <0x70080600 0x100>; | |
610 | nvidia,ahub-cif-ids = <7 7>; | |
611 | clocks = <&tegra_car TEGRA114_CLK_I2S3>; | |
3393d422 SW |
612 | resets = <&tegra_car 101>; |
613 | reset-names = "i2s"; | |
15e5c647 SW |
614 | status = "disabled"; |
615 | }; | |
616 | ||
617 | tegra_i2s4: i2s@70080700 { | |
618 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
619 | reg = <0x70080700 0x100>; | |
620 | nvidia,ahub-cif-ids = <8 8>; | |
621 | clocks = <&tegra_car TEGRA114_CLK_I2S4>; | |
3393d422 SW |
622 | resets = <&tegra_car 102>; |
623 | reset-names = "i2s"; | |
15e5c647 SW |
624 | status = "disabled"; |
625 | }; | |
626 | }; | |
627 | ||
e3d04d17 TR |
628 | mipi: mipi@700e3000 { |
629 | compatible = "nvidia,tegra114-mipi"; | |
630 | reg = <0x700e3000 0x100>; | |
631 | clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; | |
632 | #nvidia,mipi-calibrate-cells = <1>; | |
633 | }; | |
634 | ||
933d87a5 PR |
635 | sdhci@78000000 { |
636 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
637 | reg = <0x78000000 0x200>; | |
6cecf916 | 638 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 639 | clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; |
3393d422 SW |
640 | resets = <&tegra_car 14>; |
641 | reset-names = "sdhci"; | |
e2b6d77e | 642 | status = "disabled"; |
933d87a5 PR |
643 | }; |
644 | ||
645 | sdhci@78000200 { | |
646 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
647 | reg = <0x78000200 0x200>; | |
6cecf916 | 648 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 649 | clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; |
3393d422 SW |
650 | resets = <&tegra_car 9>; |
651 | reset-names = "sdhci"; | |
e2b6d77e | 652 | status = "disabled"; |
933d87a5 PR |
653 | }; |
654 | ||
655 | sdhci@78000400 { | |
656 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
657 | reg = <0x78000400 0x200>; | |
6cecf916 | 658 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 659 | clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; |
3393d422 SW |
660 | resets = <&tegra_car 69>; |
661 | reset-names = "sdhci"; | |
e2b6d77e | 662 | status = "disabled"; |
933d87a5 PR |
663 | }; |
664 | ||
665 | sdhci@78000600 { | |
666 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
667 | reg = <0x78000600 0x200>; | |
6cecf916 | 668 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 669 | clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; |
3393d422 SW |
670 | resets = <&tegra_car 15>; |
671 | reset-names = "sdhci"; | |
e2b6d77e | 672 | status = "disabled"; |
933d87a5 PR |
673 | }; |
674 | ||
328dc0ec | 675 | usb@7d000000 { |
a70cb07b | 676 | compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
328dc0ec MP |
677 | reg = <0x7d000000 0x4000>; |
678 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
679 | phy_type = "utmi"; | |
680 | clocks = <&tegra_car TEGRA114_CLK_USBD>; | |
3393d422 SW |
681 | resets = <&tegra_car 22>; |
682 | reset-names = "usb"; | |
328dc0ec MP |
683 | nvidia,phy = <&phy1>; |
684 | status = "disabled"; | |
685 | }; | |
686 | ||
687 | phy1: usb-phy@7d000000 { | |
a70cb07b | 688 | compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; |
328dc0ec MP |
689 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; |
690 | phy_type = "utmi"; | |
691 | clocks = <&tegra_car TEGRA114_CLK_USBD>, | |
692 | <&tegra_car TEGRA114_CLK_PLL_U>, | |
693 | <&tegra_car TEGRA114_CLK_USBD>; | |
694 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
695 | resets = <&tegra_car 22>, <&tegra_car 22>; |
696 | reset-names = "usb", "utmi-pads"; | |
328dc0ec MP |
697 | nvidia,hssync-start-delay = <0>; |
698 | nvidia,idle-wait-delay = <17>; | |
699 | nvidia,elastic-limit = <16>; | |
700 | nvidia,term-range-adj = <6>; | |
701 | nvidia,xcvr-setup = <9>; | |
702 | nvidia,xcvr-lsfslew = <0>; | |
703 | nvidia,xcvr-lsrslew = <3>; | |
704 | nvidia,hssquelch-level = <2>; | |
705 | nvidia,hsdiscon-level = <5>; | |
706 | nvidia,xcvr-hsslew = <12>; | |
308efde2 | 707 | nvidia,has-utmi-pad-registers; |
328dc0ec MP |
708 | status = "disabled"; |
709 | }; | |
710 | ||
711 | usb@7d008000 { | |
a70cb07b | 712 | compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
328dc0ec MP |
713 | reg = <0x7d008000 0x4000>; |
714 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
715 | phy_type = "utmi"; | |
716 | clocks = <&tegra_car TEGRA114_CLK_USB3>; | |
3393d422 SW |
717 | resets = <&tegra_car 59>; |
718 | reset-names = "usb"; | |
328dc0ec MP |
719 | nvidia,phy = <&phy3>; |
720 | status = "disabled"; | |
721 | }; | |
722 | ||
723 | phy3: usb-phy@7d008000 { | |
a70cb07b | 724 | compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; |
328dc0ec MP |
725 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; |
726 | phy_type = "utmi"; | |
727 | clocks = <&tegra_car TEGRA114_CLK_USB3>, | |
728 | <&tegra_car TEGRA114_CLK_PLL_U>, | |
729 | <&tegra_car TEGRA114_CLK_USBD>; | |
730 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
731 | resets = <&tegra_car 59>, <&tegra_car 22>; |
732 | reset-names = "usb", "utmi-pads"; | |
328dc0ec MP |
733 | nvidia,hssync-start-delay = <0>; |
734 | nvidia,idle-wait-delay = <17>; | |
735 | nvidia,elastic-limit = <16>; | |
736 | nvidia,term-range-adj = <6>; | |
737 | nvidia,xcvr-setup = <9>; | |
738 | nvidia,xcvr-lsfslew = <0>; | |
739 | nvidia,xcvr-lsrslew = <3>; | |
740 | nvidia,hssquelch-level = <2>; | |
741 | nvidia,hsdiscon-level = <5>; | |
742 | nvidia,xcvr-hsslew = <12>; | |
743 | status = "disabled"; | |
744 | }; | |
745 | ||
18a4df70 HD |
746 | cpus { |
747 | #address-cells = <1>; | |
748 | #size-cells = <0>; | |
749 | ||
750 | cpu@0 { | |
751 | device_type = "cpu"; | |
752 | compatible = "arm,cortex-a15"; | |
753 | reg = <0>; | |
754 | }; | |
755 | ||
756 | cpu@1 { | |
757 | device_type = "cpu"; | |
758 | compatible = "arm,cortex-a15"; | |
759 | reg = <1>; | |
760 | }; | |
761 | ||
762 | cpu@2 { | |
763 | device_type = "cpu"; | |
764 | compatible = "arm,cortex-a15"; | |
765 | reg = <2>; | |
766 | }; | |
767 | ||
768 | cpu@3 { | |
769 | device_type = "cpu"; | |
770 | compatible = "arm,cortex-a15"; | |
771 | reg = <3>; | |
772 | }; | |
773 | }; | |
774 | ||
775 | timer { | |
776 | compatible = "arm,armv7-timer"; | |
6cecf916 SW |
777 | interrupts = |
778 | <GIC_PPI 13 | |
779 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
780 | <GIC_PPI 14 | |
781 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
782 | <GIC_PPI 11 | |
783 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
784 | <GIC_PPI 10 | |
785 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
870c81a4 | 786 | interrupt-parent = <&gic>; |
18a4df70 HD |
787 | }; |
788 | }; |