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4ab328f0 CYT |
1 | /* |
2 | * Copyright 2014 Chen-Yu Tsai | |
3 | * | |
4 | * Chen-Yu Tsai <wens@csie.org> | |
5 | * | |
6 | * This file is dual-licensed: you can use it either under the terms | |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
10 | * | |
136d18a8 | 11 | * a) This file is free software; you can redistribute it and/or |
4ab328f0 CYT |
12 | * modify it under the terms of the GNU General Public License as |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
136d18a8 | 16 | * This file is distributed in the hope that it will be useful, |
4ab328f0 CYT |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
4ab328f0 CYT |
21 | * Or, alternatively, |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
43 | */ | |
44 | ||
19882b84 MR |
45 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
46 | ||
64507fe3 CYT |
47 | #include <dt-bindings/clock/sun9i-a80-ccu.h> |
48 | #include <dt-bindings/clock/sun9i-a80-de.h> | |
49 | #include <dt-bindings/clock/sun9i-a80-usb.h> | |
50 | #include <dt-bindings/reset/sun9i-a80-ccu.h> | |
51 | #include <dt-bindings/reset/sun9i-a80-de.h> | |
52 | #include <dt-bindings/reset/sun9i-a80-usb.h> | |
53 | ||
4ab328f0 | 54 | / { |
98dc89db MR |
55 | #address-cells = <2>; |
56 | #size-cells = <2>; | |
4ab328f0 CYT |
57 | interrupt-parent = <&gic>; |
58 | ||
4ab328f0 CYT |
59 | cpus { |
60 | #address-cells = <1>; | |
61 | #size-cells = <0>; | |
62 | ||
63 | cpu0: cpu@0 { | |
64 | compatible = "arm,cortex-a7"; | |
65 | device_type = "cpu"; | |
f0b55841 CYT |
66 | cci-control-port = <&cci_control0>; |
67 | clock-frequency = <12000000>; | |
4ab328f0 CYT |
68 | reg = <0x0>; |
69 | }; | |
70 | ||
71 | cpu1: cpu@1 { | |
72 | compatible = "arm,cortex-a7"; | |
73 | device_type = "cpu"; | |
f0b55841 CYT |
74 | cci-control-port = <&cci_control0>; |
75 | clock-frequency = <12000000>; | |
4ab328f0 CYT |
76 | reg = <0x1>; |
77 | }; | |
78 | ||
79 | cpu2: cpu@2 { | |
80 | compatible = "arm,cortex-a7"; | |
81 | device_type = "cpu"; | |
f0b55841 CYT |
82 | cci-control-port = <&cci_control0>; |
83 | clock-frequency = <12000000>; | |
4ab328f0 CYT |
84 | reg = <0x2>; |
85 | }; | |
86 | ||
87 | cpu3: cpu@3 { | |
88 | compatible = "arm,cortex-a7"; | |
89 | device_type = "cpu"; | |
f0b55841 CYT |
90 | cci-control-port = <&cci_control0>; |
91 | clock-frequency = <12000000>; | |
4ab328f0 CYT |
92 | reg = <0x3>; |
93 | }; | |
94 | ||
95 | cpu4: cpu@100 { | |
96 | compatible = "arm,cortex-a15"; | |
97 | device_type = "cpu"; | |
f0b55841 CYT |
98 | cci-control-port = <&cci_control1>; |
99 | clock-frequency = <18000000>; | |
4ab328f0 CYT |
100 | reg = <0x100>; |
101 | }; | |
102 | ||
103 | cpu5: cpu@101 { | |
104 | compatible = "arm,cortex-a15"; | |
105 | device_type = "cpu"; | |
f0b55841 CYT |
106 | cci-control-port = <&cci_control1>; |
107 | clock-frequency = <18000000>; | |
4ab328f0 CYT |
108 | reg = <0x101>; |
109 | }; | |
110 | ||
111 | cpu6: cpu@102 { | |
112 | compatible = "arm,cortex-a15"; | |
113 | device_type = "cpu"; | |
f0b55841 CYT |
114 | cci-control-port = <&cci_control1>; |
115 | clock-frequency = <18000000>; | |
4ab328f0 CYT |
116 | reg = <0x102>; |
117 | }; | |
118 | ||
119 | cpu7: cpu@103 { | |
120 | compatible = "arm,cortex-a15"; | |
121 | device_type = "cpu"; | |
f0b55841 CYT |
122 | cci-control-port = <&cci_control1>; |
123 | clock-frequency = <18000000>; | |
4ab328f0 CYT |
124 | reg = <0x103>; |
125 | }; | |
126 | }; | |
127 | ||
51e9f5ff CYT |
128 | timer { |
129 | compatible = "arm,armv7-timer"; | |
130 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
131 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
132 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
133 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
134 | clock-frequency = <24000000>; | |
135 | arm,cpu-registers-not-fw-configured; | |
136 | }; | |
137 | ||
4ab328f0 CYT |
138 | clocks { |
139 | #address-cells = <1>; | |
140 | #size-cells = <1>; | |
141 | /* | |
142 | * map 64 bit address range down to 32 bits, | |
143 | * as the peripherals are all under 512MB. | |
144 | */ | |
145 | ranges = <0 0 0 0x20000000>; | |
146 | ||
d255abd6 CYT |
147 | /* |
148 | * This clock is actually configurable from the PRCM address | |
149 | * space. The external 24M oscillator can be turned off, and | |
150 | * the clock switched to an internal 16M RC oscillator. Under | |
151 | * normal operation there's no reason to do this, and the | |
152 | * default is to use the external good one, so just model this | |
153 | * as a fixed clock. Also it is not entirely clear if the | |
154 | * osc24M mux in the PRCM affects the entire clock tree, which | |
155 | * would also throw all the PLL clock rates off, or just the | |
156 | * downstream clocks in the PRCM. | |
157 | */ | |
00a7088f | 158 | osc24M: clk-24M { |
4ab328f0 CYT |
159 | #clock-cells = <0>; |
160 | compatible = "fixed-clock"; | |
161 | clock-frequency = <24000000>; | |
162 | clock-output-names = "osc24M"; | |
163 | }; | |
164 | ||
d255abd6 CYT |
165 | /* |
166 | * The 32k clock is from an external source, normally the | |
16266987 CYT |
167 | * AC100 codec/RTC chip. This serves as a placeholder for |
168 | * board dts files to specify the source. | |
d255abd6 | 169 | */ |
00a7088f | 170 | osc32k: clk-32k { |
4ab328f0 | 171 | #clock-cells = <0>; |
16266987 CYT |
172 | compatible = "fixed-factor-clock"; |
173 | clock-div = <1>; | |
174 | clock-mult = <1>; | |
4ab328f0 CYT |
175 | clock-output-names = "osc32k"; |
176 | }; | |
ac399a97 | 177 | |
5841f6c0 | 178 | cpus_clk: clk@8001410 { |
afd7d66c CYT |
179 | compatible = "allwinner,sun9i-a80-cpus-clk"; |
180 | reg = <0x08001410 0x4>; | |
181 | #clock-cells = <0>; | |
64507fe3 CYT |
182 | clocks = <&osc32k>, <&osc24M>, |
183 | <&ccu CLK_PLL_PERIPH0>, | |
184 | <&ccu CLK_PLL_AUDIO>; | |
afd7d66c CYT |
185 | clock-output-names = "cpus"; |
186 | }; | |
187 | ||
00a7088f | 188 | ahbs: clk-ahbs { |
afd7d66c CYT |
189 | compatible = "fixed-factor-clock"; |
190 | #clock-cells = <0>; | |
191 | clock-div = <1>; | |
192 | clock-mult = <1>; | |
193 | clocks = <&cpus_clk>; | |
194 | clock-output-names = "ahbs"; | |
195 | }; | |
196 | ||
5841f6c0 | 197 | apbs: clk@800141c { |
afd7d66c CYT |
198 | compatible = "allwinner,sun8i-a23-apb0-clk"; |
199 | reg = <0x0800141c 0x4>; | |
200 | #clock-cells = <0>; | |
201 | clocks = <&ahbs>; | |
202 | clock-output-names = "apbs"; | |
203 | }; | |
204 | ||
5841f6c0 | 205 | apbs_gates: clk@8001428 { |
afd7d66c CYT |
206 | compatible = "allwinner,sun9i-a80-apbs-gates-clk"; |
207 | reg = <0x08001428 0x4>; | |
208 | #clock-cells = <1>; | |
209 | clocks = <&apbs>; | |
210 | clock-indices = <0>, <1>, | |
211 | <2>, <3>, | |
212 | <4>, <5>, | |
213 | <6>, <7>, | |
214 | <12>, <13>, | |
215 | <16>, <17>, | |
216 | <18>, <20>; | |
217 | clock-output-names = "apbs_pio", "apbs_ir", | |
218 | "apbs_timer", "apbs_rsb", | |
219 | "apbs_uart", "apbs_1wire", | |
220 | "apbs_i2c0", "apbs_i2c1", | |
221 | "apbs_ps2_0", "apbs_ps2_1", | |
222 | "apbs_dma", "apbs_i2s0", | |
223 | "apbs_i2s1", "apbs_twd"; | |
224 | }; | |
225 | ||
5841f6c0 | 226 | r_1wire_clk: clk@8001450 { |
afd7d66c CYT |
227 | reg = <0x08001450 0x4>; |
228 | #clock-cells = <0>; | |
229 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
230 | clocks = <&osc32k>, <&osc24M>; | |
231 | clock-output-names = "r_1wire"; | |
232 | }; | |
233 | ||
5841f6c0 | 234 | r_ir_clk: clk@8001454 { |
afd7d66c CYT |
235 | reg = <0x08001454 0x4>; |
236 | #clock-cells = <0>; | |
237 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
238 | clocks = <&osc32k>, <&osc24M>; | |
239 | clock-output-names = "r_ir"; | |
240 | }; | |
4ab328f0 CYT |
241 | }; |
242 | ||
243 | soc { | |
244 | compatible = "simple-bus"; | |
245 | #address-cells = <1>; | |
246 | #size-cells = <1>; | |
247 | /* | |
248 | * map 64 bit address range down to 32 bits, | |
249 | * as the peripherals are all under 512MB. | |
250 | */ | |
251 | ranges = <0 0 0 0x20000000>; | |
252 | ||
5841f6c0 | 253 | ehci0: usb@a00000 { |
70472163 CYT |
254 | compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; |
255 | reg = <0x00a00000 0x100>; | |
256 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
64507fe3 CYT |
257 | clocks = <&usb_clocks CLK_BUS_HCI0>; |
258 | resets = <&usb_clocks RST_USB0_HCI>; | |
70472163 CYT |
259 | phys = <&usbphy1>; |
260 | phy-names = "usb"; | |
261 | status = "disabled"; | |
262 | }; | |
263 | ||
5841f6c0 | 264 | ohci0: usb@a00400 { |
70472163 CYT |
265 | compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; |
266 | reg = <0x00a00400 0x100>; | |
267 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
64507fe3 CYT |
268 | clocks = <&usb_clocks CLK_BUS_HCI0>, |
269 | <&usb_clocks CLK_USB_OHCI0>; | |
270 | resets = <&usb_clocks RST_USB0_HCI>; | |
70472163 CYT |
271 | phys = <&usbphy1>; |
272 | phy-names = "usb"; | |
273 | status = "disabled"; | |
274 | }; | |
275 | ||
5841f6c0 | 276 | usbphy1: phy@a00800 { |
1af5d192 CYT |
277 | compatible = "allwinner,sun9i-a80-usb-phy"; |
278 | reg = <0x00a00800 0x4>; | |
64507fe3 | 279 | clocks = <&usb_clocks CLK_USB0_PHY>; |
1af5d192 | 280 | clock-names = "phy"; |
64507fe3 | 281 | resets = <&usb_clocks RST_USB0_PHY>; |
1af5d192 CYT |
282 | reset-names = "phy"; |
283 | status = "disabled"; | |
284 | #phy-cells = <0>; | |
285 | }; | |
286 | ||
5841f6c0 | 287 | ehci1: usb@a01000 { |
70472163 CYT |
288 | compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; |
289 | reg = <0x00a01000 0x100>; | |
290 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
64507fe3 CYT |
291 | clocks = <&usb_clocks CLK_BUS_HCI1>; |
292 | resets = <&usb_clocks RST_USB1_HCI>; | |
70472163 CYT |
293 | phys = <&usbphy2>; |
294 | phy-names = "usb"; | |
295 | status = "disabled"; | |
296 | }; | |
297 | ||
5841f6c0 | 298 | usbphy2: phy@a01800 { |
1af5d192 CYT |
299 | compatible = "allwinner,sun9i-a80-usb-phy"; |
300 | reg = <0x00a01800 0x4>; | |
64507fe3 CYT |
301 | clocks = <&usb_clocks CLK_USB1_HSIC>, |
302 | <&usb_clocks CLK_USB_HSIC>, | |
303 | <&usb_clocks CLK_USB1_PHY>; | |
304 | clock-names = "hsic_480M", | |
305 | "hsic_12M", | |
306 | "phy"; | |
307 | resets = <&usb_clocks RST_USB1_HSIC>, | |
308 | <&usb_clocks RST_USB1_PHY>; | |
309 | reset-names = "hsic", | |
310 | "phy"; | |
1af5d192 CYT |
311 | status = "disabled"; |
312 | #phy-cells = <0>; | |
313 | /* usb1 is always used with HSIC */ | |
314 | phy_type = "hsic"; | |
315 | }; | |
316 | ||
5841f6c0 | 317 | ehci2: usb@a02000 { |
70472163 CYT |
318 | compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; |
319 | reg = <0x00a02000 0x100>; | |
320 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
64507fe3 CYT |
321 | clocks = <&usb_clocks CLK_BUS_HCI2>; |
322 | resets = <&usb_clocks RST_USB2_HCI>; | |
70472163 CYT |
323 | phys = <&usbphy3>; |
324 | phy-names = "usb"; | |
325 | status = "disabled"; | |
326 | }; | |
327 | ||
5841f6c0 | 328 | ohci2: usb@a02400 { |
70472163 CYT |
329 | compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; |
330 | reg = <0x00a02400 0x100>; | |
331 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
64507fe3 CYT |
332 | clocks = <&usb_clocks CLK_BUS_HCI2>, |
333 | <&usb_clocks CLK_USB_OHCI2>; | |
334 | resets = <&usb_clocks RST_USB2_HCI>; | |
70472163 CYT |
335 | phys = <&usbphy3>; |
336 | phy-names = "usb"; | |
337 | status = "disabled"; | |
338 | }; | |
339 | ||
5841f6c0 | 340 | usbphy3: phy@a02800 { |
1af5d192 CYT |
341 | compatible = "allwinner,sun9i-a80-usb-phy"; |
342 | reg = <0x00a02800 0x4>; | |
64507fe3 CYT |
343 | clocks = <&usb_clocks CLK_USB2_HSIC>, |
344 | <&usb_clocks CLK_USB_HSIC>, | |
345 | <&usb_clocks CLK_USB2_PHY>; | |
346 | clock-names = "hsic_480M", | |
347 | "hsic_12M", | |
348 | "phy"; | |
349 | resets = <&usb_clocks RST_USB2_HSIC>, | |
350 | <&usb_clocks RST_USB2_PHY>; | |
351 | reset-names = "hsic", | |
352 | "phy"; | |
1af5d192 CYT |
353 | status = "disabled"; |
354 | #phy-cells = <0>; | |
355 | }; | |
356 | ||
5841f6c0 | 357 | usb_clocks: clock@a08000 { |
64507fe3 CYT |
358 | compatible = "allwinner,sun9i-a80-usb-clks"; |
359 | reg = <0x00a08000 0x8>; | |
360 | clocks = <&ccu CLK_BUS_USB>, <&osc24M>; | |
361 | clock-names = "bus", "hosc"; | |
362 | #clock-cells = <1>; | |
363 | #reset-cells = <1>; | |
364 | }; | |
365 | ||
61cf3ed0 CYT |
366 | cpucfg@1700000 { |
367 | compatible = "allwinner,sun9i-a80-cpucfg"; | |
368 | reg = <0x01700000 0x100>; | |
369 | }; | |
370 | ||
5841f6c0 | 371 | mmc0: mmc@1c0f000 { |
3a952213 | 372 | compatible = "allwinner,sun9i-a80-mmc"; |
2f6941cd | 373 | reg = <0x01c0f000 0x1000>; |
64507fe3 CYT |
374 | clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, |
375 | <&ccu CLK_MMC0_OUTPUT>, | |
376 | <&ccu CLK_MMC0_SAMPLE>; | |
2f6941cd CYT |
377 | clock-names = "ahb", "mmc", "output", "sample"; |
378 | resets = <&mmc_config_clk 0>; | |
379 | reset-names = "ahb"; | |
380 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
381 | status = "disabled"; | |
4c1bb9c3 HG |
382 | #address-cells = <1>; |
383 | #size-cells = <0>; | |
2f6941cd CYT |
384 | }; |
385 | ||
5841f6c0 | 386 | mmc1: mmc@1c10000 { |
3a952213 | 387 | compatible = "allwinner,sun9i-a80-mmc"; |
2f6941cd | 388 | reg = <0x01c10000 0x1000>; |
64507fe3 CYT |
389 | clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, |
390 | <&ccu CLK_MMC1_OUTPUT>, | |
391 | <&ccu CLK_MMC1_SAMPLE>; | |
2f6941cd CYT |
392 | clock-names = "ahb", "mmc", "output", "sample"; |
393 | resets = <&mmc_config_clk 1>; | |
394 | reset-names = "ahb"; | |
395 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
396 | status = "disabled"; | |
4c1bb9c3 HG |
397 | #address-cells = <1>; |
398 | #size-cells = <0>; | |
2f6941cd CYT |
399 | }; |
400 | ||
5841f6c0 | 401 | mmc2: mmc@1c11000 { |
3a952213 | 402 | compatible = "allwinner,sun9i-a80-mmc"; |
2f6941cd | 403 | reg = <0x01c11000 0x1000>; |
64507fe3 CYT |
404 | clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, |
405 | <&ccu CLK_MMC2_OUTPUT>, | |
406 | <&ccu CLK_MMC2_SAMPLE>; | |
2f6941cd CYT |
407 | clock-names = "ahb", "mmc", "output", "sample"; |
408 | resets = <&mmc_config_clk 2>; | |
409 | reset-names = "ahb"; | |
410 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
411 | status = "disabled"; | |
4c1bb9c3 HG |
412 | #address-cells = <1>; |
413 | #size-cells = <0>; | |
2f6941cd CYT |
414 | }; |
415 | ||
5841f6c0 | 416 | mmc3: mmc@1c12000 { |
3a952213 | 417 | compatible = "allwinner,sun9i-a80-mmc"; |
2f6941cd | 418 | reg = <0x01c12000 0x1000>; |
64507fe3 CYT |
419 | clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, |
420 | <&ccu CLK_MMC3_OUTPUT>, | |
421 | <&ccu CLK_MMC3_SAMPLE>; | |
2f6941cd CYT |
422 | clock-names = "ahb", "mmc", "output", "sample"; |
423 | resets = <&mmc_config_clk 3>; | |
424 | reset-names = "ahb"; | |
425 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
426 | status = "disabled"; | |
4c1bb9c3 HG |
427 | #address-cells = <1>; |
428 | #size-cells = <0>; | |
2f6941cd CYT |
429 | }; |
430 | ||
5841f6c0 | 431 | mmc_config_clk: clk@1c13000 { |
9c56f3f3 CYT |
432 | compatible = "allwinner,sun9i-a80-mmc-config-clk"; |
433 | reg = <0x01c13000 0x10>; | |
64507fe3 | 434 | clocks = <&ccu CLK_BUS_MMC>; |
9c56f3f3 | 435 | clock-names = "ahb"; |
64507fe3 | 436 | resets = <&ccu RST_BUS_MMC>; |
9c56f3f3 CYT |
437 | reset-names = "ahb"; |
438 | #clock-cells = <1>; | |
439 | #reset-cells = <1>; | |
440 | clock-output-names = "mmc0_config", "mmc1_config", | |
441 | "mmc2_config", "mmc3_config"; | |
442 | }; | |
443 | ||
5841f6c0 | 444 | gic: interrupt-controller@1c41000 { |
4ab328f0 CYT |
445 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
446 | reg = <0x01c41000 0x1000>, | |
387720c9 | 447 | <0x01c42000 0x2000>, |
4ab328f0 CYT |
448 | <0x01c44000 0x2000>, |
449 | <0x01c46000 0x2000>; | |
450 | interrupt-controller; | |
451 | #interrupt-cells = <3>; | |
19882b84 | 452 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
4ab328f0 CYT |
453 | }; |
454 | ||
f0b55841 CYT |
455 | cci: cci@1c90000 { |
456 | compatible = "arm,cci-400"; | |
457 | #address-cells = <1>; | |
458 | #size-cells = <1>; | |
459 | reg = <0x01c90000 0x1000>; | |
460 | ranges = <0x0 0x01c90000 0x10000>; | |
461 | ||
462 | cci_control0: slave-if@4000 { | |
463 | compatible = "arm,cci-400-ctrl-if"; | |
464 | interface-type = "ace"; | |
465 | reg = <0x4000 0x1000>; | |
466 | }; | |
467 | ||
468 | cci_control1: slave-if@5000 { | |
469 | compatible = "arm,cci-400-ctrl-if"; | |
470 | interface-type = "ace"; | |
471 | reg = <0x5000 0x1000>; | |
472 | }; | |
473 | ||
474 | pmu@9000 { | |
475 | compatible = "arm,cci-400-pmu,r1"; | |
476 | reg = <0x9000 0x5000>; | |
477 | interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
478 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
479 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
480 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
481 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
482 | }; | |
483 | }; | |
484 | ||
5841f6c0 | 485 | de_clocks: clock@3000000 { |
64507fe3 CYT |
486 | compatible = "allwinner,sun9i-a80-de-clks"; |
487 | reg = <0x03000000 0x30>; | |
488 | clocks = <&ccu CLK_DE>, | |
489 | <&ccu CLK_SDRAM>, | |
490 | <&ccu CLK_BUS_DE>; | |
491 | clock-names = "mod", | |
492 | "dram", | |
493 | "bus"; | |
494 | resets = <&ccu RST_BUS_DE>; | |
495 | #clock-cells = <1>; | |
ac399a97 | 496 | #reset-cells = <1>; |
ac399a97 CYT |
497 | }; |
498 | ||
5841f6c0 | 499 | ccu: clock@6000000 { |
64507fe3 CYT |
500 | compatible = "allwinner,sun9i-a80-ccu"; |
501 | reg = <0x06000000 0x800>; | |
502 | clocks = <&osc24M>, <&osc32k>; | |
503 | clock-names = "hosc", "losc"; | |
504 | #clock-cells = <1>; | |
ac399a97 | 505 | #reset-cells = <1>; |
ac399a97 CYT |
506 | }; |
507 | ||
5841f6c0 | 508 | timer@6000c00 { |
4ab328f0 CYT |
509 | compatible = "allwinner,sun4i-a10-timer"; |
510 | reg = <0x06000c00 0xa0>; | |
19882b84 MR |
511 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
512 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, | |
513 | <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, | |
514 | <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, | |
515 | <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, | |
516 | <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
4ab328f0 CYT |
517 | |
518 | clocks = <&osc24M>; | |
519 | }; | |
520 | ||
5841f6c0 | 521 | wdt: watchdog@6000ca0 { |
6d6693c8 CYT |
522 | compatible = "allwinner,sun6i-a31-wdt"; |
523 | reg = <0x06000ca0 0x20>; | |
524 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
525 | }; | |
526 | ||
5841f6c0 | 527 | pio: pinctrl@6000800 { |
43d024d3 MR |
528 | compatible = "allwinner,sun9i-a80-pinctrl"; |
529 | reg = <0x06000800 0x400>; | |
19882b84 MR |
530 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
531 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | |
532 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | |
533 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, | |
534 | <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
64507fe3 | 535 | clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; |
be7bc6b9 | 536 | clock-names = "apb", "hosc", "losc"; |
43d024d3 MR |
537 | gpio-controller; |
538 | interrupt-controller; | |
6d55d339 | 539 | #interrupt-cells = <3>; |
43d024d3 MR |
540 | #size-cells = <0>; |
541 | #gpio-cells = <3>; | |
888366fa | 542 | |
d177864f | 543 | i2c3_pins: i2c3-pins { |
1edcd36f MR |
544 | pins = "PG10", "PG11"; |
545 | function = "i2c3"; | |
6657a058 CYT |
546 | }; |
547 | ||
d177864f | 548 | mmc0_pins: mmc0-pins { |
1edcd36f MR |
549 | pins = "PF0", "PF1" ,"PF2", "PF3", |
550 | "PF4", "PF5"; | |
551 | function = "mmc0"; | |
552 | drive-strength = <30>; | |
80ee72e7 | 553 | bias-pull-up; |
cd23e2e5 CYT |
554 | }; |
555 | ||
d177864f | 556 | mmc1_pins: mmc1-pins { |
1edcd36f | 557 | pins = "PG0", "PG1" ,"PG2", "PG3", |
56b07301 | 558 | "PG4", "PG5"; |
1edcd36f MR |
559 | function = "mmc1"; |
560 | drive-strength = <30>; | |
80ee72e7 | 561 | bias-pull-up; |
56b07301 CYT |
562 | }; |
563 | ||
d177864f | 564 | mmc2_8bit_pins: mmc2-8bit-pins { |
1edcd36f MR |
565 | pins = "PC6", "PC7", "PC8", "PC9", |
566 | "PC10", "PC11", "PC12", | |
567 | "PC13", "PC14", "PC15", | |
568 | "PC16"; | |
569 | function = "mmc2"; | |
570 | drive-strength = <30>; | |
80ee72e7 | 571 | bias-pull-up; |
6657a058 CYT |
572 | }; |
573 | ||
d177864f | 574 | uart0_ph_pins: uart0-ph-pins { |
1edcd36f MR |
575 | pins = "PH12", "PH13"; |
576 | function = "uart0"; | |
888366fa | 577 | }; |
2a950b2c | 578 | |
d177864f | 579 | uart4_pins: uart4-pins { |
1edcd36f MR |
580 | pins = "PG12", "PG13", "PG14", "PG15"; |
581 | function = "uart4"; | |
2a950b2c | 582 | }; |
43d024d3 MR |
583 | }; |
584 | ||
5841f6c0 | 585 | uart0: serial@7000000 { |
4ab328f0 CYT |
586 | compatible = "snps,dw-apb-uart"; |
587 | reg = <0x07000000 0x400>; | |
19882b84 | 588 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
589 | reg-shift = <2>; |
590 | reg-io-width = <4>; | |
64507fe3 CYT |
591 | clocks = <&ccu CLK_BUS_UART0>; |
592 | resets = <&ccu RST_BUS_UART0>; | |
4ab328f0 CYT |
593 | status = "disabled"; |
594 | }; | |
595 | ||
5841f6c0 | 596 | uart1: serial@7000400 { |
4ab328f0 CYT |
597 | compatible = "snps,dw-apb-uart"; |
598 | reg = <0x07000400 0x400>; | |
19882b84 | 599 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
600 | reg-shift = <2>; |
601 | reg-io-width = <4>; | |
64507fe3 CYT |
602 | clocks = <&ccu CLK_BUS_UART1>; |
603 | resets = <&ccu RST_BUS_UART1>; | |
4ab328f0 CYT |
604 | status = "disabled"; |
605 | }; | |
606 | ||
5841f6c0 | 607 | uart2: serial@7000800 { |
4ab328f0 CYT |
608 | compatible = "snps,dw-apb-uart"; |
609 | reg = <0x07000800 0x400>; | |
19882b84 | 610 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
611 | reg-shift = <2>; |
612 | reg-io-width = <4>; | |
64507fe3 CYT |
613 | clocks = <&ccu CLK_BUS_UART2>; |
614 | resets = <&ccu RST_BUS_UART2>; | |
4ab328f0 CYT |
615 | status = "disabled"; |
616 | }; | |
617 | ||
5841f6c0 | 618 | uart3: serial@7000c00 { |
4ab328f0 CYT |
619 | compatible = "snps,dw-apb-uart"; |
620 | reg = <0x07000c00 0x400>; | |
19882b84 | 621 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
622 | reg-shift = <2>; |
623 | reg-io-width = <4>; | |
64507fe3 CYT |
624 | clocks = <&ccu CLK_BUS_UART3>; |
625 | resets = <&ccu RST_BUS_UART3>; | |
4ab328f0 CYT |
626 | status = "disabled"; |
627 | }; | |
628 | ||
5841f6c0 | 629 | uart4: serial@7001000 { |
4ab328f0 CYT |
630 | compatible = "snps,dw-apb-uart"; |
631 | reg = <0x07001000 0x400>; | |
19882b84 | 632 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
633 | reg-shift = <2>; |
634 | reg-io-width = <4>; | |
64507fe3 CYT |
635 | clocks = <&ccu CLK_BUS_UART4>; |
636 | resets = <&ccu RST_BUS_UART4>; | |
4ab328f0 CYT |
637 | status = "disabled"; |
638 | }; | |
639 | ||
5841f6c0 | 640 | uart5: serial@7001400 { |
4ab328f0 CYT |
641 | compatible = "snps,dw-apb-uart"; |
642 | reg = <0x07001400 0x400>; | |
19882b84 | 643 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
644 | reg-shift = <2>; |
645 | reg-io-width = <4>; | |
64507fe3 CYT |
646 | clocks = <&ccu CLK_BUS_UART5>; |
647 | resets = <&ccu RST_BUS_UART5>; | |
4ab328f0 CYT |
648 | status = "disabled"; |
649 | }; | |
650 | ||
5841f6c0 | 651 | i2c0: i2c@7002800 { |
e4aa753a CYT |
652 | compatible = "allwinner,sun6i-a31-i2c"; |
653 | reg = <0x07002800 0x400>; | |
19882b84 | 654 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
64507fe3 CYT |
655 | clocks = <&ccu CLK_BUS_I2C0>; |
656 | resets = <&ccu RST_BUS_I2C0>; | |
e4aa753a CYT |
657 | status = "disabled"; |
658 | #address-cells = <1>; | |
659 | #size-cells = <0>; | |
660 | }; | |
661 | ||
5841f6c0 | 662 | i2c1: i2c@7002c00 { |
e4aa753a CYT |
663 | compatible = "allwinner,sun6i-a31-i2c"; |
664 | reg = <0x07002c00 0x400>; | |
19882b84 | 665 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
64507fe3 CYT |
666 | clocks = <&ccu CLK_BUS_I2C1>; |
667 | resets = <&ccu RST_BUS_I2C1>; | |
e4aa753a CYT |
668 | status = "disabled"; |
669 | #address-cells = <1>; | |
670 | #size-cells = <0>; | |
671 | }; | |
672 | ||
5841f6c0 | 673 | i2c2: i2c@7003000 { |
e4aa753a CYT |
674 | compatible = "allwinner,sun6i-a31-i2c"; |
675 | reg = <0x07003000 0x400>; | |
19882b84 | 676 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
64507fe3 CYT |
677 | clocks = <&ccu CLK_BUS_I2C2>; |
678 | resets = <&ccu RST_BUS_I2C2>; | |
e4aa753a CYT |
679 | status = "disabled"; |
680 | #address-cells = <1>; | |
681 | #size-cells = <0>; | |
682 | }; | |
683 | ||
5841f6c0 | 684 | i2c3: i2c@7003400 { |
e4aa753a CYT |
685 | compatible = "allwinner,sun6i-a31-i2c"; |
686 | reg = <0x07003400 0x400>; | |
19882b84 | 687 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
64507fe3 CYT |
688 | clocks = <&ccu CLK_BUS_I2C3>; |
689 | resets = <&ccu RST_BUS_I2C3>; | |
e4aa753a CYT |
690 | status = "disabled"; |
691 | #address-cells = <1>; | |
692 | #size-cells = <0>; | |
693 | }; | |
694 | ||
5841f6c0 | 695 | i2c4: i2c@7003800 { |
e4aa753a CYT |
696 | compatible = "allwinner,sun6i-a31-i2c"; |
697 | reg = <0x07003800 0x400>; | |
19882b84 | 698 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
64507fe3 CYT |
699 | clocks = <&ccu CLK_BUS_I2C4>; |
700 | resets = <&ccu RST_BUS_I2C4>; | |
e4aa753a CYT |
701 | status = "disabled"; |
702 | #address-cells = <1>; | |
703 | #size-cells = <0>; | |
704 | }; | |
705 | ||
5841f6c0 | 706 | r_wdt: watchdog@8001000 { |
4ab328f0 CYT |
707 | compatible = "allwinner,sun6i-a31-wdt"; |
708 | reg = <0x08001000 0x20>; | |
19882b84 | 709 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
710 | }; |
711 | ||
fd4b0c33 CYT |
712 | prcm@8001400 { |
713 | compatible = "allwinner,sun9i-a80-prcm"; | |
714 | reg = <0x08001400 0x200>; | |
715 | }; | |
716 | ||
5841f6c0 | 717 | apbs_rst: reset@80014b0 { |
afd7d66c CYT |
718 | reg = <0x080014b0 0x4>; |
719 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
720 | #reset-cells = <1>; | |
721 | }; | |
722 | ||
5841f6c0 | 723 | nmi_intc: interrupt-controller@80015a0 { |
67e1cbfb CYT |
724 | compatible = "allwinner,sun9i-a80-nmi"; |
725 | interrupt-controller; | |
726 | #interrupt-cells = <2>; | |
727 | reg = <0x080015a0 0xc>; | |
728 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
729 | }; | |
730 | ||
5841f6c0 | 731 | r_ir: ir@8002000 { |
1595b37c CYT |
732 | compatible = "allwinner,sun5i-a13-ir"; |
733 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
734 | pinctrl-names = "default"; | |
735 | pinctrl-0 = <&r_ir_pins>; | |
736 | clocks = <&apbs_gates 1>, <&r_ir_clk>; | |
737 | clock-names = "apb", "ir"; | |
738 | resets = <&apbs_rst 1>; | |
739 | reg = <0x08002000 0x40>; | |
740 | status = "disabled"; | |
741 | }; | |
742 | ||
5841f6c0 | 743 | r_uart: serial@8002800 { |
4ab328f0 CYT |
744 | compatible = "snps,dw-apb-uart"; |
745 | reg = <0x08002800 0x400>; | |
19882b84 | 746 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
747 | reg-shift = <2>; |
748 | reg-io-width = <4>; | |
afd7d66c CYT |
749 | clocks = <&apbs_gates 4>; |
750 | resets = <&apbs_rst 4>; | |
4ab328f0 CYT |
751 | status = "disabled"; |
752 | }; | |
1ac56a6d | 753 | |
5841f6c0 | 754 | r_pio: pinctrl@8002c00 { |
1ac56a6d CYT |
755 | compatible = "allwinner,sun9i-a80-r-pinctrl"; |
756 | reg = <0x08002c00 0x400>; | |
757 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
758 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
be7bc6b9 MR |
759 | clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; |
760 | clock-names = "apb", "hosc", "losc"; | |
1ac56a6d CYT |
761 | resets = <&apbs_rst 0>; |
762 | gpio-controller; | |
763 | interrupt-controller; | |
06ad11be | 764 | #interrupt-cells = <3>; |
1ac56a6d | 765 | #gpio-cells = <3>; |
1595b37c | 766 | |
00a7088f | 767 | r_ir_pins: r-ir-pins { |
1edcd36f MR |
768 | pins = "PL6"; |
769 | function = "s_cir_rx"; | |
1595b37c | 770 | }; |
ed473ebd | 771 | |
00a7088f | 772 | r_rsb_pins: r-rsb-pins { |
1edcd36f MR |
773 | pins = "PN0", "PN1"; |
774 | function = "s_rsb"; | |
775 | drive-strength = <20>; | |
776 | bias-pull-up; | |
ed473ebd CYT |
777 | }; |
778 | }; | |
779 | ||
5841f6c0 | 780 | r_rsb: i2c@8003400 { |
ed473ebd CYT |
781 | compatible = "allwinner,sun8i-a23-rsb"; |
782 | reg = <0x08003400 0x400>; | |
783 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
784 | clocks = <&apbs_gates 3>; | |
785 | clock-frequency = <3000000>; | |
786 | resets = <&apbs_rst 3>; | |
787 | pinctrl-names = "default"; | |
788 | pinctrl-0 = <&r_rsb_pins>; | |
789 | status = "disabled"; | |
790 | #address-cells = <1>; | |
791 | #size-cells = <0>; | |
1ac56a6d | 792 | }; |
4ab328f0 CYT |
793 | }; |
794 | }; |