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ARM: dts: sun9i: Add A80 GMAC RGMII pinmux setting
[linux-2.6-block.git] / arch / arm / boot / dts / sun9i-a80.dtsi
CommitLineData
4ab328f0
CYT		 1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
136d18a8 11 * a) This file is free software; you can redistribute it and/or
4ab328f0
CYT		 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
136d18a8 16 * This file is distributed in the hope that it will be useful,
4ab328f0
CYT		 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
4ab328f0
CYT		 21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
19882b84
MR		 45#include <dt-bindings/interrupt-controller/arm-gic.h>
46
64507fe3
CYT		 47#include <dt-bindings/clock/sun9i-a80-ccu.h>
48#include <dt-bindings/clock/sun9i-a80-de.h>
49#include <dt-bindings/clock/sun9i-a80-usb.h>
50#include <dt-bindings/reset/sun9i-a80-ccu.h>
51#include <dt-bindings/reset/sun9i-a80-de.h>
52#include <dt-bindings/reset/sun9i-a80-usb.h>
53
4ab328f0 54/ {
98dc89db
MR		 55 #address-cells = <2>;
56 #size-cells = <2>;
4ab328f0
CYT		 57 interrupt-parent = <&gic>;
58
6fa39a54
CYT		 59 aliases {
60 ethernet0 = &gmac;
61 };
62
4ab328f0
CYT		 63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu0: cpu@0 {
68 compatible = "arm,cortex-a7";
69 device_type = "cpu";
f0b55841
CYT		 70 cci-control-port = <&cci_control0>;
71 clock-frequency = <12000000>;
651f97f5 72 enable-method = "allwinner,sun9i-a80-smp";
4ab328f0
CYT		 73 reg = <0x0>;
74 };
75
76 cpu1: cpu@1 {
77 compatible = "arm,cortex-a7";
78 device_type = "cpu";
f0b55841
CYT		 79 cci-control-port = <&cci_control0>;
80 clock-frequency = <12000000>;
651f97f5 81 enable-method = "allwinner,sun9i-a80-smp";
4ab328f0
CYT		 82 reg = <0x1>;
83 };
84
85 cpu2: cpu@2 {
86 compatible = "arm,cortex-a7";
87 device_type = "cpu";
f0b55841
CYT		 88 cci-control-port = <&cci_control0>;
89 clock-frequency = <12000000>;
651f97f5 90 enable-method = "allwinner,sun9i-a80-smp";
4ab328f0
CYT		 91 reg = <0x2>;
92 };
93
94 cpu3: cpu@3 {
95 compatible = "arm,cortex-a7";
96 device_type = "cpu";
f0b55841
CYT		 97 cci-control-port = <&cci_control0>;
98 clock-frequency = <12000000>;
651f97f5 99 enable-method = "allwinner,sun9i-a80-smp";
4ab328f0
CYT		 100 reg = <0x3>;
101 };
102
103 cpu4: cpu@100 {
104 compatible = "arm,cortex-a15";
105 device_type = "cpu";
f0b55841
CYT		 106 cci-control-port = <&cci_control1>;
107 clock-frequency = <18000000>;
651f97f5 108 enable-method = "allwinner,sun9i-a80-smp";
4ab328f0
CYT		 109 reg = <0x100>;
110 };
111
112 cpu5: cpu@101 {
113 compatible = "arm,cortex-a15";
114 device_type = "cpu";
f0b55841
CYT		 115 cci-control-port = <&cci_control1>;
116 clock-frequency = <18000000>;
651f97f5 117 enable-method = "allwinner,sun9i-a80-smp";
4ab328f0
CYT		 118 reg = <0x101>;
119 };
120
121 cpu6: cpu@102 {
122 compatible = "arm,cortex-a15";
123 device_type = "cpu";
f0b55841
CYT		 124 cci-control-port = <&cci_control1>;
125 clock-frequency = <18000000>;
651f97f5 126 enable-method = "allwinner,sun9i-a80-smp";
4ab328f0
CYT		 127 reg = <0x102>;
128 };
129
130 cpu7: cpu@103 {
131 compatible = "arm,cortex-a15";
132 device_type = "cpu";
f0b55841
CYT		 133 cci-control-port = <&cci_control1>;
134 clock-frequency = <18000000>;
651f97f5 135 enable-method = "allwinner,sun9i-a80-smp";
4ab328f0
CYT		 136 reg = <0x103>;
137 };
138 };
139
51e9f5ff
CYT		 140 timer {
141 compatible = "arm,armv7-timer";
142 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
143 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
144 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
145 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
146 clock-frequency = <24000000>;
147 arm,cpu-registers-not-fw-configured;
148 };
149
4ab328f0
CYT		 150 clocks {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 /*
154 * map 64 bit address range down to 32 bits,
155 * as the peripherals are all under 512MB.
156 */
157 ranges = <0 0 0 0x20000000>;
158
d255abd6
CYT		 159 /*
160 * This clock is actually configurable from the PRCM address
161 * space. The external 24M oscillator can be turned off, and
162 * the clock switched to an internal 16M RC oscillator. Under
163 * normal operation there's no reason to do this, and the
164 * default is to use the external good one, so just model this
165 * as a fixed clock. Also it is not entirely clear if the
166 * osc24M mux in the PRCM affects the entire clock tree, which
167 * would also throw all the PLL clock rates off, or just the
168 * downstream clocks in the PRCM.
169 */
00a7088f 170 osc24M: clk-24M {
4ab328f0
CYT		 171 #clock-cells = <0>;
172 compatible = "fixed-clock";
173 clock-frequency = <24000000>;
174 clock-output-names = "osc24M";
175 };
176
d255abd6
CYT		 177 /*
178 * The 32k clock is from an external source, normally the
16266987
CYT		 179 * AC100 codec/RTC chip. This serves as a placeholder for
180 * board dts files to specify the source.
d255abd6 181 */
00a7088f 182 osc32k: clk-32k {
4ab328f0 183 #clock-cells = <0>;
16266987
CYT		 184 compatible = "fixed-factor-clock";
185 clock-div = <1>;
186 clock-mult = <1>;
4ab328f0
CYT		 187 clock-output-names = "osc32k";
188 };
ac399a97 189
e78adcfe
CYT		 190 /*
191 * The following two are dummy clocks, placeholders
192 * used in the gmac_tx clock. The gmac driver will
193 * choose one parent depending on the PHY interface
194 * mode, using clk_set_rate auto-reparenting.
195 *
196 * The actual TX clock rate is not controlled by the
197 * gmac_tx clock.
198 */
199 mii_phy_tx_clk: mii_phy_tx_clk {
200 #clock-cells = <0>;
201 compatible = "fixed-clock";
202 clock-frequency = <25000000>;
203 clock-output-names = "mii_phy_tx";
204 };
205
206 gmac_int_tx_clk: gmac_int_tx_clk {
207 #clock-cells = <0>;
208 compatible = "fixed-clock";
209 clock-frequency = <125000000>;
210 clock-output-names = "gmac_int_tx";
211 };
212
213 gmac_tx_clk: clk@800030 {
214 #clock-cells = <0>;
215 compatible = "allwinner,sun7i-a20-gmac-clk";
216 reg = <0x00800030 0x4>;
217 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
218 clock-output-names = "gmac_tx";
219 };
220
5841f6c0 221 cpus_clk: clk@8001410 {
afd7d66c
CYT		 222 compatible = "allwinner,sun9i-a80-cpus-clk";
223 reg = <0x08001410 0x4>;
224 #clock-cells = <0>;
64507fe3
CYT		 225 clocks = <&osc32k>, <&osc24M>,
226 <&ccu CLK_PLL_PERIPH0>,
227 <&ccu CLK_PLL_AUDIO>;
afd7d66c
CYT		 228 clock-output-names = "cpus";
229 };
230
00a7088f 231 ahbs: clk-ahbs {
afd7d66c
CYT		 232 compatible = "fixed-factor-clock";
233 #clock-cells = <0>;
234 clock-div = <1>;
235 clock-mult = <1>;
236 clocks = <&cpus_clk>;
237 clock-output-names = "ahbs";
238 };
239
5841f6c0 240 apbs: clk@800141c {
afd7d66c
CYT		 241 compatible = "allwinner,sun8i-a23-apb0-clk";
242 reg = <0x0800141c 0x4>;
243 #clock-cells = <0>;
244 clocks = <&ahbs>;
245 clock-output-names = "apbs";
246 };
247
5841f6c0 248 apbs_gates: clk@8001428 {
afd7d66c
CYT		 249 compatible = "allwinner,sun9i-a80-apbs-gates-clk";
250 reg = <0x08001428 0x4>;
251 #clock-cells = <1>;
252 clocks = <&apbs>;
253 clock-indices = <0>, <1>,
254 <2>, <3>,
255 <4>, <5>,
256 <6>, <7>,
257 <12>, <13>,
258 <16>, <17>,
259 <18>, <20>;
260 clock-output-names = "apbs_pio", "apbs_ir",
261 "apbs_timer", "apbs_rsb",
262 "apbs_uart", "apbs_1wire",
263 "apbs_i2c0", "apbs_i2c1",
264 "apbs_ps2_0", "apbs_ps2_1",
265 "apbs_dma", "apbs_i2s0",
266 "apbs_i2s1", "apbs_twd";
267 };
268
5841f6c0 269 r_1wire_clk: clk@8001450 {
afd7d66c
CYT		 270 reg = <0x08001450 0x4>;
271 #clock-cells = <0>;
272 compatible = "allwinner,sun4i-a10-mod0-clk";
273 clocks = <&osc32k>, <&osc24M>;
274 clock-output-names = "r_1wire";
275 };
276
5841f6c0 277 r_ir_clk: clk@8001454 {
afd7d66c
CYT		 278 reg = <0x08001454 0x4>;
279 #clock-cells = <0>;
280 compatible = "allwinner,sun4i-a10-mod0-clk";
281 clocks = <&osc32k>, <&osc24M>;
282 clock-output-names = "r_ir";
283 };
4ab328f0
CYT		 284 };
285
f1317774
CYT		 286 de: display-engine {
287 compatible = "allwinner,sun9i-a80-display-engine";
288 allwinner,pipelines = <&fe0>, <&fe1>;
289 status = "disabled";
290 };
291
4ab328f0
CYT		 292 soc {
293 compatible = "simple-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
296 /*
297 * map 64 bit address range down to 32 bits,
298 * as the peripherals are all under 512MB.
299 */
300 ranges = <0 0 0 0x20000000>;
301
43f624aa
CYT		 302 sram_b: sram@20000 {
303 /* 256 KiB secure SRAM at 0x20000 */
304 compatible = "mmio-sram";
305 reg = <0x00020000 0x40000>;
306
307 #address-cells = <1>;
308 #size-cells = <1>;
309 ranges = <0 0x00020000 0x40000>;
310
311 smp-sram@1000 {
312 /*
313 * This is checked by BROM to determine if
314 * cpu0 should jump to SMP entry vector
315 */
316 compatible = "allwinner,sun9i-a80-smp-sram";
317 reg = <0x1000 0x8>;
318 };
319 };
320
6fa39a54
CYT		 321 gmac: ethernet@830000 {
322 compatible = "allwinner,sun7i-a20-gmac";
323 reg = <0x00830000 0x1054>;
324 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
325 interrupt-names = "macirq";
326 clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
327 clock-names = "stmmaceth", "allwinner_gmac_tx";
328 resets = <&ccu RST_BUS_GMAC>;
329 reset-names = "stmmaceth";
330 snps,pbl = <2>;
331 snps,fixed-burst;
332 snps,force_sf_dma_mode;
333 status = "disabled";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 };
337
5841f6c0 338 ehci0: usb@a00000 {
70472163
CYT		 339 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
340 reg = <0x00a00000 0x100>;
341 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
64507fe3
CYT		 342 clocks = <&usb_clocks CLK_BUS_HCI0>;
343 resets = <&usb_clocks RST_USB0_HCI>;
70472163
CYT		 344 phys = <&usbphy1>;
345 phy-names = "usb";
346 status = "disabled";
347 };
348
5841f6c0 349 ohci0: usb@a00400 {
70472163
CYT		 350 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
351 reg = <0x00a00400 0x100>;
352 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
64507fe3
CYT		 353 clocks = <&usb_clocks CLK_BUS_HCI0>,
354 <&usb_clocks CLK_USB_OHCI0>;
355 resets = <&usb_clocks RST_USB0_HCI>;
70472163
CYT		 356 phys = <&usbphy1>;
357 phy-names = "usb";
358 status = "disabled";
359 };
360
5841f6c0 361 usbphy1: phy@a00800 {
1af5d192
CYT		 362 compatible = "allwinner,sun9i-a80-usb-phy";
363 reg = <0x00a00800 0x4>;
64507fe3 364 clocks = <&usb_clocks CLK_USB0_PHY>;
1af5d192 365 clock-names = "phy";
64507fe3 366 resets = <&usb_clocks RST_USB0_PHY>;
1af5d192
CYT		 367 reset-names = "phy";
368 status = "disabled";
369 #phy-cells = <0>;
370 };
371
5841f6c0 372 ehci1: usb@a01000 {
70472163
CYT		 373 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
374 reg = <0x00a01000 0x100>;
375 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
64507fe3
CYT		 376 clocks = <&usb_clocks CLK_BUS_HCI1>;
377 resets = <&usb_clocks RST_USB1_HCI>;
70472163
CYT		 378 phys = <&usbphy2>;
379 phy-names = "usb";
380 status = "disabled";
381 };
382
5841f6c0 383 usbphy2: phy@a01800 {
1af5d192
CYT		 384 compatible = "allwinner,sun9i-a80-usb-phy";
385 reg = <0x00a01800 0x4>;
64507fe3
CYT		 386 clocks = <&usb_clocks CLK_USB1_HSIC>,
387 <&usb_clocks CLK_USB_HSIC>,
388 <&usb_clocks CLK_USB1_PHY>;
389 clock-names = "hsic_480M",
390 "hsic_12M",
391 "phy";
392 resets = <&usb_clocks RST_USB1_HSIC>,
393 <&usb_clocks RST_USB1_PHY>;
394 reset-names = "hsic",
395 "phy";
1af5d192
CYT		 396 status = "disabled";
397 #phy-cells = <0>;
398 /* usb1 is always used with HSIC */
399 phy_type = "hsic";
400 };
401
5841f6c0 402 ehci2: usb@a02000 {
70472163
CYT		 403 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
404 reg = <0x00a02000 0x100>;
405 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
64507fe3
CYT		 406 clocks = <&usb_clocks CLK_BUS_HCI2>;
407 resets = <&usb_clocks RST_USB2_HCI>;
70472163
CYT		 408 phys = <&usbphy3>;
409 phy-names = "usb";
410 status = "disabled";
411 };
412
5841f6c0 413 ohci2: usb@a02400 {
70472163
CYT		 414 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
415 reg = <0x00a02400 0x100>;
416 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
64507fe3
CYT		 417 clocks = <&usb_clocks CLK_BUS_HCI2>,
418 <&usb_clocks CLK_USB_OHCI2>;
419 resets = <&usb_clocks RST_USB2_HCI>;
70472163
CYT		 420 phys = <&usbphy3>;
421 phy-names = "usb";
422 status = "disabled";
423 };
424
5841f6c0 425 usbphy3: phy@a02800 {
1af5d192
CYT		 426 compatible = "allwinner,sun9i-a80-usb-phy";
427 reg = <0x00a02800 0x4>;
64507fe3
CYT		 428 clocks = <&usb_clocks CLK_USB2_HSIC>,
429 <&usb_clocks CLK_USB_HSIC>,
430 <&usb_clocks CLK_USB2_PHY>;
431 clock-names = "hsic_480M",
432 "hsic_12M",
433 "phy";
434 resets = <&usb_clocks RST_USB2_HSIC>,
435 <&usb_clocks RST_USB2_PHY>;
436 reset-names = "hsic",
437 "phy";
1af5d192
CYT		 438 status = "disabled";
439 #phy-cells = <0>;
440 };
441
5841f6c0 442 usb_clocks: clock@a08000 {
64507fe3
CYT		 443 compatible = "allwinner,sun9i-a80-usb-clks";
444 reg = <0x00a08000 0x8>;
445 clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
446 clock-names = "bus", "hosc";
447 #clock-cells = <1>;
448 #reset-cells = <1>;
449 };
450
61cf3ed0
CYT		 451 cpucfg@1700000 {
452 compatible = "allwinner,sun9i-a80-cpucfg";
453 reg = <0x01700000 0x100>;
454 };
455
5841f6c0 456 mmc0: mmc@1c0f000 {
3a952213 457 compatible = "allwinner,sun9i-a80-mmc";
2f6941cd 458 reg = <0x01c0f000 0x1000>;
64507fe3
CYT		 459 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
460 <&ccu CLK_MMC0_OUTPUT>,
461 <&ccu CLK_MMC0_SAMPLE>;
2f6941cd
CYT		 462 clock-names = "ahb", "mmc", "output", "sample";
463 resets = <&mmc_config_clk 0>;
464 reset-names = "ahb";
465 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
466 status = "disabled";
4c1bb9c3
HG		 467 #address-cells = <1>;
468 #size-cells = <0>;
2f6941cd
CYT		 469 };
470
5841f6c0 471 mmc1: mmc@1c10000 {
3a952213 472 compatible = "allwinner,sun9i-a80-mmc";
2f6941cd 473 reg = <0x01c10000 0x1000>;
64507fe3
CYT		 474 clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
475 <&ccu CLK_MMC1_OUTPUT>,
476 <&ccu CLK_MMC1_SAMPLE>;
2f6941cd
CYT		 477 clock-names = "ahb", "mmc", "output", "sample";
478 resets = <&mmc_config_clk 1>;
479 reset-names = "ahb";
480 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
481 status = "disabled";
4c1bb9c3
HG		 482 #address-cells = <1>;
483 #size-cells = <0>;
2f6941cd
CYT		 484 };
485
5841f6c0 486 mmc2: mmc@1c11000 {
3a952213 487 compatible = "allwinner,sun9i-a80-mmc";
2f6941cd 488 reg = <0x01c11000 0x1000>;
64507fe3
CYT		 489 clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
490 <&ccu CLK_MMC2_OUTPUT>,
491 <&ccu CLK_MMC2_SAMPLE>;
2f6941cd
CYT		 492 clock-names = "ahb", "mmc", "output", "sample";
493 resets = <&mmc_config_clk 2>;
494 reset-names = "ahb";
495 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
496 status = "disabled";
4c1bb9c3
HG		 497 #address-cells = <1>;
498 #size-cells = <0>;
2f6941cd
CYT		 499 };
500
5841f6c0 501 mmc3: mmc@1c12000 {
3a952213 502 compatible = "allwinner,sun9i-a80-mmc";
2f6941cd 503 reg = <0x01c12000 0x1000>;
64507fe3
CYT		 504 clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
505 <&ccu CLK_MMC3_OUTPUT>,
506 <&ccu CLK_MMC3_SAMPLE>;
2f6941cd
CYT		 507 clock-names = "ahb", "mmc", "output", "sample";
508 resets = <&mmc_config_clk 3>;
509 reset-names = "ahb";
510 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
511 status = "disabled";
4c1bb9c3
HG		 512 #address-cells = <1>;
513 #size-cells = <0>;
2f6941cd
CYT		 514 };
515
5841f6c0 516 mmc_config_clk: clk@1c13000 {
9c56f3f3
CYT		 517 compatible = "allwinner,sun9i-a80-mmc-config-clk";
518 reg = <0x01c13000 0x10>;
64507fe3 519 clocks = <&ccu CLK_BUS_MMC>;
9c56f3f3 520 clock-names = "ahb";
64507fe3 521 resets = <&ccu RST_BUS_MMC>;
9c56f3f3
CYT		 522 reset-names = "ahb";
523 #clock-cells = <1>;
524 #reset-cells = <1>;
525 clock-output-names = "mmc0_config", "mmc1_config",
526 "mmc2_config", "mmc3_config";
527 };
528
5841f6c0 529 gic: interrupt-controller@1c41000 {
4ab328f0
CYT		 530 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
531 reg = <0x01c41000 0x1000>,
387720c9 532 <0x01c42000 0x2000>,
4ab328f0
CYT		 533 <0x01c44000 0x2000>,
534 <0x01c46000 0x2000>;
535 interrupt-controller;
536 #interrupt-cells = <3>;
19882b84 537 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
4ab328f0
CYT		 538 };
539
f0b55841
CYT		 540 cci: cci@1c90000 {
541 compatible = "arm,cci-400";
542 #address-cells = <1>;
543 #size-cells = <1>;
544 reg = <0x01c90000 0x1000>;
545 ranges = <0x0 0x01c90000 0x10000>;
546
547 cci_control0: slave-if@4000 {
548 compatible = "arm,cci-400-ctrl-if";
549 interface-type = "ace";
550 reg = <0x4000 0x1000>;
551 };
552
553 cci_control1: slave-if@5000 {
554 compatible = "arm,cci-400-ctrl-if";
555 interface-type = "ace";
556 reg = <0x5000 0x1000>;
557 };
558
559 pmu@9000 {
560 compatible = "arm,cci-400-pmu,r1";
561 reg = <0x9000 0x5000>;
562 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
567 };
568 };
569
5841f6c0 570 de_clocks: clock@3000000 {
64507fe3
CYT		 571 compatible = "allwinner,sun9i-a80-de-clks";
572 reg = <0x03000000 0x30>;
573 clocks = <&ccu CLK_DE>,
574 <&ccu CLK_SDRAM>,
575 <&ccu CLK_BUS_DE>;
576 clock-names = "mod",
577 "dram",
578 "bus";
579 resets = <&ccu RST_BUS_DE>;
580 #clock-cells = <1>;
ac399a97 581 #reset-cells = <1>;
ac399a97
CYT		 582 };
583
f1317774
CYT		 584 fe0: display-frontend@3100000 {
585 compatible = "allwinner,sun9i-a80-display-frontend";
586 reg = <0x03100000 0x40000>;
587 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
589 <&de_clocks CLK_DRAM_FE0>;
590 clock-names = "ahb", "mod",
591 "ram";
592 resets = <&de_clocks RST_FE0>;
593
594 ports {
595 #address-cells = <1>;
596 #size-cells = <0>;
597
598 fe0_out: port@1 {
599 #address-cells = <1>;
600 #size-cells = <0>;
601 reg = <1>;
602
603 fe0_out_deu0: endpoint@0 {
604 reg = <0>;
605 remote-endpoint = <&deu0_in_fe0>;
606 };
607 };
608 };
609 };
610
611 fe1: display-frontend@3140000 {
612 compatible = "allwinner,sun9i-a80-display-frontend";
613 reg = <0x03140000 0x40000>;
614 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
616 <&de_clocks CLK_DRAM_FE1>;
617 clock-names = "ahb", "mod",
618 "ram";
619 resets = <&de_clocks RST_FE0>;
620
621 ports {
622 #address-cells = <1>;
623 #size-cells = <0>;
624
625 fe1_out: port@1 {
626 #address-cells = <1>;
627 #size-cells = <0>;
628 reg = <1>;
629
630 fe1_out_deu1: endpoint@0 {
631 reg = <0>;
632 remote-endpoint = <&deu1_in_fe1>;
633 };
634 };
635 };
636 };
637
638 be0: display-backend@3200000 {
639 compatible = "allwinner,sun9i-a80-display-backend";
640 reg = <0x03200000 0x40000>;
641 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
643 <&de_clocks CLK_DRAM_BE0>;
644 clock-names = "ahb", "mod",
645 "ram";
646 resets = <&de_clocks RST_BE0>;
647
648 ports {
649 #address-cells = <1>;
650 #size-cells = <0>;
651
652 be0_in: port@0 {
653 #address-cells = <1>;
654 #size-cells = <0>;
655 reg = <0>;
656
657 be0_in_deu0: endpoint@0 {
658 reg = <0>;
659 remote-endpoint = <&deu0_out_be0>;
660 };
661
662 be0_in_deu1: endpoint@1 {
663 reg = <1>;
664 remote-endpoint = <&deu1_out_be0>;
665 };
666 };
667
668 be0_out: port@1 {
669 #address-cells = <1>;
670 #size-cells = <0>;
671 reg = <1>;
672
673 be0_out_drc0: endpoint@0 {
674 reg = <0>;
675 remote-endpoint = <&drc0_in_be0>;
676 };
677 };
678 };
679 };
680
681 be1: display-backend@3240000 {
682 compatible = "allwinner,sun9i-a80-display-backend";
683 reg = <0x03240000 0x40000>;
684 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
686 <&de_clocks CLK_DRAM_BE1>;
687 clock-names = "ahb", "mod",
688 "ram";
689 resets = <&de_clocks RST_BE1>;
690
691 ports {
692 #address-cells = <1>;
693 #size-cells = <0>;
694
695 be1_in: port@0 {
696 #address-cells = <1>;
697 #size-cells = <0>;
698 reg = <0>;
699
700 be1_in_deu0: endpoint@0 {
701 reg = <0>;
702 remote-endpoint = <&deu0_out_be1>;
703 };
704
705 be1_in_deu1: endpoint@1 {
706 reg = <1>;
707 remote-endpoint = <&deu1_out_be1>;
708 };
709 };
710
711 be1_out: port@1 {
712 #address-cells = <1>;
713 #size-cells = <0>;
714 reg = <1>;
715
716 be1_out_drc1: endpoint@0 {
717 reg = <0>;
718 remote-endpoint = <&drc1_in_be1>;
719 };
720 };
721 };
722 };
723
724 deu0: deu@3300000 {
725 compatible = "allwinner,sun9i-a80-deu";
726 reg = <0x03300000 0x40000>;
727 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&de_clocks CLK_BUS_DEU0>,
729 <&de_clocks CLK_IEP_DEU0>,
730 <&de_clocks CLK_DRAM_DEU0>;
731 clock-names = "ahb",
732 "mod",
733 "ram";
734 resets = <&de_clocks RST_DEU0>;
735
736 ports {
737 #address-cells = <1>;
738 #size-cells = <0>;
739
740 deu0_in: port@0 {
741 #address-cells = <1>;
742 #size-cells = <0>;
743 reg = <0>;
744
745 deu0_in_fe0: endpoint@0 {
746 reg = <0>;
747 remote-endpoint = <&fe0_out_deu0>;
748 };
749 };
750
751 deu0_out: port@1 {
752 #address-cells = <1>;
753 #size-cells = <0>;
754 reg = <1>;
755
756 deu0_out_be0: endpoint@0 {
757 reg = <0>;
758 remote-endpoint = <&be0_in_deu0>;
759 };
760
761 deu0_out_be1: endpoint@1 {
762 reg = <1>;
763 remote-endpoint = <&be1_in_deu0>;
764 };
765 };
766 };
767 };
768
769 deu1: deu@3340000 {
770 compatible = "allwinner,sun9i-a80-deu";
771 reg = <0x03340000 0x40000>;
772 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&de_clocks CLK_BUS_DEU1>,
774 <&de_clocks CLK_IEP_DEU1>,
775 <&de_clocks CLK_DRAM_DEU1>;
776 clock-names = "ahb",
777 "mod",
778 "ram";
779 resets = <&de_clocks RST_DEU1>;
780
781 ports {
782 #address-cells = <1>;
783 #size-cells = <0>;
784
785 deu1_in: port@0 {
786 #address-cells = <1>;
787 #size-cells = <0>;
788 reg = <0>;
789
790 deu1_in_fe1: endpoint@0 {
791 reg = <0>;
792 remote-endpoint = <&fe1_out_deu1>;
793 };
794 };
795
796 deu1_out: port@1 {
797 #address-cells = <1>;
798 #size-cells = <0>;
799 reg = <1>;
800
801 deu1_out_be0: endpoint@0 {
802 reg = <0>;
803 remote-endpoint = <&be0_in_deu1>;
804 };
805
806 deu1_out_be1: endpoint@1 {
807 reg = <1>;
808 remote-endpoint = <&be1_in_deu1>;
809 };
810 };
811 };
812 };
813
814 drc0: drc@3400000 {
815 compatible = "allwinner,sun9i-a80-drc";
816 reg = <0x03400000 0x40000>;
817 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&de_clocks CLK_BUS_DRC0>,
819 <&de_clocks CLK_IEP_DRC0>,
820 <&de_clocks CLK_DRAM_DRC0>;
821 clock-names = "ahb",
822 "mod",
823 "ram";
824 resets = <&de_clocks RST_DRC0>;
825
826 ports {
827 #address-cells = <1>;
828 #size-cells = <0>;
829
830 drc0_in: port@0 {
831 #address-cells = <1>;
832 #size-cells = <0>;
833 reg = <0>;
834
835 drc0_in_be0: endpoint@0 {
836 reg = <0>;
837 remote-endpoint = <&be0_out_drc0>;
838 };
839 };
840
841 drc0_out: port@1 {
842 #address-cells = <1>;
843 #size-cells = <0>;
844 reg = <1>;
845
846 drc0_out_tcon0: endpoint@0 {
847 reg = <0>;
848 remote-endpoint = <&tcon0_in_drc0>;
849 };
850 };
851 };
852 };
853
854 drc1: drc@3440000 {
855 compatible = "allwinner,sun9i-a80-drc";
856 reg = <0x03440000 0x40000>;
857 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&de_clocks CLK_BUS_DRC1>,
859 <&de_clocks CLK_IEP_DRC1>,
860 <&de_clocks CLK_DRAM_DRC1>;
861 clock-names = "ahb",
862 "mod",
863 "ram";
864 resets = <&de_clocks RST_DRC1>;
865
866 ports {
867 #address-cells = <1>;
868 #size-cells = <0>;
869
870 drc1_in: port@0 {
871 #address-cells = <1>;
872 #size-cells = <0>;
873 reg = <0>;
874
875 drc1_in_be1: endpoint@0 {
876 reg = <0>;
877 remote-endpoint = <&be1_out_drc1>;
878 };
879 };
880
881 drc1_out: port@1 {
882 #address-cells = <1>;
883 #size-cells = <0>;
884 reg = <1>;
885
886 drc1_out_tcon1: endpoint@0 {
887 reg = <0>;
888 remote-endpoint = <&tcon1_in_drc1>;
889 };
890 };
891 };
892 };
893
894 tcon0: lcd-controller@3c00000 {
895 compatible = "allwinner,sun9i-a80-tcon-lcd";
896 reg = <0x03c00000 0x10000>;
897 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
899 clock-names = "ahb", "tcon-ch0";
900 resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
901 reset-names = "lcd", "edp";
902 clock-output-names = "tcon0-pixel-clock";
903
904 ports {
905 #address-cells = <1>;
906 #size-cells = <0>;
907
908 tcon0_in: port@0 {
909 #address-cells = <1>;
910 #size-cells = <0>;
911 reg = <0>;
912
913 tcon0_in_drc0: endpoint@0 {
914 reg = <0>;
915 remote-endpoint = <&drc0_out_tcon0>;
916 };
917 };
918
919 tcon0_out: port@1 {
920 #address-cells = <1>;
921 #size-cells = <0>;
922 reg = <1>;
923 };
924 };
925 };
926
927 tcon1: lcd-controller@3c10000 {
928 compatible = "allwinner,sun9i-a80-tcon-tv";
929 reg = <0x03c10000 0x10000>;
930 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
932 clock-names = "ahb", "tcon-ch1";
933 resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
934 reset-names = "lcd", "edp";
935
936 ports {
937 #address-cells = <1>;
938 #size-cells = <0>;
939
940 tcon1_in: port@0 {
941 #address-cells = <1>;
942 #size-cells = <0>;
943 reg = <0>;
944
945 tcon1_in_drc1: endpoint@0 {
946 reg = <0>;
947 remote-endpoint = <&drc1_out_tcon1>;
948 };
949 };
950
951 tcon1_out: port@1 {
952 #address-cells = <1>;
953 #size-cells = <0>;
954 reg = <1>;
955 };
956 };
957 };
958
5841f6c0 959 ccu: clock@6000000 {
64507fe3
CYT		 960 compatible = "allwinner,sun9i-a80-ccu";
961 reg = <0x06000000 0x800>;
962 clocks = <&osc24M>, <&osc32k>;
963 clock-names = "hosc", "losc";
964 #clock-cells = <1>;
ac399a97 965 #reset-cells = <1>;
ac399a97
CYT		 966 };
967
5841f6c0 968 timer@6000c00 {
4ab328f0
CYT		 969 compatible = "allwinner,sun4i-a10-timer";
970 reg = <0x06000c00 0xa0>;
19882b84
MR		 971 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 977
978 clocks = <&osc24M>;
979 };
980
5841f6c0 981 wdt: watchdog@6000ca0 {
6d6693c8
CYT		 982 compatible = "allwinner,sun6i-a31-wdt";
983 reg = <0x06000ca0 0x20>;
984 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
985 };
986
5841f6c0 987 pio: pinctrl@6000800 {
43d024d3
MR		 988 compatible = "allwinner,sun9i-a80-pinctrl";
989 reg = <0x06000800 0x400>;
19882b84
MR		 990 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
64507fe3 995 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
be7bc6b9 996 clock-names = "apb", "hosc", "losc";
43d024d3
MR		 997 gpio-controller;
998 interrupt-controller;
6d55d339 999 #interrupt-cells = <3>;
43d024d3
MR		 1000 #size-cells = <0>;
1001 #gpio-cells = <3>;
888366fa 1002
72acaa13
CYT		 1003 gmac_rgmii_pins: gmac-rgmii-pins {
1004 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
1005 "PA4", "PA5", "PA7", "PA8",
1006 "PA9", "PA10", "PA12", "PA13",
1007 "PA15", "PA16", "PA17";
1008 allwinner,function = "gmac";
1009 /*
1010 * data lines in RGMII mode use DDR mode
1011 * and need a higher signal drive strength
1012 */
1013 drive-strength = <40>;
1014 };
1015
d177864f 1016 i2c3_pins: i2c3-pins {
1edcd36f
MR		 1017 pins = "PG10", "PG11";
1018 function = "i2c3";
6657a058
CYT		 1019 };
1020
02104704
CYT		 1021 lcd0_rgb888_pins: lcd0-rgb888-pins {
1022 pins = "PD0", "PD1", "PD2", "PD3",
1023 "PD4", "PD5", "PD6", "PD7",
1024 "PD8", "PD9", "PD10", "PD11",
1025 "PD12", "PD13", "PD14", "PD15",
1026 "PD16", "PD17", "PD18", "PD19",
1027 "PD20", "PD21", "PD22", "PD23",
1028 "PD24", "PD25", "PD26", "PD27";
1029 function = "lcd0";
1030 };
1031
d177864f 1032 mmc0_pins: mmc0-pins {
1edcd36f
MR		 1033 pins = "PF0", "PF1" ,"PF2", "PF3",
1034 "PF4", "PF5";
1035 function = "mmc0";
1036 drive-strength = <30>;
80ee72e7 1037 bias-pull-up;
cd23e2e5
CYT		 1038 };
1039
d177864f 1040 mmc1_pins: mmc1-pins {
1edcd36f 1041 pins = "PG0", "PG1" ,"PG2", "PG3",
56b07301 1042 "PG4", "PG5";
1edcd36f
MR		 1043 function = "mmc1";
1044 drive-strength = <30>;
80ee72e7 1045 bias-pull-up;
56b07301
CYT		 1046 };
1047
d177864f 1048 mmc2_8bit_pins: mmc2-8bit-pins {
1edcd36f
MR		 1049 pins = "PC6", "PC7", "PC8", "PC9",
1050 "PC10", "PC11", "PC12",
1051 "PC13", "PC14", "PC15",
1052 "PC16";
1053 function = "mmc2";
1054 drive-strength = <30>;
80ee72e7 1055 bias-pull-up;
6657a058
CYT		 1056 };
1057
d177864f 1058 uart0_ph_pins: uart0-ph-pins {
1edcd36f
MR		 1059 pins = "PH12", "PH13";
1060 function = "uart0";
888366fa 1061 };
2a950b2c 1062
d177864f 1063 uart4_pins: uart4-pins {
1edcd36f
MR		 1064 pins = "PG12", "PG13", "PG14", "PG15";
1065 function = "uart4";
2a950b2c 1066 };
43d024d3
MR		 1067 };
1068
5841f6c0 1069 uart0: serial@7000000 {
4ab328f0
CYT		 1070 compatible = "snps,dw-apb-uart";
1071 reg = <0x07000000 0x400>;
19882b84 1072 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 1073 reg-shift = <2>;
1074 reg-io-width = <4>;
64507fe3
CYT		 1075 clocks = <&ccu CLK_BUS_UART0>;
1076 resets = <&ccu RST_BUS_UART0>;
4ab328f0
CYT		 1077 status = "disabled";
1078 };
1079
5841f6c0 1080 uart1: serial@7000400 {
4ab328f0
CYT		 1081 compatible = "snps,dw-apb-uart";
1082 reg = <0x07000400 0x400>;
19882b84 1083 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 1084 reg-shift = <2>;
1085 reg-io-width = <4>;
64507fe3
CYT		 1086 clocks = <&ccu CLK_BUS_UART1>;
1087 resets = <&ccu RST_BUS_UART1>;
4ab328f0
CYT		 1088 status = "disabled";
1089 };
1090
5841f6c0 1091 uart2: serial@7000800 {
4ab328f0
CYT		 1092 compatible = "snps,dw-apb-uart";
1093 reg = <0x07000800 0x400>;
19882b84 1094 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 1095 reg-shift = <2>;
1096 reg-io-width = <4>;
64507fe3
CYT		 1097 clocks = <&ccu CLK_BUS_UART2>;
1098 resets = <&ccu RST_BUS_UART2>;
4ab328f0
CYT		 1099 status = "disabled";
1100 };
1101
5841f6c0 1102 uart3: serial@7000c00 {
4ab328f0
CYT		 1103 compatible = "snps,dw-apb-uart";
1104 reg = <0x07000c00 0x400>;
19882b84 1105 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 1106 reg-shift = <2>;
1107 reg-io-width = <4>;
64507fe3
CYT		 1108 clocks = <&ccu CLK_BUS_UART3>;
1109 resets = <&ccu RST_BUS_UART3>;
4ab328f0
CYT		 1110 status = "disabled";
1111 };
1112
5841f6c0 1113 uart4: serial@7001000 {
4ab328f0
CYT		 1114 compatible = "snps,dw-apb-uart";
1115 reg = <0x07001000 0x400>;
19882b84 1116 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 1117 reg-shift = <2>;
1118 reg-io-width = <4>;
64507fe3
CYT		 1119 clocks = <&ccu CLK_BUS_UART4>;
1120 resets = <&ccu RST_BUS_UART4>;
4ab328f0
CYT		 1121 status = "disabled";
1122 };
1123
5841f6c0 1124 uart5: serial@7001400 {
4ab328f0
CYT		 1125 compatible = "snps,dw-apb-uart";
1126 reg = <0x07001400 0x400>;
19882b84 1127 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 1128 reg-shift = <2>;
1129 reg-io-width = <4>;
64507fe3
CYT		 1130 clocks = <&ccu CLK_BUS_UART5>;
1131 resets = <&ccu RST_BUS_UART5>;
4ab328f0
CYT		 1132 status = "disabled";
1133 };
1134
5841f6c0 1135 i2c0: i2c@7002800 {
e4aa753a
CYT		 1136 compatible = "allwinner,sun6i-a31-i2c";
1137 reg = <0x07002800 0x400>;
19882b84 1138 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
64507fe3
CYT		 1139 clocks = <&ccu CLK_BUS_I2C0>;
1140 resets = <&ccu RST_BUS_I2C0>;
e4aa753a
CYT		 1141 status = "disabled";
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1144 };
1145
5841f6c0 1146 i2c1: i2c@7002c00 {
e4aa753a
CYT		 1147 compatible = "allwinner,sun6i-a31-i2c";
1148 reg = <0x07002c00 0x400>;
19882b84 1149 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
64507fe3
CYT		 1150 clocks = <&ccu CLK_BUS_I2C1>;
1151 resets = <&ccu RST_BUS_I2C1>;
e4aa753a
CYT		 1152 status = "disabled";
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1155 };
1156
5841f6c0 1157 i2c2: i2c@7003000 {
e4aa753a
CYT		 1158 compatible = "allwinner,sun6i-a31-i2c";
1159 reg = <0x07003000 0x400>;
19882b84 1160 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
64507fe3
CYT		 1161 clocks = <&ccu CLK_BUS_I2C2>;
1162 resets = <&ccu RST_BUS_I2C2>;
e4aa753a
CYT		 1163 status = "disabled";
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1166 };
1167
5841f6c0 1168 i2c3: i2c@7003400 {
e4aa753a
CYT		 1169 compatible = "allwinner,sun6i-a31-i2c";
1170 reg = <0x07003400 0x400>;
19882b84 1171 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
64507fe3
CYT		 1172 clocks = <&ccu CLK_BUS_I2C3>;
1173 resets = <&ccu RST_BUS_I2C3>;
e4aa753a
CYT		 1174 status = "disabled";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1177 };
1178
5841f6c0 1179 i2c4: i2c@7003800 {
e4aa753a
CYT		 1180 compatible = "allwinner,sun6i-a31-i2c";
1181 reg = <0x07003800 0x400>;
19882b84 1182 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
64507fe3
CYT		 1183 clocks = <&ccu CLK_BUS_I2C4>;
1184 resets = <&ccu RST_BUS_I2C4>;
e4aa753a
CYT		 1185 status = "disabled";
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188 };
1189
5841f6c0 1190 r_wdt: watchdog@8001000 {
4ab328f0
CYT		 1191 compatible = "allwinner,sun6i-a31-wdt";
1192 reg = <0x08001000 0x20>;
19882b84 1193 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 1194 };
1195
fd4b0c33
CYT		 1196 prcm@8001400 {
1197 compatible = "allwinner,sun9i-a80-prcm";
1198 reg = <0x08001400 0x200>;
1199 };
1200
5841f6c0 1201 apbs_rst: reset@80014b0 {
afd7d66c
CYT		 1202 reg = <0x080014b0 0x4>;
1203 compatible = "allwinner,sun6i-a31-clock-reset";
1204 #reset-cells = <1>;
1205 };
1206
5841f6c0 1207 nmi_intc: interrupt-controller@80015a0 {
67e1cbfb
CYT		 1208 compatible = "allwinner,sun9i-a80-nmi";
1209 interrupt-controller;
1210 #interrupt-cells = <2>;
1211 reg = <0x080015a0 0xc>;
1212 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1213 };
1214
5841f6c0 1215 r_ir: ir@8002000 {
1595b37c
CYT		 1216 compatible = "allwinner,sun5i-a13-ir";
1217 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1218 pinctrl-names = "default";
1219 pinctrl-0 = <&r_ir_pins>;
1220 clocks = <&apbs_gates 1>, <&r_ir_clk>;
1221 clock-names = "apb", "ir";
1222 resets = <&apbs_rst 1>;
1223 reg = <0x08002000 0x40>;
1224 status = "disabled";
1225 };
1226
5841f6c0 1227 r_uart: serial@8002800 {
4ab328f0
CYT		 1228 compatible = "snps,dw-apb-uart";
1229 reg = <0x08002800 0x400>;
19882b84 1230 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 1231 reg-shift = <2>;
1232 reg-io-width = <4>;
afd7d66c
CYT		 1233 clocks = <&apbs_gates 4>;
1234 resets = <&apbs_rst 4>;
4ab328f0
CYT		 1235 status = "disabled";
1236 };
1ac56a6d 1237
5841f6c0 1238 r_pio: pinctrl@8002c00 {
1ac56a6d
CYT		 1239 compatible = "allwinner,sun9i-a80-r-pinctrl";
1240 reg = <0x08002c00 0x400>;
1241 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
be7bc6b9
MR		 1243 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
1244 clock-names = "apb", "hosc", "losc";
1ac56a6d
CYT		 1245 resets = <&apbs_rst 0>;
1246 gpio-controller;
1247 interrupt-controller;
06ad11be 1248 #interrupt-cells = <3>;
1ac56a6d 1249 #gpio-cells = <3>;
1595b37c 1250
00a7088f 1251 r_ir_pins: r-ir-pins {
1edcd36f
MR		 1252 pins = "PL6";
1253 function = "s_cir_rx";
1595b37c 1254 };
ed473ebd 1255
00a7088f 1256 r_rsb_pins: r-rsb-pins {
1edcd36f
MR		 1257 pins = "PN0", "PN1";
1258 function = "s_rsb";
1259 drive-strength = <20>;
1260 bias-pull-up;
ed473ebd
CYT		 1261 };
1262 };
1263
57a83c52 1264 r_rsb: rsb@8003400 {
ed473ebd
CYT		 1265 compatible = "allwinner,sun8i-a23-rsb";
1266 reg = <0x08003400 0x400>;
1267 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&apbs_gates 3>;
1269 clock-frequency = <3000000>;
1270 resets = <&apbs_rst 3>;
1271 pinctrl-names = "default";
1272 pinctrl-0 = <&r_rsb_pins>;
1273 status = "disabled";
1274 #address-cells = <1>;
1275 #size-cells = <0>;
1ac56a6d 1276 };
4ab328f0
CYT		 1277 };
1278};
Linux 6.x block layer and io_uring tree(s)