[linux-2.6-block.git] / arch / arm / boot / dts / sun9i-a80.dtsi

/*
 * Copyright 2014 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this library; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/include/ "skeleton64.dtsi"

/ {
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &r_uart;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x1>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x3>;
		};

		cpu4: cpu@100 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0x100>;
		};

		cpu5: cpu@101 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0x101>;
		};

		cpu6: cpu@102 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0x102>;
		};

		cpu7: cpu@103 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0x103>;
		};
	};

	memory {
		/* 8GB max. with LPAE */
		reg = <0 0x20000000 0x02 0>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		/*
		 * map 64 bit address range down to 32 bits,
		 * as the peripherals are all under 512MB.
		 */
		ranges = <0 0 0 0x20000000>;

		osc24M: osc24M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: osc32k_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		/*
		 * map 64 bit address range down to 32 bits,
		 * as the peripherals are all under 512MB.
		 */
		ranges = <0 0 0 0x20000000>;

		gic: interrupt-controller@01c41000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c41000 0x1000>,
			      <0x01c42000 0x1000>,
			      <0x01c44000 0x2000>,
			      <0x01c46000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 0xf04>;
		};

		timer@06000c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x06000c00 0xa0>;
			interrupts = <0 18 4>,
				     <0 19 4>,
				     <0 20 4>,
				     <0 21 4>,
				     <0 22 4>,
				     <0 23 4>;

			clocks = <&osc24M>;
		};

		uart0: serial@07000000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000000 0x400>;
			interrupts = <0 0 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc24M>;
			status = "disabled";
		};

		uart1: serial@07000400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000400 0x400>;
			interrupts = <0 1 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc24M>;
			status = "disabled";
		};

		uart2: serial@07000800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000800 0x400>;
			interrupts = <0 2 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc24M>;
			status = "disabled";
		};

		uart3: serial@07000c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000c00 0x400>;
			interrupts = <0 3 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc24M>;
			status = "disabled";
		};

		uart4: serial@07001000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07001000 0x400>;
			interrupts = <0 4 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc24M>;
			status = "disabled";
		};

		uart5: serial@07001400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07001400 0x400>;
			interrupts = <0 5 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc24M>;
			status = "disabled";
		};

		r_wdt: watchdog@08001000 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x08001000 0x20>;
			interrupts = <0 36 4>;
		};

		r_uart: serial@08002800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x08002800 0x400>;
			interrupts = <0 38 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc24M>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
4ab328f0 CYT	1	/*
	2	* Copyright 2014 Chen-Yu Tsai
	3	*
	4	* Chen-Yu Tsai <wens@csie.org>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public
	22	* License along with this library; if not, write to the Free
	23	* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
	24	* MA 02110-1301 USA
	25	*
	26	* Or, alternatively,
	27	*
	28	* b) Permission is hereby granted, free of charge, to any person
	29	* obtaining a copy of this software and associated documentation
	30	* files (the "Software"), to deal in the Software without
	31	* restriction, including without limitation the rights to use,
	32	* copy, modify, merge, publish, distribute, sublicense, and/or
	33	* sell copies of the Software, and to permit persons to whom the
	34	* Software is furnished to do so, subject to the following
	35	* conditions:
	36	*
	37	* The above copyright notice and this permission notice shall be
	38	* included in all copies or substantial portions of the Software.
	39	*
	40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	41	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	42	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	43	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	44	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	45	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	46	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	47	* OTHER DEALINGS IN THE SOFTWARE.
	48	*/
	49
	50	/include/ "skeleton64.dtsi"
	51
	52	/ {
	53	interrupt-parent = <&gic>;
	54
	55	aliases {
	56	serial0 = &uart0;
	57	serial1 = &uart1;
	58	serial2 = &uart2;
	59	serial3 = &uart3;
	60	serial4 = &uart4;
	61	serial5 = &uart5;
	62	serial6 = &r_uart;
	63	};
	64
65	cpus {
66	#address-cells = <1>;
67	#size-cells = <0>;
68
69	cpu0: cpu@0 {
70	compatible = "arm,cortex-a7";
71	device_type = "cpu";
72	reg = <0x0>;
73	};
74
75	cpu1: cpu@1 {
76	compatible = "arm,cortex-a7";
77	device_type = "cpu";
78	reg = <0x1>;
79	};
80
81	cpu2: cpu@2 {
82	compatible = "arm,cortex-a7";
83	device_type = "cpu";
84	reg = <0x2>;
85	};
86
87	cpu3: cpu@3 {
88	compatible = "arm,cortex-a7";
89	device_type = "cpu";
90	reg = <0x3>;
91	};
92
93	cpu4: cpu@100 {
94	compatible = "arm,cortex-a15";
95	device_type = "cpu";
96	reg = <0x100>;
97	};
98
99	cpu5: cpu@101 {
100	compatible = "arm,cortex-a15";
101	device_type = "cpu";
102	reg = <0x101>;
103	};
104
105	cpu6: cpu@102 {
106	compatible = "arm,cortex-a15";
107	device_type = "cpu";
108	reg = <0x102>;
109	};
110
111	cpu7: cpu@103 {
112	compatible = "arm,cortex-a15";
113	device_type = "cpu";
114	reg = <0x103>;
115	};
116	};
117
118	memory {
119	/* 8GB max. with LPAE */
120	reg = <0 0x20000000 0x02 0>;
121	};
122
123	clocks {
124	#address-cells = <1>;
125	#size-cells = <1>;
126	/*
127	* map 64 bit address range down to 32 bits,
128	* as the peripherals are all under 512MB.
129	*/
130	ranges = <0 0 0 0x20000000>;
131
132	osc24M: osc24M_clk {
133	#clock-cells = <0>;
134	compatible = "fixed-clock";
135	clock-frequency = <24000000>;
136	clock-output-names = "osc24M";
137	};
138
139	osc32k: osc32k_clk {
140	#clock-cells = <0>;
141	compatible = "fixed-clock";
142	clock-frequency = <32768>;
143	clock-output-names = "osc32k";
144	};
145	};
146
147	soc {
148	compatible = "simple-bus";
149	#address-cells = <1>;
150	#size-cells = <1>;
151	/*
152	* map 64 bit address range down to 32 bits,
153	* as the peripherals are all under 512MB.
154	*/
155	ranges = <0 0 0 0x20000000>;
156
157	gic: interrupt-controller@01c41000 {
158	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
159	reg = <0x01c41000 0x1000>,
160	<0x01c42000 0x1000>,
161	<0x01c44000 0x2000>,
162	<0x01c46000 0x2000>;
163	interrupt-controller;
164	#interrupt-cells = <3>;
165	interrupts = <1 9 0xf04>;
166	};
167
168	timer@06000c00 {
169	compatible = "allwinner,sun4i-a10-timer";
170	reg = <0x06000c00 0xa0>;
171	interrupts = <0 18 4>,
172	<0 19 4>,
173	<0 20 4>,
174	<0 21 4>,
175	<0 22 4>,
176	<0 23 4>;
177
178	clocks = <&osc24M>;
179	};
180
181	uart0: serial@07000000 {
182	compatible = "snps,dw-apb-uart";
183	reg = <0x07000000 0x400>;
184	interrupts = <0 0 4>;
185	reg-shift = <2>;
186	reg-io-width = <4>;
187	clocks = <&osc24M>;
188	status = "disabled";
189	};
190
191	uart1: serial@07000400 {
192	compatible = "snps,dw-apb-uart";
193	reg = <0x07000400 0x400>;
194	interrupts = <0 1 4>;
195	reg-shift = <2>;
196	reg-io-width = <4>;
197	clocks = <&osc24M>;
198	status = "disabled";
199	};
200
201	uart2: serial@07000800 {
202	compatible = "snps,dw-apb-uart";
203	reg = <0x07000800 0x400>;
204	interrupts = <0 2 4>;
205	reg-shift = <2>;
206	reg-io-width = <4>;
207	clocks = <&osc24M>;
208	status = "disabled";
209	};
210
211	uart3: serial@07000c00 {
212	compatible = "snps,dw-apb-uart";
213	reg = <0x07000c00 0x400>;
214	interrupts = <0 3 4>;
215	reg-shift = <2>;
216	reg-io-width = <4>;
217	clocks = <&osc24M>;
218	status = "disabled";
219	};
220
221	uart4: serial@07001000 {
222	compatible = "snps,dw-apb-uart";
223	reg = <0x07001000 0x400>;
224	interrupts = <0 4 4>;
225	reg-shift = <2>;
226	reg-io-width = <4>;
227	clocks = <&osc24M>;
228	status = "disabled";
229	};
230
231	uart5: serial@07001400 {
232	compatible = "snps,dw-apb-uart";
233	reg = <0x07001400 0x400>;
234	interrupts = <0 5 4>;
235	reg-shift = <2>;
236	reg-io-width = <4>;
237	clocks = <&osc24M>;
238	status = "disabled";
239	};
240
241	r_wdt: watchdog@08001000 {
242	compatible = "allwinner,sun6i-a31-wdt";
243	reg = <0x08001000 0x20>;
244	interrupts = <0 36 4>;
245	};
246
247	r_uart: serial@08002800 {
248	compatible = "snps,dw-apb-uart";
249	reg = <0x08002800 0x400>;
250	interrupts = <0 38 4>;
251	reg-shift = <2>;
252	reg-io-width = <4>;
253	clocks = <&osc24M>;
254	status = "disabled";
255	};
256	};
257	};