[linux-block.git] / arch / arm / boot / dts / sun8i-h3.dtsi

/*
 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "sunxi-h3-h5.dtsi"

/ {
	cpu0_opp_table: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp@648000000 {
			opp-hz = /bits/ 64 <648000000>;
			opp-microvolt = <1040000 1040000 1300000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};

		opp@816000000 {
			opp-hz = /bits/ 64 <816000000>;
			opp-microvolt = <1100000 1100000 1300000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};

		opp@1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <1200000 1200000 1300000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clocks = <&ccu CLK_CPUX>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu0_opp_table>;
			#cooling-cells = <2>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
			clocks = <&ccu CLK_CPUX>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu0_opp_table>;
			#cooling-cells = <2>;
		};

		cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
			clocks = <&ccu CLK_CPUX>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu0_opp_table>;
			#cooling-cells = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
			clocks = <&ccu CLK_CPUX>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu0_opp_table>;
			#cooling-cells = <2>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		cma_pool: cma@4a000000 {
			compatible = "shared-dma-pool";
			size = <0x6000000>;
			alloc-ranges = <0x4a000000 0x6000000>;
			reusable;
			linux,cma-default;
		};
	};

	soc {
		system-control@1c00000 {
			compatible = "allwinner,sun8i-h3-system-control";
			reg = <0x01c00000 0x30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			sram_c: sram@1d00000 {
				compatible = "mmio-sram";
				reg = <0x01d00000 0x80000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x01d00000 0x80000>;

				ve_sram: sram-section@0 {
					compatible = "allwinner,sun8i-h3-sram-c1",
						     "allwinner,sun4i-a10-sram-c1";
					reg = <0x000000 0x80000>;
				};
			};
		};

		video-codec@01c0e000 {
			compatible = "allwinner,sun8i-h3-video-engine";
			reg = <0x01c0e000 0x1000>;
			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
				 <&ccu CLK_DRAM_VE>;
			clock-names = "ahb", "mod", "ram";
			resets = <&ccu RST_BUS_VE>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			allwinner,sram = <&ve_sram 1>;
		};

		mali: gpu@1c40000 {
			compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
			reg = <0x01c40000 0x10000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gp",
					  "gpmmu",
					  "pp0",
					  "ppmmu0",
					  "pp1",
					  "ppmmu1",
					  "pmu";
			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
			clock-names = "bus", "core";
			resets = <&ccu RST_BUS_GPU>;

			assigned-clocks = <&ccu CLK_GPU>;
			assigned-clock-rates = <384000000>;
		};
	};
};

&ccu {
	compatible = "allwinner,sun8i-h3-ccu";
};

&display_clocks {
	compatible = "allwinner,sun8i-h3-de2-clk";
};

&mmc0 {
	compatible = "allwinner,sun7i-a20-mmc";
	clocks = <&ccu CLK_BUS_MMC0>,
		 <&ccu CLK_MMC0>,
		 <&ccu CLK_MMC0_OUTPUT>,
		 <&ccu CLK_MMC0_SAMPLE>;
	clock-names = "ahb",
		      "mmc",
		      "output",
		      "sample";
};

&mmc1 {
	compatible = "allwinner,sun7i-a20-mmc";
	clocks = <&ccu CLK_BUS_MMC1>,
		 <&ccu CLK_MMC1>,
		 <&ccu CLK_MMC1_OUTPUT>,
		 <&ccu CLK_MMC1_SAMPLE>;
	clock-names = "ahb",
		      "mmc",
		      "output",
		      "sample";
};

&mmc2 {
	compatible = "allwinner,sun7i-a20-mmc";
	clocks = <&ccu CLK_BUS_MMC2>,
		 <&ccu CLK_MMC2>,
		 <&ccu CLK_MMC2_OUTPUT>,
		 <&ccu CLK_MMC2_SAMPLE>;
	clock-names = "ahb",
		      "mmc",
		      "output",
		      "sample";
};

&pio {
	compatible = "allwinner,sun8i-h3-pinctrl";
};
Commit	Line	Data
318d93bc JK	1	/*
	2	* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
0127216f	43	#include "sunxi-h3-h5.dtsi"
318d93bc JK	44
318d93bc JK	45	/ {
dceecd91 IZ	46	cpu0_opp_table: opp_table0 {
	47	compatible = "operating-points-v2";
	48	opp-shared;
	49
	50	opp@648000000 {
	51	opp-hz = /bits/ 64 <648000000>;
	52	opp-microvolt = <1040000 1040000 1300000>;
	53	clock-latency-ns = <244144>; /* 8 32k periods */
	54	};
	55
	56	opp@816000000 {
	57	opp-hz = /bits/ 64 <816000000>;
	58	opp-microvolt = <1100000 1100000 1300000>;
	59	clock-latency-ns = <244144>; /* 8 32k periods */
	60	};
	61
	62	opp@1008000000 {
	63	opp-hz = /bits/ 64 <1008000000>;
	64	opp-microvolt = <1200000 1200000 1300000>;
	65	clock-latency-ns = <244144>; /* 8 32k periods */
	66	};
	67	};
	68
318d93bc JK	69	cpus {
	70	#address-cells = <1>;
	71	#size-cells = <0>;
	72
dceecd91	73	cpu0: cpu@0 {
318d93bc JK	74	compatible = "arm,cortex-a7";
	75	device_type = "cpu";
	76	reg = <0>;
dceecd91 IZ	77	clocks = <&ccu CLK_CPUX>;
	78	clock-names = "cpu";
	79	operating-points-v2 = <&cpu0_opp_table>;
	80	#cooling-cells = <2>;
318d93bc JK	81	};
	82
	83	cpu@1 {
	84	compatible = "arm,cortex-a7";
	85	device_type = "cpu";
	86	reg = <1>;
77ad0f2e VK	87	clocks = <&ccu CLK_CPUX>;
77ad0f2e VK	88	clock-names = "cpu";
dceecd91	89	operating-points-v2 = <&cpu0_opp_table>;
77ad0f2e	90	#cooling-cells = <2>;
318d93bc JK	91	};
	92
	93	cpu@2 {
	94	compatible = "arm,cortex-a7";
	95	device_type = "cpu";
	96	reg = <2>;
77ad0f2e VK	97	clocks = <&ccu CLK_CPUX>;
77ad0f2e VK	98	clock-names = "cpu";
dceecd91	99	operating-points-v2 = <&cpu0_opp_table>;
77ad0f2e	100	#cooling-cells = <2>;
318d93bc JK	101	};
	102
	103	cpu@3 {
	104	compatible = "arm,cortex-a7";
	105	device_type = "cpu";
	106	reg = <3>;
77ad0f2e VK	107	clocks = <&ccu CLK_CPUX>;
77ad0f2e VK	108	clock-names = "cpu";
dceecd91	109	operating-points-v2 = <&cpu0_opp_table>;
77ad0f2e	110	#cooling-cells = <2>;
318d93bc JK	111	};
	112	};
	113
	114	timer {
	115	compatible = "arm,armv7-timer";
	116	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	117	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	118	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	119	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	120	};
c235edcb	121
36c4bef3 PK	122	reserved-memory {
	123	#address-cells = <1>;
	124	#size-cells = <1>;
	125	ranges;
	126
	127	cma_pool: cma@4a000000 {
	128	compatible = "shared-dma-pool";
	129	size = <0x6000000>;
	130	alloc-ranges = <0x4a000000 0x6000000>;
	131	reusable;
	132	linux,cma-default;
	133	};
	134	};
	135
c235edcb	136	soc {
626e6ee2 PK	137	system-control@1c00000 {
	138	compatible = "allwinner,sun8i-h3-system-control";
	139	reg = <0x01c00000 0x30>;
	140	#address-cells = <1>;
	141	#size-cells = <1>;
	142	ranges;
	143
	144	sram_c: sram@1d00000 {
	145	compatible = "mmio-sram";
	146	reg = <0x01d00000 0x80000>;
	147	#address-cells = <1>;
	148	#size-cells = <1>;
	149	ranges = <0 0x01d00000 0x80000>;
	150
	151	ve_sram: sram-section@0 {
	152	compatible = "allwinner,sun8i-h3-sram-c1",
	153	"allwinner,sun4i-a10-sram-c1";
	154	reg = <0x000000 0x80000>;
	155	};
	156	};
	157	};
	158
36c4bef3 PK	159	video-codec@01c0e000 {
	160	compatible = "allwinner,sun8i-h3-video-engine";
	161	reg = <0x01c0e000 0x1000>;
	162	clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
	163	<&ccu CLK_DRAM_VE>;
	164	clock-names = "ahb", "mod", "ram";
	165	resets = <&ccu RST_BUS_VE>;
	166	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	167	allwinner,sram = <&ve_sram 1>;
	168	};
	169
c235edcb GB	170	mali: gpu@1c40000 {
	171	compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
	172	reg = <0x01c40000 0x10000>;
	173	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	174	<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
	175	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	176	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	177	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	178	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
	179	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	180	interrupt-names = "gp",
	181	"gpmmu",
	182	"pp0",
	183	"ppmmu0",
	184	"pp1",
	185	"ppmmu1",
	186	"pmu";
	187	clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
	188	clock-names = "bus", "core";
	189	resets = <&ccu RST_BUS_GPU>;
	190
	191	assigned-clocks = <&ccu CLK_GPU>;
	192	assigned-clock-rates = <384000000>;
	193	};
	194	};
0127216f	195	};
318d93bc	196
0127216f AP	197	&ccu {
	198	compatible = "allwinner,sun8i-h3-ccu";
	199	};
93385367	200
d8c6f1f0 IZ	201	&display_clocks {
	202	compatible = "allwinner,sun8i-h3-de2-clk";
	203	};
	204
0127216f AP	205	&mmc0 {
	206	compatible = "allwinner,sun7i-a20-mmc";
	207	clocks = <&ccu CLK_BUS_MMC0>,
	208	<&ccu CLK_MMC0>,
	209	<&ccu CLK_MMC0_OUTPUT>,
	210	<&ccu CLK_MMC0_SAMPLE>;
	211	clock-names = "ahb",
	212	"mmc",
	213	"output",
	214	"sample";
	215	};
20d5c4e9	216
0127216f AP	217	&mmc1 {
	218	compatible = "allwinner,sun7i-a20-mmc";
	219	clocks = <&ccu CLK_BUS_MMC1>,
	220	<&ccu CLK_MMC1>,
	221	<&ccu CLK_MMC1_OUTPUT>,
	222	<&ccu CLK_MMC1_SAMPLE>;
	223	clock-names = "ahb",
	224	"mmc",
	225	"output",
	226	"sample";
	227	};
fe0a8ea1	228
0127216f AP	229	&mmc2 {
	230	compatible = "allwinner,sun7i-a20-mmc";
	231	clocks = <&ccu CLK_BUS_MMC2>,
	232	<&ccu CLK_MMC2>,
	233	<&ccu CLK_MMC2_OUTPUT>,
	234	<&ccu CLK_MMC2_SAMPLE>;
	235	clock-names = "ahb",
	236	"mmc",
	237	"output",
	238	"sample";
	239	};
fe0a8ea1	240
0127216f AP	241	&pio {
0127216f AP	242	compatible = "allwinner,sun8i-h3-pinctrl";
318d93bc	243	};